EP2966460A1 - Circuit et procédé d'échantillonnage de courant - Google Patents
Circuit et procédé d'échantillonnage de courant Download PDFInfo
- Publication number
- EP2966460A1 EP2966460A1 EP14885839.2A EP14885839A EP2966460A1 EP 2966460 A1 EP2966460 A1 EP 2966460A1 EP 14885839 A EP14885839 A EP 14885839A EP 2966460 A1 EP2966460 A1 EP 2966460A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- current
- sampling
- proportional
- source
- ldnmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 title claims abstract description 129
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0038—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude)
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Definitions
- the present disclosure relates to current sampling techniques in the field of circuit design, and in particular to a current sampling circuit and method.
- a feedback A op ⁇ g m ⁇ 4 ⁇ R o
- the current in the power transistor M1 is firstly mirrored into the sampling transistors M2 and M3, after passing through the close loop negative feedback circuit consisting of the operational amplifier, the transistor M4 and the resistors R1 and R2, the mirrored current is output as a sampling current.
- the clamping effect of the operational amplifier is used to ensure that a first input voltage V n is equal to a second input voltage V p so that the output sampling current lout is the same as the current flowing through the sampling transistors M2 and M3, thereby the current in the power transistor M1 can be sampled stably and accurately; if the current in the power transistor M1 changes direction, the output sampling current also changes direction, thereby implementing accurate sampling of current in both directions.
- the current sampling scheme in the related arts has the following disadvantages: 1) it is disadvantageous for applications in large-scale circuits having a high integration density; 2) the current sampling circuit is not energy-saving due to its high power consumption.
- Embodiments of the disclosure are intended to provide a current sampling circuit that has an integrated circuit structure, a low power consumption and a low cost and can output a stable and accurate sampling current, and a corresponding current sampling method.
- An embodiment of the disclosure provides a current sampling circuit including a proportional current output circuit and a full differential common mode negative feedback circuit, specifically, the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit; and the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current.
- the power device may be implemented by a first Lateral Diffusion N-channel Metal-Oxide-Semiconductor (LDNMOS); the proportional current output circuit may include a second LDNMOS, a third LDNMOS, a fourth LDNMOS and a fifth LDNMOS; and the full differential common mode negative feedback circuit may include a first P-channel Metal-Oxide-Semiconductor (PMOS), a second PMOS, a third PMOS, a fourth PMOS, a first resistor, a second resistor, a second reference current source, a third reference current source, a fourth reference current source, and a fifth reference current source.
- PMOS Metal-Oxide-Semiconductor
- the drain of the second LDNMOS is connected with the drain of the fourth LDNMOS and a power supply
- the gate of the second LDNMOS is connected with the gate of the first LDNMOS, the gate of the third LDNMOS and a gate driving voltage (hdrv_in from a gate driving circuit)
- the source of the second LDNMOS is connected respectively with the drain of the third LDNMOS and the drain of the fifth LDNMOS
- the source of the third LDNMOS is connected respectively with the source of the first LDNMOS and a first end of the first reference current source
- the gate of the fourth LDNMOS is connected with the gate of the fifth LDNMOS
- the source of the fourth LDNMOS is connected respectively with the source of the first PMOS and the source of the third PMOS in the full differential common mode negative feedback circuit
- the source of the fifth LDNMOS is connected respectively with the source of the second PMOS and the source of the fourth PMOS in the full differential common mode negative feedback circuit
- an embodiment of the disclosure further provides a current sampling method, and the method includes:
- the step that a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current may include:
- the step that the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current may include:
- the current sampling circuit and method provided by the embodiments of the disclosure have the following advantages:
- a current output from a power device is calculated according to a preset proportion to obtain a first proportional current and a second proportional current; and the first proportional current and the second proportional current are shunted respectively using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and the first sampling current and the second sampling current are output constantly.
- An embodiment of the disclosure provides a current sampling circuit for sampling current of a power device, as shown in Fig. 2 , the current sampling circuit includes a proportional current output circuit 201 and a full differential common mode negative feedback circuit 202,
- the proportional current output circuit 201 is configured to calculate a current output from a power device according to a preset proportion to obtain a proportional current, and to output the proportional current to the full differential common mode negative feedback circuit 202; and the full differential common mode negative feedback circuit 202 is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current.
- the power device may be implemented by a Negative channel Metal Oxide Semiconductor (NMOS), a Positive channel Metal Oxide Semiconductor (PMOS), a Lateral Diffusion NMOS (LDNMOS), a Lateral Diffusion PMOS (LDPMOS), and a PNP transistor or an NPN transistor that has power output function; preferably, the embodiment of the disclosure is implemented by an LDNMOS, and a first LDNMOS M 1 shown in Fig. 3 is namely a power device.
- NMOS Negative channel Metal Oxide Semiconductor
- PMOS Positive channel Metal Oxide Semiconductor
- LDNMOS Lateral Diffusion NMOS
- LDPMOS Lateral Diffusion PMOS
- PNP transistor or an NPN transistor that has power output function preferably, the embodiment of the disclosure is implemented by an LDNMOS, and a first LDNMOS M 1 shown in Fig. 3 is namely a power device.
- the proportional current output circuit 201 includes a second LDNMOS M 2 , a third LDNMOS M 3 , a fourth LDNMOS M 4 and a fifth LDNMOS M 5 ;
- the full differential common mode negative feedback circuit 202 includes a first PMOS M 6 , a second PMOS M 7 , a third PMOS M 8 , a fourth PMOS M 9 , a first resistor R 1 , a second resistor R 2 , a second reference current source I 2 , a third reference current source I 3 , a fourth reference current source I 4 , and a fifth reference current source I 5 .
- transistors M 2 , M 3 , M 4 , M 5 in the proportional current output circuit 201 are implemented by an LDMOS transistor of the same type as that of power transistor M 1 , with a gate voltage being a gate driving voltage (hdrv_in output from a gate driving circuit), thus respective transistors operate in the linear region and are equivalent to resistors, and the maximum withstanding voltage of each of the transistors M 1 , M 2 , M 3 , M 4 , M 5 is 18V.
- transistors M 6 , M 7 , M 8 , M 9 in the full differential common mode negative feedback circuit 202 are implemented by a PMOS transistor with a maximum withstanding voltage of 20V.
- transistors in the full differential common mode negative feedback circuit 203 can also be implemented, as required, by NMOS, NPN or PNP transistors.
- the drain of the second LDNMOS M 2 is connected with the drain of the fourth LDNMOS M 4 and a power supply V in
- the gate of the second LDNMOS M 2 is connected with the gate of the first LDNMOS M 1
- the gate of the third LDNMOS and an output hdrv_in of a gate driving circuit namely driven by a voltage signal output from the gate driving circuit
- the source of the second LDNMOS M 2 is connected respectively with the drain of the third LDNMOS M 3 and the drain of the fifth LDNMOS M 5
- the source of the third LDNMOS M 3 is connected respectively with the source of the first LDNMOS M 1 and one end of the first reference current source I 1
- the gate of the fourth LDNMOS M 4 is connected with the gate of the fifth LDNMOS M 5
- the source of the fourth LDNMOS M 4 is connected with the gate of the fifth LDNMOS M 5 , the source of the fourth
- the operation principle of the current sampling circuit is as follows.
- the power device i.e., a first LDNMOS M 1 outputs I power to the proportional current output circuit 201
- the proportional current output circuit 201 calculates the output current I power according to a preset proportion to obtain a first proportional current and a second proportional current and outputs them to the full differential common mode negative feedback circuit 202.
- the gate voltage of the transistors M 1 , M 2 , M 3 , M 4 , M 5 are driven by hdrv_in, thus these transistors operate in the linear region and are equivalent to resistors, and each of the transistors M 1 , M 2 , M 3 , M 4 , M 5 has a maximum withstanding voltage of 18 V since the voltage V in input by the power supply has a maximum value of 18 V.
- the full differential common mode negative feedback network is equivalent to a negative feedback network including an operational amplifier, as shown in Fig. 4 ; wherein a circuit consisting of transistors M 6 , M 7 and resistors R 1 , R 2 is equivalent to an operational amplifier, points C and D are taken as inputs of the operational amplifier, and the two sampling currents are taken approximately as being connected to the input and output of the operational amplifier.
- the current sampling circuit Due to the clamping effect of the operational amplifier, its inputs C and D have a same voltage, the first sampling current I sense+ from the output is fed back to the input C of the operational amplifier via the transistor M 8 , the second sampling current I sense- from the output is fed back to the input D of the operational amplifier via the transistor M 9 , thus an effect of an operational amplifier feedback network is resulted, and it is possible to provide the current sampling circuit with a stable gain, therefore, the current sampling circuit according to the embodiment of the disclosure occupies smaller pattern area, has a higher integration density and lower cost.
- the proportional current output circuit 201 and the full differential common mode negative feedback circuit 202 can be applied to a charger chip of a power supply management chip.
- the current sampling circuit in the embodiment of the disclosure can also be of a folding structure, the folding current sampling circuit has a similar principle as that of the above current sampling circuit, and it has flexible applications, as shown in Fig. 5 , the current sampling circuit includes a proportional current output circuit 501 and a full differential common mode negative feedback circuit 502; specifically, the proportional current output circuit 501 includes a second LDNMOS M 2 , a third LDNMOS M 3 , a fourth LDNMOS M 4 , a fifth LDNMOS M 5 , a sixth LDNMOS M 6 , a seventh LDNMOS M 7 , and a eighth LDNMOS M 8 ; the full differential common mode negative feedback circuit 502 includes a first PMOS M 9 , a second PMOS M 10 , a third PMOS M 11 , a fourth PMOS M 12 , a fifth PMOS M 13 , a sixth PMOS M 14 , a first resistor R 1 , a second resistor R 2 , a
- transistors M 2 , M 3 , M 4 , M 5 , M 6 , M 7 , M 8 in the proportional current output circuit 201 are implemented by an LDMOS transistor of the same type as that of power transistor M 1 , with a gate voltage being a gate driving voltage hdrv_in, thus respective transistors operate in the linear region and are equivalent to resistors, and each of the transistors is implemented by a transistor with the maximum withstanding voltage of 18 V.
- voltages of transistors M 9 , M 10 , M 11 , M 12 , M 13 , M 14 in the full differential common mode negative feedback circuit are all maintained at a voltage of 20 V; voltages of transistors M 19 , M 20 , M 21 , M 22 , M 23 , M 24 can be adjusted appropriately to ensure a benchmark bias current I b desired in the full differential common mode negative feedback circuit 502, and the benchmark bias current I b providing M 10 , M 11 with a quiescent operating point is as low as 10 to 20 ⁇ A.
- transistors in the full differential common mode negative feedback circuit 502 can also be implemented, as required, by NMOS, NPN or PNP transistors.
- the drain of the transistor M 2 is connected with a power supply V in
- the gate of the transistor M 2 is connected with the gate of the transistor M 1 , the gate of the transistor M 3 , the gate of the transistor M 4 , the gate of the transistor M 5 and a driving voltage hdrv_in
- the source of the transistor M 2 is connected with the drain of the transistor M 3 and the drain of the transistor M 6 in a current mirror circuit 502
- the source of the transistor M 3 is connected with the source of the transistor M 4 and one end of the first reference current source I 1
- the gate of the transistor M 6 is connected with the gate of the transistor M 7 and the gate of transistor M 8
- the source of the transistor M 6 is connected with the source of the transistor M 9 and the source of the transistor M 13 in the full differential common mode negative feedback circuit 502
- the source of the transistor M 7 is connected with the
- the current of the transistor M 1 in the folding current sampling circuit is scaled twice through the proportional current output circuit 501, the output current becomes smaller than that of the above current sampling circuit, thus the power consumption is lowered further;
- the transistors M 10 , M 11 , M 13 , M 14 , the first resistor R 1 and the second resistor constitute a full differential common mode negative feedback network;
- the transistors M 9 , M 20 , M 21 , M 22 , M 23 , M 24 constitute a folding structure, and the folding current sampling circuit according to the embodiment of the disclosure can meet application demand in low voltage field.
- current sampling circuits shown in Fig. 2 , 3 or 5 can be applied in devices or apparatuses that need current sampling.
- an embodiment of the disclosure further provides a current sampling method, since the principle of the method is similar to that of the current sampling circuit, for the implementation of the method and its principle, please refer to the implementation of the circuit and its corresponding principle, and duplicated content thereof will be omitted.
- the current sampling method includes:
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410134447.8A CN104977450B (zh) | 2014-04-03 | 2014-04-03 | 一种电流采样电路及方法 |
PCT/CN2014/090733 WO2015149521A1 (fr) | 2014-04-03 | 2014-11-10 | Circuit et procédé d'échantillonnage de courant |
Publications (3)
Publication Number | Publication Date |
---|---|
EP2966460A1 true EP2966460A1 (fr) | 2016-01-13 |
EP2966460A4 EP2966460A4 (fr) | 2016-07-20 |
EP2966460B1 EP2966460B1 (fr) | 2021-03-10 |
Family
ID=54239367
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP14885839.2A Active EP2966460B1 (fr) | 2014-04-03 | 2014-11-10 | Circuit et procédé d'échantillonnage de courant |
Country Status (4)
Country | Link |
---|---|
US (1) | US9766274B2 (fr) |
EP (1) | EP2966460B1 (fr) |
CN (1) | CN104977450B (fr) |
WO (1) | WO2015149521A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3477320A1 (fr) * | 2017-10-23 | 2019-05-01 | Contemporary Amperex Technology Co., Limited | Appareil de traitement de signaux d'une boucle haute tension, détecteur, dispositif de batterie et véhicule |
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JP2017063300A (ja) * | 2015-09-24 | 2017-03-30 | エスアイアイ・セミコンダクタ株式会社 | 入力回路 |
CN106908647A (zh) * | 2015-12-23 | 2017-06-30 | 深圳市盛德金科技有限公司 | 电流检测电路 |
CN106415282B (zh) * | 2016-08-16 | 2019-06-21 | 深圳市汇顶科技股份有限公司 | 一种电流采样保持电路及信号采集系统 |
CN112946351B (zh) * | 2019-12-11 | 2023-04-11 | 圣邦微电子(北京)股份有限公司 | 一种负向续流电流监测电路 |
CN111308161B (zh) * | 2020-03-10 | 2022-04-19 | 福州瑞芯微电子股份有限公司 | 一种电压采样电路及方法 |
US20230275502A1 (en) * | 2022-02-25 | 2023-08-31 | Stmicroelectronics Asia Pacific Pte Ltd | Vertical metal sensing method for dc-dc converter |
CN115184663B (zh) * | 2022-08-17 | 2023-06-09 | 上海紫鹰微电子有限公司 | 双向高精度nmos功率管电流采样电路及方法 |
CN115656609B (zh) * | 2022-12-28 | 2023-04-28 | 苏州博创集成电路设计有限公司 | 一种电感电流采样电路 |
CN117310253A (zh) * | 2023-09-20 | 2023-12-29 | 上海帝迪集成电路设计有限公司 | 一种宽范围高精度电流检测电路及其检测方法 |
CN117388561B (zh) * | 2023-12-07 | 2024-03-01 | 苏州锴威特半导体股份有限公司 | 一种宽电压范围的电流检测电路和开关电源 |
CN117517753B (zh) * | 2024-01-03 | 2024-03-29 | 江苏帝奥微电子股份有限公司 | 采用电阻采样且兼容p、n型功率管的电流采样电路 |
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2014
- 2014-04-03 CN CN201410134447.8A patent/CN104977450B/zh active Active
- 2014-11-10 EP EP14885839.2A patent/EP2966460B1/fr active Active
- 2014-11-10 US US14/773,758 patent/US9766274B2/en active Active
- 2014-11-10 WO PCT/CN2014/090733 patent/WO2015149521A1/fr active Application Filing
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3477320A1 (fr) * | 2017-10-23 | 2019-05-01 | Contemporary Amperex Technology Co., Limited | Appareil de traitement de signaux d'une boucle haute tension, détecteur, dispositif de batterie et véhicule |
US10797674B2 (en) | 2017-10-23 | 2020-10-06 | Contemporary Amperex Technology Co., Limited | Signal acquisition device for high-voltage loop, detector, battery device, and vehicle |
Also Published As
Publication number | Publication date |
---|---|
EP2966460B1 (fr) | 2021-03-10 |
EP2966460A4 (fr) | 2016-07-20 |
WO2015149521A1 (fr) | 2015-10-08 |
CN104977450B (zh) | 2019-04-30 |
US9766274B2 (en) | 2017-09-19 |
CN104977450A (zh) | 2015-10-14 |
US20160109487A1 (en) | 2016-04-21 |
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