US9496487B2 - Vertical hall device - Google Patents

Vertical hall device Download PDF

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US9496487B2
US9496487B2 US14/794,439 US201514794439A US9496487B2 US 9496487 B2 US9496487 B2 US 9496487B2 US 201514794439 A US201514794439 A US 201514794439A US 9496487 B2 US9496487 B2 US 9496487B2
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contacts
contact
hall device
vertical hall
deep
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US20160013399A1 (en
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Sasa Dimitrijevic
Radivoje Popovic
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Senisens Ag
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Senis AG
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    • H01L43/065—
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
    • G01R33/07—Hall effect devices
    • G01R33/077—Vertical Hall-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/101—Semiconductor Hall-effect devices

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  • the invention relates to a vertical Hall device fabricated by an IC (integrated circuits) technology of integrated circuits, for example a CMOS technology.
  • a Hall-effect device or Hall device in short, also known as a Hall element or Hall sensor, is a device that converts the component to be measured of a magnetic field vector into a voltage.
  • Hall devices are currently the most used magnetic sensors. They are commercially available both as discrete devices and integrated circuits incorporating a combination of a Hall device, current source, amplifier, and other signal conditioning electronic circuits. The principle of operation and basic technology of Hall devices are described in the book by R. S. Popovic, entitled “HALL EFFECT DEVICES”, Institute of Physics Publishing, Bristol and Philadelphia 2004.
  • a horizontal Hall device has the form of a plate, which is usually disposed in parallel with the active chip surface, and is sensitive to a magnetic field running perpendicular to the active chip surface.
  • a vertical Hall device usually does not have a plate-like geometry, but it behaves like a plate disposed vertically with respect to the active chip surface, and it is sensitive to a magnetic field running parallel to the active chip surface.
  • FIG. 1 shows a cross-section
  • FIG. 2 shows a plan view of a vertical Hall device 1 of the prior art.
  • axes x and y oriented orthogonally to each other are used to indicate the direction in which a “length” or a “width” is measured. Any distance along the x-axis, such as L in FIG. 2 , will be called a length; and any distance along the y-axis, such as W in FIG. 2 , will be called a width.
  • This convention will be applied independently of the ratio of the length and the width of the structure under consideration.
  • the vertical Hall device 1 is fabricated with an IC (integrated circuit) technology: It has an N-type region 2 which is implanted into a P-type region 3 which may be a P-type substrate. Four heavily doped N + regions arranged along a straight line 8 are disposed at the surface of the N-well NW and form electrical contacts 4 to 7 .
  • the N-well NW has a depth d NW
  • the N + contacts have a depth d + .
  • the vertical Hall device 1 has a length L and a width W. Two non-neighboring contacts of the vertical Hall device 1 are used as input terminals and the other two non-neighboring contacts are used as output terminals.
  • the contacts 4 and 6 can be used as the input terminals and the contacts 5 and 7 as the output terminals, or vice versa.
  • the electrical resistances R 1 , R 2 , R 3 and R 4 between the contacts 4 to 7 of the Hall device 1 can be represented by a Wheatstone bridge as shown in FIG. 3 .
  • the Hall device 1 is supplied with a constant current I in , or with a constant voltage V in via the input terminals. If the Hall device 1 is exposed to a magnetic field having a component perpendicular to the effective device plane, then the electromotive force of the Hall effect acts between the output terminals. The voltage V out , which appears between the output terminals, is called the output voltage of the Hall device 1 .
  • V out V off +S I ⁇ I in ⁇ B
  • V out V off +S V ⁇ V in ⁇ B
  • V off denotes an offset voltage
  • S I denotes the current-related sensitivity
  • B denotes the component of a magnetic field perpendicular to the effective device plane
  • S V denotes the voltage-related sensitivity
  • a Hall device In order to be suitable for a practical application as a magnetic field sensor, a Hall device should have the following main characteristics:
  • the requirements a) through c) will be met if the four resistances R 1 , R 2 , R 3 , R 4 are all approximately equal.
  • the voltage-related magnetic sensitivity (requirement d) is a complex function of the characteristics of the material used for the Hall device and of its geometry. But roughly speaking, the requirement d) is easier to meet if the resistances R 1 , R 2 , R 3 , R 4 have equal values and are “short”. Here “short” means that the length of a resistor is not greater than the square root of its cross-sectional area.
  • the flicker noise (requirement e) depends much on the quality of the material used for the Hall device, and on the quality and protection of its surface.
  • any two-dimensional (planar) horizontal Hall device can be transformed by a mathematical technique known as conformal mapping into a vertical Hall device. But the calculated dimensions of the contacts are nearly impossible to meet in reality.
  • a vertical Hall device was first described in U.S. Pat. No. 4,782,375. This device has five contacts arranged along a line, the two outermost of them being short-circuited. When designed properly, the five-contact vertical Hall device may meet the requirements a), d), and e); but it is much more difficult to meet the requirements b) and c) with the known five-contact structures.
  • the four-contact vertical Hall device disclosed in U.S. Pat. No. 5,057,890 intrinsically meets the exchangeability requirement c). But when implemented by using IC technology, the four-contact vertical Hall device usually has a very big offset and a low voltage-related magnetic sensitivity; that is, the requirements a) and d) are not met.
  • the invention concerns a four-contact or five-contact vertical Hall device with the contacts arranged along a straight line on the surface of a deep N-well.
  • the four-contact vertical Hall device has two inner contacts and two outer contacts. The contacts are formed of highly doped N + regions.
  • the five-contact vertical Hall device additionally has a central contact placed between the two inner contacts.
  • the two outer contacts of the five-contact vertical Hall device are short-circuited, e.g., by a metal line which directly connects the two outer contacts.
  • the two inner contacts have a same length and a same width and the two outer contacts have a same length and a same width.
  • Both, the four-contact vertical Hall device and the five-contact vertical Hall device are symmetrical with respect to a first symmetry line and a central symmetry plane which extends orthogonally to the first symmetry line.
  • the object of the invention is to develop a vertical Hall device, which fulfills all the above requirements a) through e) and which can be fabricated by using the process of a commercially available silicon CMOS integrated circuit technology.
  • the invention proposes a novel layout of integrated four- and five-contact vertical Hall-effect devices, which allows for equating the values of the resistances R 1 , R 2 , R 3 , R 4 as well as for achieving high magnetic sensitivity of the Hall device without the need to add separate fabrication steps to an existing silicon CMOS technology.
  • the invention proposes new designs for vertical Hall devices as follows which reduce the resistance R 4 and/or increase the resistance R 2 (The reference numbers refer to FIGS. 1 and 2 ):
  • the effective width of the outer contacts is bigger than the effective width of the inner contacts.
  • the resulting effective width of the vertical Hall device along its length is therefore non-uniform, smaller near the inner contacts and larger toward the outer contacts. This design reduces the resistance R 4 between the outer contacts.
  • a P + stripe is disposed between the inner contacts 5 and 6 .
  • the P + stripe does not touch the N + regions of the inner contacts.
  • the P + stripe is a heavily doped P + area.
  • the length of the P + stripe is selected so that its distance to the inner contacts is smaller than the minimum distance allowed by the design rules of the used IC technology. This design increases the resistance R 2 between the inner contacts.
  • the resistance R 4 is reduced according to the first embodiment by making the effective width of the outer contacts bigger than the effective width of the inner contacts and the resistance R 2 is increased according to the second embodiment by disposing a P + stripe between the inner contacts.
  • the effective width of the outer contacts is bigger than the effective width of the inner contacts and the effective width of the central contact is the same as or, preferably, less than the effective width of the inner contacts.
  • the resulting effective width of the vertical Hall device along its length is non-uniform, smaller near the central contact and larger toward the outer contacts. This design reduces the resistance R 4 between an outer contact and the inner contact that is farthest away from this outer contact.
  • a P + stripe is disposed between the central contact and each of its neighbouring inner contacts.
  • the two P + stripes do not touch the N + areas of the neighbouring contacts.
  • the length of the two P + stripes is preferably selected so that their distance to the neighbouring N + contacts is smaller than the minimum distance allowed by the design rules of the used IC technology. This design increases resistances between the inner contacts and the central contact.
  • the P + stripes of this embodiment may be also added to the vertical Hall device of the first embodiment.
  • the effective width of the inner contacts may be defined by the course of an inner edge of an additional deep P-well ring.
  • the width of the opening of the deep P-well ring which is enclosed by the inner edge of the deep P-well ring is bigger at the outer contacts than as at the inner contacts.
  • the deep P-well ring has a depth that is less than the depth of the deep N-well. Because the lateral diffusion of the deep P-well ring is smaller than the lateral diffusion of the deep N-well ring, the shape of the active zone contributing most to the magnetic sensitivity of the vertical Hall device is better defined.
  • the term “effective width” of a contact has the meaning that it is not the width of the contact at the surface of the N+ region that counts but the width of the area where the deep N-well and the highly doped N + region forming the contact merge into one another.
  • variable width of the vertical Hall device of the invention along its length is different from all known designs of prior art vertical Hall devices, where the width W is constant as illustrated in FIG. 2 .
  • the width W of the vertical Hall device corresponds to the thickness of a conventional horizontal Hall device.
  • the horizontal Hall devices always have a uniform thickness of the active layer. Obviously, the uniformity of the width W of the vertical Hall devices has been considered a rule by analogy with the horizontal Hall devices. The invention breaks with this rule.
  • variable width of the vertical Hall device of the invention along its length means that the active zone of the Hall device is significantly three-dimensional, whereas the active zone of the vertical Hall devices of the prior art is essentially two-dimensional (the active zone lies in the plane XZ of FIG. 3 ).
  • the shallow P + stripe (or stripes) eliminates some negative effects originating from the three-dimensional structure of the N + contacts, and makes them behave like two-dimensional contacts (which is in the plane XY of FIG. 3 ).
  • the essence of the invention is the improvement of the characteristics of vertical Hall devices by A) transforming some parts of its active zone from a two dimensional structure into a three dimensional structure, and B) transforming some other parts of its active zone from a three dimensional structure into a two dimensional structure. The best results are achieved when the measures A) and B) are combined.
  • a vertical Hall device has a deep N-well, two inner contacts and two outer contacts disposed at a surface of the deep N-well and arranged along a straight symmetry line, wherein the two inner contacts have a same length and a same effective width and the two outer contacts have a same length and a same effective width, wherein the lengths are measured along the straight symmetry line and the widths are measured perpendicularly to the straight symmetry line, and wherein the contacts are arranged symmetrically with respect to a central symmetry plane, and wherein the effective width of the outer contacts is bigger than the effective width of the inner contacts.
  • the vertical Hall device may have a P + stripe is disposed between the inner contacts and wherein the P + stripe is separated from the inner contacts by a distance.
  • the vertical Hall device may further comprise a central contact disposed between the inner contacts.
  • the vertical Hall device may further comprise a P + stripe disposed between the central contact and the one of the inner contacts and a further P + stripe disposed between the central contact and the other of the inner contacts, wherein the two P + stripes are separated from the central contact and the respective neighbouring inner contact by a distance.
  • the vertical Hall device may further comprise a deep P-well ring, wherein an inner edge of the deep P-well ring defines the effective width of the inner contacts and, if applicable, the effective width of the central contact.
  • FIG. 1 shows a cross-section of a four-contact vertical Hall device according to the prior art
  • FIG. 2 shows a plan view of the four-contact vertical Hall device according to the prior art
  • FIG. 3 illustrates the electrical equivalent circuit of a Hall device
  • FIG. 4 shows a plan view of a first embodiment of a four-contact vertical Hall device according to the invention
  • FIG. 5 shows a plan view and two cross-sections of a second embodiment of a four-contact vertical Hall device according to the invention
  • FIG. 6 shows a plan view of a third embodiment of a four-contact vertical Hall device according to the invention.
  • FIG. 7 shows a cross-section of a fourth embodiment of a four-contact vertical Hall device according to the invention.
  • FIG. 8 shows a cross-section of an embodiment of a five-contact vertical Hall device
  • FIG. 9 shows a plan view of another embodiment of a five-contact vertical Hall device according to the invention.
  • FIG. 4 shows a plan view of a first embodiment of a four-contact vertical Hall device 1 according to the invention.
  • the vertical Hall device 1 is manufactured for example by the well-known CMOS technology and comprises a deep N-well NW embedded in a low-doped P-type substrate 3 (with substrate doping PS).
  • the deep N-well NW has preferably a rectangular shape of length L and width W.
  • the vertical Hall device 1 has four electrical contacts 4 - 7 disposed at the surface of the N-well NW and arranged along a first symmetry line 8 and symmetrically with respect to a symmetry plane 9 .
  • the symmetry line 8 is a straight line and runs orthogonally to the symmetry plane 9 .
  • the electrical contacts 4 - 7 are formed of highly doped N + regions which are contacted in conventional manner by metal lines (not shown).
  • the electrical contacts 4 - 7 have approximately rectangular shapes.
  • the inner contacts 5 , 6 have a same length 1 6 and a same width w 2 and the outer contacts 4 , 5 have a same length 1 7 and a same width w 4 .
  • the width w 2 of the inner contacts 5 and 6 is smaller than the width w 4 of the outer contacts 4 and 5 , namely: w 2 ⁇ w 4 (3)
  • the effective width of the vertical Hall device along its length is now highly non-uniform: in the vicinity of the inner contacts 5 and 6 the width of the vertical Hall device 1 is much smaller than the width of the vertical Hall device 1 in the vicinity of the outer contacts 4 , 7 .
  • the influence of these facts on the values of the resistances R 1 to R 4 can be estimated by comparing the planar shapes of the resistances in FIGS. 1, 2 and 4 : according to the prior art ( FIGS. 1 and 2 ), all four resistances have—seen in plan view—equal widths; whereas according to the invention ( FIG.
  • the regions of the resistances R 1 to R 4 in FIG. 4 are of three-dimensional nature, with complicated current distributions, they can be approximated by simple shapes: in plan view, the resistances R 1 and R 3 appear as trapezoides having a middle width w I , and the resistances R 2 and R 4 appear as rectangles having widths w 2 and w 4 , respectively, with w 2 ⁇ w 4 .
  • R 4 >>R 2 , i.e., R 4 /R 2 >>1. If the length L and all the other lengths of the vertical Hall devices shown in FIGS.
  • variable thickness also has a beneficial influence on the ratio of the resistances R 1 and R 3 with the resistances R 2 and R 4 .
  • FIG. 5 shows a plan view a) and two cross-sections b) and c) of a second embodiment of a four-contact vertical Hall device 1 according to the invention.
  • the design of this vertical Hall device differs from the vertical Hall device 1 shown in FIG. 4 in that the effective width of the inner contacts 5 and 6 is defined by an additional appropriately shaped P-well ring PW and not by the nominal width of the N + regions.
  • the P-well ring PW is made of a moderately doped P-type area.
  • the average doping of the N + regions, deep P-well and deep N-well is chosen such that Doping N + >>Doping PW >>Doping NW (5) Therefore, when two or more of these layers overlap, the layer with the highest doping dominates.
  • the plan view illustrated in FIG. 5 a ) shows that
  • the width of the N + regions at the surface of the N-well NW is equal for all N + regions but that the width of the inner contacts 5 and 6 in the depth ranging from d + to d PW is smaller than the width of the outer contacts 4 and 7 in this depth range.
  • This facilitates contacting the N + regions with metal lines (not shown), which occurs at the surface of the device, but reduces the effective width of the inner contacts 5 and 6 .
  • the effective width of a contact is the width of the area where the N + region contacts the deep N-well NW.
  • FIG. 5 a illustrates the size of the contacts 4 to 7 at the surface of the chip while the hatched area inside the borderline illustrates the effective contact area at the depth d PW below the surface of the chip.
  • the effective width is therefore smaller for the inner contacts 5 and 6 than for the outer contacts 4 and 7 .
  • FIG. 5 b ) and 5 c ) show the cross sections of the vertical Hall device 1 along the lines S 1 and S 2 shown in FIG. 5 a ), respectively.
  • the depths d + and d PW of the N + regions and the deep P-well ring PW are chosen so that d + ⁇ d PW .
  • the doping profiles shown in FIG. 5 b ) and c) illustrate that the effective width w 2 of the contacts 5 and 6 is smaller than the effective width w 4 of the contacts 4 and 7 .
  • the shape of the inner edge 11 of the P-well ring PW is chosen so that P-well ring PW channels the current flowing between the input terminals into the areas denoted in FIG. 5 a ) by A 1 , A 2 , A 3 and A 4 .
  • This is indicated by the facts that the width of the electrical contacts between the N + regions of the inner contacts 5 , 6 and of the adjacent part of the deep N-well NW are small—see w 2 in FIG. 5 b ) and that the width of the contacts between the N + regions of the outer contacts 4 , 7 and of the adjacent part of the deep N-well NW are large—see w 4 in FIG. 5 c ).
  • the width of the resistance R 4 is essentially given by the width w of the deep N-well NW, as indicated in FIG. 5 c ). So in spite of the fact that the distance between the outer contacts 4 and 7 is larger than the distance between the inner contacts 5 and 6 , since the widths of the conductive regions of the deep N-well NW between these pairs of contacts are also different with a convenient proportion, namely w 4 >w 2 , the resistances between these two pairs of contacts can be made similar, that is R 4 ⁇ R 2 .
  • the application of the additional deep P-well ring PW of the described shape helps achieving the equality of the resistances R 1 , R 2 , R 3 and R 4 . Moreover, forcing the current between the inner contacts 5 and 6 into a channel of narrow width w 2 results in increasing the current-related sensitivity of the vertical Hall device 1 .
  • FIG. 6 shows a plan view of a third embodiment of a four-contact vertical Hall device according to the invention.
  • the only difference with respect to the second embodiment shown in FIG. 5 a ) is a different shape of the inner edge 11 of the deep P-well ring PW. But the essential features of the embodiments shown in FIGS. 5 and 6 are the same.
  • FIG. 7 shows a cross-section of a fourth embodiment of a four-contact vertical Hall device 1 according to the invention.
  • the vertical Hall device 1 has a P + stripe 10 disposed between the N + regions of the inner contacts 5 and 6 .
  • the P + stripe 10 is implemented by using a shallow highly doped P-type layer having a depth approximately equal to the depth d + of the N + layer.
  • the P + stripe 10 has a length L P+ which is chosen such that the P + stripe 10 does not touch the neighbouring contacts 5 or 6 and 12 , i.e. the P + stripe 10 and the inner neighbouring contacts 5 or 6 and 12 are separated by distances L P5 and L P6 , respectively.
  • the separation between the P + region of the P + stripe 10 and the N + regions of the neighbouring contacts 5 or 6 and 12 is needed in order to avoid a tunneling current between these regions. Since the P + stripe 10 is surrounded by N-type material, it is isolated from it by a depletion layer. This depletion layer prohibits a lateral current to flow between the adjacent side walls of the N + regions of the contacts 5 or 6 and 12 . In other words, the conduction path indicated by the resistance R 2 ′ in FIG. 2 is eliminated. By doing so, the resulting resistance R b between the inner contact 5 or 6 and the central contacts 12 increases and it becomes easier to equate the resistances R a and R b .
  • a deep P-well PW shaped as shown in FIGS. 5 and 6 may be used to define the width of the active zone and also the width of the contacts 5 and 6 or of all contacts 4 to 7 .
  • a well designed four-contact integrated vertical Hall device should have a very small distance 1 2 between the inner contacts 5 and 6 .
  • This requirement makes impossible the realization of the P + region 10 and the gaps L P5 and L P6 while respecting the design rules of a given CMOS technology.
  • the deep N-well NW can be a ring that is shaped like the deep P-well ring PW.
  • five-contact vertical Hall elements can be designed straightforward in an analogous way in order to reduce the respective resistances R a , R d ; and/or to increase the resistances R b and R c see FIG. 8 for these resistances.
  • FIG. 8 shows a cross-section of a five-contact vertical Hall device 1 .
  • the five-contact vertical Hall device 1 has a deep N-well NW, two inner contacts 5 , 6 and two outer contacts 4 , 7 and a central contact 12 disposed between the inner contacts 5 and 6 .
  • the contacts 4 to 7 and 12 are disposed at a surface of the deep N-well NW and arranged along a straight symmetry line.
  • the two inner contacts 5 and 6 have a same length and a same width and the two outer contacts 4 and 7 have a same length and a same width.
  • the inner contacts 5 and 6 and the outer contacts 4 and 7 are disposed symmetrically with respect to the central contact 12 .
  • the two outer contacts 4 and 7 are short-circuited, e.g.
  • the metal line 13 serves then as one of the terminals of the Hall device as it short circuits the contacts 4 and 7 .
  • the contact 12 and the metal line 13 are used as input terminals and the contacts 5 and 6 as output terminals, or the contacts 5 and 6 are used as input terminals and the contact 12 and the metal line 13 as output terminals.
  • the resistances Ra, Rb, Rc and Rd symbolize the electrical resistances between the said terminals of the device.
  • FIG. 8 illustrates an embodiment of the five-contact vertical Hall device 1 according to the invention wherein a P + stripe 10 is disposed between each of the inner contacts 5 and 6 and the central contact 12 .
  • the P + stripes 10 are separated from the respective neighbouring inner contact 5 , 6 and the central contact 12 by a distance.
  • the P + stripes 10 increase the resistance R b between the contacts 5 and 12 , and the resistance R c between the contacts 12 and 6 , while keeping a small distance 1 2 , as determined by conformal mapping.
  • a deep P-well PW may be used to define the width of the active zone and also the width of the contacts 5 , 6 and 12 or 4 to 7 and 12 .
  • the effective width w 4 of the outer contacts 4 , 7 is bigger than the effective width of the inner contacts 5 , 6 which is slightly larger than w 2 .
  • This can be achieved by making the width of the N + regions of the inner contacts 5 and 6 and the central contact 12 smaller than the width of the N + regions of the outer contacts 4 and 7 analogously to the embodiment of the four-contact vertical Hall device 1 shown in FIG. 4 , or, as shown in FIG. 9 , by adding a deep P-well ring PW wherein the inner edge 11 of the deep P-well ring PW is appropriately shaped.
  • the effective width w 5 of the central contact 12 is smaller than the effective width of the inner contacts 5 and 6 which is slightly larger than w 2 , but the width of the central contract 12 may also be the same as the effective width of the inner contacts 5 and 6 .
  • the P + stripes 10 shown in FIG. 8 may also be added to the vertical Hall device 1 shown in FIG. 9 .
  • the vertical Hall devices 1 are fabricated using a 0.35 ⁇ m “high voltage CMOS technology” which provides the following doping layers:

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DE102019004599B4 (de) * 2019-07-04 2021-01-14 Tdk-Micronas Gmbh Vertikale Hallsensorstruktur, Betrieb derselben und vertikaler Hallsensor
CN110736942B (zh) * 2019-10-12 2021-09-10 南京邮电大学 一种具有对称结构的高灵敏度垂直型磁场传感器
JP7506526B2 (ja) * 2020-05-22 2024-06-26 ローム株式会社 ホール素子、および電子部品
CN117279481B (zh) * 2023-11-23 2024-02-09 深圳市晶扬电子有限公司 一种高性能垂直型霍尔器件

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JP6726448B2 (ja) 2020-07-22
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