US8471546B2 - Time constant circuit, switch circuit, DC/DC converter, and display device - Google Patents

Time constant circuit, switch circuit, DC/DC converter, and display device Download PDF

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US8471546B2
US8471546B2 US12/891,434 US89143410A US8471546B2 US 8471546 B2 US8471546 B2 US 8471546B2 US 89143410 A US89143410 A US 89143410A US 8471546 B2 US8471546 B2 US 8471546B2
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terminal
fet
voltage
circuit
capacitance
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US20110074377A1 (en
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Kouichi Ooga
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Tianma Japan Ltd
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NLT Technologeies Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Definitions

  • the present invention relates to a time constant circuit that outputs voltages attenuating as the time passes, and a switch circuit and the like provided with the same.
  • Patent Document 1 discloses a time constant circuit that controls such rush current.
  • the time constant circuit is structured by disposing a single capacitor and a single resistor in parallel between a gate and a source of an FET (Field Effect Transistor), and disposing a resistor between a gate and a ground (GND) of the FET (see FIG. 8 ).
  • FET Field Effect Transistor
  • GND ground
  • the rush current is decreased.
  • a voltage-dividing resistor for determining the gate potential of the FET is disposed between the gate and GND of the FET.
  • Patent Document 2 discloses a voltage control circuit that controls the voltage between the gate and the source of the FET.
  • This voltage control circuit uses an operation amplifier, a resistor, and a capacitor for decreasing the rush current.
  • the voltage between the gate and the source of the FET is controlled by the voltage control circuit to decrease the rush current at the time of starting up the FET.
  • ICs such as a driver IC (Integrated Circuit) for driving the display device and a timing controller require a power source that outputs different voltage values.
  • a power source circuit DC (Direct Current)/DC converter) that generates a plurality of voltage values from the one kind of voltage value is used.
  • DC Direct Current
  • the starting order is controlled normally by using a component or a device having a switch function such as an FET.
  • a change in the voltage between the gate and the source of the FET after the voltage is applied to the FET may be controlled so that the FET starts up gradually.
  • a voltage control circuit may be provided between the gate and the source of the FET.
  • the FET is gradually started up in many cases by providing a time constant circuit that is formed with one resistor and one capacitor between the gate and the source of the FET as disclosed in Patent Document 1 (see FIG. 8).
  • the starting timing of the FET is moderated by the time constant circuit to reduce the rush current as much as possible without increasing the circuit scale, the rush current can be decreased.
  • the starting timing becomes delayed.
  • the time until an image displayed becomes longer in the display device.
  • the time constant circuit is characterized to include: a serial-parallel circuit that is formed by serially connecting a plurality of parallel circuits each structured with a resistance element and a capacitance element between a first terminal and a second terminal; and a voltage-dividing resistance element connected between a third terminal that is connected to the second terminal and a fourth terminal, wherein the first terminal and the second terminal are input terminals, and the third terminal and the fourth terminal are output terminals.
  • FIG. 1 is a block diagram showing a first exemplary embodiment
  • FIG. 2 is a block diagram showing a second exemplary embodiment
  • FIG. 3 is a circuit diagram showing a third exemplary embodiment
  • FIG. 4 is a first graph showing changes in the gate potentials of FETs of the third exemplary embodiment and a comparative example
  • FIG. 5 is a second graph showing changes in the gate potentials of FETs of the third exemplary embodiment and the comparative example
  • FIG. 6 is a block diagram showing a fourth exemplary embodiment
  • FIG. 7 is a circuit diagram showing a fifth exemplary embodiment
  • FIG. 8 is a circuit diagram showing a comparative example
  • FIG. 9 is a graph showing changes in the gate potential of an FET of the comparative example.
  • FIG. 11 is a graph showing a simulation result of the gate potential of the FET according to the third exemplary embodiment.
  • FIG. 12 is a graph showing a simulation result of the electric currents flowing in the resistance element and the capacitance element according to the third exemplary embodiment.
  • FIG. 1 is a block diagram showing a first exemplary embodiment of the present invention. Explanations will be provided hereinafter by referring to FIG. 1 .
  • a time constant circuit 10 includes: a series/parallel circuit 16 formed by serially connecting a plurality of parallel circuits 131 , - - - which are structured with resistance elements 111 , - - - and capacitance elements 121 , - - - between a first terminal 14 and a second terminal 15 ; and a voltage-dividing resistance element 19 connected between a third terminal 17 connected to the second terminal 15 and a fourth terminal 18 .
  • the parallel circuit 131 is formed with the resistance element 111 and the capacitance element 121
  • the parallel circuit 132 is formed with the resistance element 112 and the capacitance element 122 , - - -
  • the parallel circuit 13 n is formed with the resistance element 11 n and the capacitance element 12 n .
  • “n” is the number of the parallel circuits 131 - 13 n , and it is an integer of 2 or larger.
  • the output voltage V(t) changes depending of the sum of a plurality of exponential functions of different time constants.
  • the first terminal 14 and the second terminal 15 are input terminals
  • the third terminal 17 and the fourth terminal 18 are output terminals.
  • the direct current (DC) voltage V 0 is applied between the input terminals
  • the output voltage V(t) acquired between the output terminals changes depending of the sum of the plurality of exponential functions of different time constants.
  • the DC voltage V 0 is supplied by a direct current (DC) power source 32 and a main switch 33 .
  • B 1 to B n+1 are constants
  • c 1 to c n are attenuation constants (reciprocals of time constants).
  • the equation (2) indicates that the output voltage V(t) is affected by the sum of a plurality of exponential functions B 1 exp( ⁇ c 1 t), - - - .
  • Each of the exponential functions is the function that monotonously attenuates, and there are ones that attenuate quickly and ones that attenuate slowly.
  • the output voltage V(t) that is the sum of those functions is affected by the exponential functions that attenuate quickly immediately after the DC voltage V 0 is applied, and comes to be affected by the exponential functions that attenuate slowly as the time passes.
  • the resistance elements 111 to 11 n and the voltage-dividing resistance element 19 may be any elements that have resistance values.
  • a separate-component resistor, a resistor formed within a monolithic IC, a transistor operating as a resistor, and the like may be employed.
  • the capacitance elements 121 to 12 n may be any elements that have capacitance values.
  • a separate-component capacitor, a capacitor formed within a monolithic IC, a diode operating as a capacitor, a serial circuit formed with a capacitor and a resistor, and the like may be employed.
  • the resistance values of the resistance elements 111 to 11 n and the capacitance values of the capacitance elements 121 to 12 n may be any values, as long as the output voltage V(t) changes depending on the sum of the plurality of exponential functions of different time constants, i.e., as long as the solution of the equation (1) does not becomes an n-th root.
  • a switch circuit 20 includes the time constant circuit 10 , a control terminal 21 , and a semiconductor switch element 24 that has a first conductive terminal 22 and a second conductive terminal 23 .
  • the semiconductor switch element 24 is such a type in which between the first conductive terminal 22 and the second conductive terminal 23 becomes conductive when a specific voltage Vth is applied to the control terminal 21 . Further, the first terminal 14 is connected to the first conductive terminal 22 , and the third terminal 17 is connected to the control terminal 21 .
  • the output voltage V(t) attenuates gradually after attenuating steeply by the effect of the time constant circuit 10 .
  • the semiconductor switch element 24 has a characteristic of becoming conductive gradually as the voltage of the control terminal 21 changes gradually when the voltage of the control terminal 21 is in the vicinity of the specific voltage Vth.
  • each condition is so set that the output voltage V(t) reaches the specific voltage Vth after attenuating steeply.
  • the conditions are the resistance values of the resistance elements 111 to 11 n and the voltage-dividing resistance element 19 , the capacitance values of the capacitance elements 121 - 12 n , the specific voltage Vth, the DC voltage V 0 , and the like.
  • the semiconductor switch element 24 becomes conductive quickly and gradually.
  • the semiconductor switch element 24 is an FET, a bipolar transistor, a thyristor, or the like, for example.
  • a p-channel type FET, a pnp-type bipolar transistor, or the like is suitable.
  • the DC current V 0 is negative, an n-channel type FET, an npn-type bipolar transistor, or the like is suitable.
  • a DC/DC converter 30 includes the switch circuit 20 and a smoothing capacitance element 31 that is connected between the second conductive terminal 23 and the fourth terminal 18 .
  • An IC, a component, and the like for a constant voltage power source are connected to the output side of the smoothing capacitance element 31 as necessary.
  • terminal in this Specification includes a simple conductor, and it is not limited to a physical or mechanical terminal.
  • to connect means to make things in a same potential, and it is not limited to a physical or mechanical connection.
  • the time constant circuit is structured by using a serial-parallel circuit in which a plurality of parallel circuits for resistance elements and capacitance elements are connected in series; therefore, it is possible to acquire the characteristic of the output voltage of the time constant circuit, with which the voltage gradually attenuates after attenuating steeply.
  • FIG. 2 is a block diagram showing a second exemplary embodiment of the present invention. Explanations will be provided hereinafter by referring to FIG. 2 . Same reference numerals as those of FIG. 1 are applied to the same structural elements in FIG. 2 as those of FIG. 1 .
  • a time constant circuit 40 according to the second exemplary embodiment is so characterized that a serial-parallel circuit 46 is formed with a first parallel circuit 131 and a second parallel circuit 132 in the structure of the first exemplary embodiment.
  • a first exponential function and a second exponential function are derived approximately from the sum of the plurality of exponential functions of the equation (2) described in the first exemplary embodiment.
  • the output voltage V(t) changes according to the first exponential function immediately after the DC voltage V 0 is applied until a specific time t 1 , and changes according to the second exponential function after the specific time t 1 .
  • the equation (4) indicates that the output voltage V(t) is affected by the sum of the two exponential functions B 1 exp( ⁇ c 1 t) and B 2 exp( ⁇ c 2 t).
  • one of those exponential functions attenuates relatively quickly, and the other exponential function attenuates relatively slowly.
  • the output voltage V(t) is affected by the exponential function that attenuates quickly from the point immediately after the DC voltage V 0 is applied until the specific time t 1 , and comes to be affected by the exponential function that attenuates slowly after the specific time t 1 .
  • V 1 ( t ) D 1 exp( ⁇ E 1 t )+ D 2 (5)
  • V 2( t ) F 1 exp( ⁇ G 1 t )+ F 2 (6)
  • D 1 , D 2 , F 1 , F 2 are constants
  • E 1 , G 1 are attenuation constants (reciprocals of time constants)
  • E 1 >G 1 are attenuation constants (reciprocals of time constants)
  • the output voltage V(t) is expressed with the equation (5) as the first exponential function from the point immediately after the DC voltage V 0 is applied until the specific time t 1 , and expressed with the equation (6) as the second exponential function after the specific time t 1 .
  • the time constant circuit 40 it is possible to acquire the characteristic of the output voltage V(t) that attenuates gradually with the attenuation coefficient G 1 after attenuating steeply with the attenuation coefficient E 1 , compared to the characteristic of the output voltage that only attenuates monotonously. This corresponds to the fact that one of the two capacitance elements 121 and 122 contained in the serial-parallel circuit 46 is charged quickly, and the other capacitance element is charged slowly.
  • the resistance value of the resistance element 111 of the first parallel circuit 131 is R 1
  • the capacitance value of the capacitance element 121 of the first parallel circuit 131 is C 1
  • the resistance value of the resistance element 112 of the second parallel circuit 132 is R 2
  • the capacitance value of the capacitance element 122 of the second parallel circuit 132 is C 2 .
  • a switch circuit 50 includes the time constant circuit 40 and a semiconductor switch element 24 .
  • the output voltage V(t) reaches the specific voltage Vth after the specific time t 1 has passed from the point at which the DC voltage V 0 is applied.
  • the output voltage V(t) of the time constant circuit 40 steeply attenuates until the specific time t 1 , and gradually attenuates after the specific time t 1 .
  • the voltage of the control terminal 21 equivalent to the output voltage V(t) attenuates quickly until the specific time t 1 , thereafter reaches the specific voltage Vth with which the semiconductor switch element 24 becomes conductive, and attenuates gradually.
  • the semiconductor switch element 24 becomes conductive quickly and gradually.
  • the switch circuit 50 may be embodied in a concretive manner as follows.
  • the semiconductor switch element 24 is a p-channel type FET 24
  • the first and second conductive terminals 22 , 23 are a source terminal 22 and a drain terminal 23 , respectively
  • the control terminal 21 is a gate terminal 21
  • the specific voltage Vth is a threshold voltage Vth of the FET 24 . Note here that same reference numerals are applied to respective corresponding structural elements in the concretive form for making it easier to comprehend.
  • the output voltage V(t) of the time constant circuit 40 steeply attenuates until the specific time t 1 , and gradually attenuates after the specific time t 1 .
  • the voltage of the gate terminal 21 equivalent to the output voltage V(t) attenuates quickly until the specific time t 1 , thereafter reaches the specific voltage Vth with which the semiconductor switch element 24 becomes conductive, and attenuates gradually.
  • the FET 24 becomes conductive quickly and gradually.
  • the FET 24 may be of any types such as a MOS (Metal Oxide Silicon), a junction type, and the like.
  • a DC/DC converter 60 includes the switch circuit 50 and a smoothing capacitance element 31 .
  • the smoothing capacitance element 31 is connected between the drain terminal 23 and the fourth terminal 18 of the FET 24 .
  • FIG. 3 is a block diagram showing a third exemplary embodiment of the present invention. Explanations will be provided hereinafter by referring to FIG. 3 . Same reference numerals as those of FIG. 2 are applied to the same structural elements in FIG. 3 as those of FIG. 2 .
  • the third exemplary embodiment is a more concretive embodiment of the structure of the second exemplary embodiment. Note here that same reference numerals are applied to respective corresponding structural elements in the concretive form for making it easier to comprehend.
  • the first and second terminals 14 , 15 , the third and fourth terminals 17 , 18 , the DC power source 32 , and the main switch 33 shown in FIG. 2 are omitted for simplification.
  • a load 61 such as an IC power source is connected to the output side of the smoothing capacitance element 31 .
  • a time constant circuit 40 is provided between a gate terminal 21 and a source terminal 22 of an FET 24 that functions as a switch for keeping the starting order of the power source.
  • the time constant circuit 40 is formed with a resistance element 111 (resistance value R 1 ), a resistance element 112 (resistance value R 2 ), a capacitance element 121 (capacitance value C 1 ), and a capacitance element 122 (capacitance value C 2 ).
  • the smoothing capacitance element 31 is disposed on the output side of the FET 24 , and it can be considered as a capacitor for corresponding to a steep transitional response of the load 61 .
  • a voltage-dividing resistance element 19 (resistance value R 3 ) is a resistor for determining the potential of the gate terminal 21 .
  • the load 61 of the IC or the like for driving a display device is disposed ahead the drain terminal 23 of the FET 24 .
  • the FET 24 is used as a switch for controlling the starting order of the DC/DC converter 60 or used as a switch for controlling the starting order of the inputted voltage.
  • the “gate terminal 21 ”, the “source terminal 22 ”, and the drain terminal 23 ′′ are simply referred to as a “gate”, a “source”, and a “drain”.
  • the gate potential of the FET 24 becomes V 0 . Subsequently, the gate potential of the FET 24 changes as the time passes with a slope determined according to the time constant of the time constant circuit 40 between the gate and the source of the FET 24 . At last, the gate potential of the FET 24 after a sufficient length of time has passed becomes a potential expressed as follows. V 0 ⁇ ( R 3)/( R 1+ R 2+ R 3)
  • each of the capacitance elements 121 and 122 virtually becomes short-circuited.
  • the gate potential of the FET 24 becomes V 0
  • the potential between the gate and the source of the FET 24 becomes 0 V (no potential difference).
  • the capacitance value C 1 is set to be 10 times as large as the capacitance value C 2 .
  • the value of ⁇ 1 shows the time constant determined according to R 2 , R 3 , and C 2 .
  • the value of A is a coefficient that takes charging of the capacitance element 121 conducted until charging of the capacitance element 122 is completed into consideration. That is, while the capacitance element 122 is being charged, the capacitance element 121 is also being charged naturally. At that time, considering that electric charges at the contact between the capacitance element 121 and the capacitance element 122 is saved, the same electric charges are to be stored in the capacitance element 121 as that the capacitance element 122 when charging of the capacitance element 122 is completed, and the gate potential of the FET 24 drops for that. That is, the value of A is a value acquired by taking that into consideration.
  • the capacitance element 121 Immediately after charging of the capacitance element 122 is completed, the capacitance element 121 also has the electric charge amount equivalent to the electric charge amount the capacitance element 122 has stored (according to the value of A described above). From this point, charging to the capacitance element 121 is conducted further. However, charging of the capacitance element 122 is completed, so that it is considered that the capacitance element 122 is in an open state (i.e., equivalent to having no capacitance element 122 ). Therefore, the change in the gate potential of the FET 24 in time t after the charging of the capacitance element 122 is completed can be expressed approximately with Expression 2 as follows.
  • V 2( t ) V 0 ⁇ [ ⁇ R 3/( R 2+ R 3) ⁇ ( R 2+ R 3)/( R 1+ R 2+ R 3) ⁇ + ⁇ R 1/( R 1+ R 2 +R 3) ⁇ exp( ⁇ t/ ⁇ 2) ⁇ ]
  • ⁇ 2 [ ⁇ R 1 ⁇ ( R 2+ R 3) ⁇ /( R 1+ R 2+ R 3)] ⁇ C 1
  • the gate potential of the FET 24 changes according to V 1 ( t ) that is expressed with Expression 1 until charging of the capacitance element 122 is completed, and changes according to V 2 ( t ) that is expressed with Expression 2 after charging of the capacitance element 122 is completed.
  • FIG. 4 and FIG. 5 are graphs showing changes in the gate potentials of the FET 24 according to the third exemplary embodiment and a comparative example. Hereinafter, explanations will be provided by referring to FIG. 3-FIG . 5 .
  • FIG. 4 and FIG. 5 show the changes in the gate potentials of the FET 24 under four conditions, in which the lateral axis is the time (ms) and the longitudinal axis is the gate potential (V).
  • the four conditions are: a case of the comparative example to be described later in which the capacitance value C 100 is set as 0.01 ⁇ F; a case of the comparative example in which the capacitance value C 100 is set as 0.1 ⁇ F; a case of the third exemplary embodiment in which the capacitance element 122 is being charged; and a case of the third exemplary embodiment after the capacitance element 122 is opened.
  • the “third exemplary embodiment” and the “capacitance element 122 ” are simply referred to as the “present invention” and “C 2 ”, respectively.
  • Explanations of “charging” and “open” are inserted in FIG. 4 , and a slope (tangential line) of the gate potential of an ON-voltage of the FET is plotted in FIG. 5 .
  • the actual time variation in the gate potential is plotted with a thick solid line.
  • the gate potential of the FET 24 in the third exemplary embodiment changes steeply up to the point where the charging of the capacitance element 122 is completed, and changes gradually after charging of the capacitance element 122 is completed.
  • the capacitance value C 2 is set smaller than the capacitance value C 1 and appropriate values are employed for the resistance values R 1 , R 2 , R 3 so as to make the change in the gate potential of the FET 24 steep immediately after applying the DC voltage V 0 and to make the change gradual after completing charging of the capacitance element 122 .
  • the slope in the gate potential before and after the FET 24 becomes ON can be controlled.
  • Each constant regarding the time constant circuit 40 can be calculated from V 1 ( t ) and V 2 ( t ) expressed with Expression 1 and Expression 2. That is, the resistance value and the capacitance value are selected in such a manner that V 1 ( t ) and V 2 ( t ) reach an actual operating voltage X of the FET 24 at the timing at which charging of the capacitance element 122 is completed.
  • the “actual operating voltage X” corresponds to “specific voltage (threshold voltage) Vth” in the first and second exemplary embodiments.
  • the values are defined as follows when the DC voltage V 0 is 12 V and the actual operating voltage X is 2.5 V.
  • the relations expressed in the left sides of Expressions a-d take optimum values (right sides) that vary according to the values of the DC voltage V 0 and the actual operating voltage X. However, those are based on the ratios expressed in the right sides of Expressions a-d, so that the relational expressions of a-d are important when selecting each of the values of the resistance elements 111 , 112 , the voltage-dividing resistance elements 19 , and the capacitance elements 121 , 122 . That is, through applying Expression a-d, proper values can be derived even when the DC voltage V 0 , the actual operating voltage X, and other conditions are changed. Further, details of the generalized relational expressions of a-d will be described. First, regarding Expression a, the resistance value R 2 of the resistance element 112 is greatly affected by the resistance value R 3 of the voltage-dividing resistance element 19 .
  • V 2(0) V 0 ⁇ ( R 3/( R 2+ R 3))
  • V 1( t ) V 0 ⁇ ( R 3/( R 2+ R 3))
  • V 0 Voltage applied between source and GND of FET 24
  • R 1 is the resistance value for determining the gate potential of the FET 24 after a sufficient length of time has passed from the point at which the voltage is applied between the source and GND of the FET 24 . Note here that it is necessary for the potential difference between the gate and the source of the FET 24 to be in a value that is equal to or larger than the actual operating voltage X of the FET 24 after the sufficient length of time has passed. It is because the FET 24 does not start up (the FET 24 cannot be turned ON), when the potential difference between the gate and the source of the FET 24 has not reached the actual operating voltage X.
  • R 1 needs to be selected to satisfy a following conditional expression.
  • V 0 Voltage applied between source and GND of FET 24
  • V 0 12 V
  • R 1 1200 k ⁇
  • R 2 300 k ⁇
  • R 3 1500 k ⁇
  • C 1 becomes an important parameter for decreasing the rush current in the third exemplary embodiment, because it is presupposed in the third exemplary embodiment that charging of the capacitance element 122 (capacitance value C 2 ) is completed earlier. That is, it is because C 1 needs to be set larger than C 2 , and the gate potential of the FET 24 changes with the time constant determined according to C 1 , R 2 , and R 3 after charging of the capacitance element 122 is completed.
  • a “comparative example” is investigated for obtaining the optimum resistance value C 1 .
  • a time constant circuit of the comparative example is formed with a parallel circuit of a single resistance element and a single capacitance element, and this corresponds to the technique disclosed in Patent Document 1.
  • a switch circuit and a DC/DC converter in which the time constant circuit in the structure of the third exemplary embodiment is replaced with that of the comparative example are taken as “a switch circuit and a DC/DC converter of the comparative example”.
  • FIG. 8 is a circuit diagram showing the comparative example.
  • Same reference numerals as those of FIG. 3 are applied to same structural elements of FIG. 8 as those of FIG. 3 .
  • a time constant circuit 100 of the comparative example includes a parallel circuit 103 that is configured with a resistance element 101 (resistance value R 100 ) and a capacitance element 102 (capacitance value C 100 ), and a voltage-dividing resistance element 104 (resistance value R 101 ).
  • a switch circuit 110 includes the time constant circuit 100 and an FET 24 .
  • a DC/DC converter 120 includes the switch circuit 110 and a smoothing capacitance element 31 .
  • a difference is that the time constant circuit 100 of the comparative example only has a single RC parallel circuit, while the time constant circuit 40 ( FIG. 3 ) of the third exemplary embodiment has two RC parallel circuits.
  • the slope in the gate potential (time variation rate) in the actual operating voltage of the FET 24 according to the comparative example can be obtained from Expression g.
  • t 1 ⁇ (( R 3 ⁇ C 1)/2) ⁇ ln(( R 3/( R 1+ R 2)) ⁇ (( R 2+ R 3)/ R 2) ⁇ ( X/V 0))
  • the slope of the gate potential in the actual operating voltage of the FET 24 is obtained in the same manner.
  • charging of the capacitance element 122 already has to be completed in the vicinity of the actual operating voltage of the FET 24 .
  • the time variation in the gate potential of the FET 24 at this time is expressed by using Expression 2, and the slope of the gate potential in the actual operating voltage of the FET 24 can be obtained as follows by performing differentiation of Expression 2 with respect to time.
  • the slope according to the third exemplary embodiment obtained from Expression i needs to be smaller than the slope according to the comparative example obtained from Expression g. Further, in time t 1 , the gate potential of the FET 24 according to the third exemplary embodiment needs to have reached the actual operating voltage.
  • C 2 becomes an important parameter for shortening the starting point of the FET 24 as much as possible with the third exemplary embodiment. Also, as is the feature of the third exemplary embodiment, it is necessary to complete charging of the capacitance element 122 earlier regarding the capacitance element 121 (capacitance value C 1 ) and the capacitance element 122 (capacitance value C 2 ), so that it is necessary to satisfy C 1 >C 2 . Further, in order to achieve the effects of the third exemplary embodiment fully, it is desirable to select C 2 to satisfy a relation of “C 1 >5 ⁇ C 2 ”. The smaller the value of C 2 with respect to the value of C 1 in Expression 1, the more the delay amount of the starting point of the FET 24 can be shortened. As described above, when selecting the resistance values R 1 , R 2 , R 3 and the capacitance values C 1 , C 2 of the time constant circuit 40 shown in FIG. 3 , values that satisfy Expression e-Expression k are to be selected.
  • FIG. 3 shows peripheral circuits of the FET 24 within the DC/DC converter 60 .
  • One terminal of the resistance element 111 and one terminal of the capacitance element 121 are connected to the source of the FET 24 , and the opposite terminals of the resistance element 111 and the capacitance element 121 are connected to each other.
  • one terminal of the resistance element 112 and one terminal of the capacitance element 122 are connected at the junction thereof, and the other terminals of the resistance element 112 and the capacitance element 122 are connected to the gate of the FET 24 , respectively.
  • the resistance element 19 is connected between the gate and GND of the FET 24
  • the smoothing capacitance element 31 is connected between the drain and the GND of the FET 24 .
  • the DC voltage V 0 is supplied from the source side of the FET 24 , and the load 61 such as the IC is connected ahead the smoothing capacitance element 31 .
  • the change in the gate potential of the FET 24 is described in the third exemplary embodiment, it is not limited only to the FET 24 . Any components (elements) having the switch function whose flown current value changes in accordance with the change in the applied voltage can be controlled in the same manner as that of the switch circuit 50 of the third exemplary embodiment.
  • the capacitance elements 121 and 122 configuring the time constant circuit 40 are not limited to be capacitors. Any components having capacitance components can be used for substitutions.
  • the third exemplary embodiment is described by using the capacitors for enabling it with the technique of the lowest const.
  • the change in the gate potential of the FET 24 after charging to the capacitance element 122 is completed and the capacitance element 122 becomes an open state will be described.
  • the gate potential of the FET 24 comes to change according to the time constant configured with R 1 , R 2 , and R 3 as shown with Expression 2 described above.
  • the gate potential of the FET 24 changes steeply until the capacitance element 122 becomes open since the time constant originated in the capacitance 122 becomes dominant, and changes gradually after the capacitance element 122 becomes open since the time constant originated in the capacitance element 121 becomes dominant.
  • the time required for the gate potential of the FET 24 to reach the actual operating voltage is about 10 ms.
  • This changing rate of the gate potential influences the rush current when the FET 24 starts up. As the absolute value thereof becomes smaller, the decrease amount of the rush current becomes greater.
  • FIG. 9 is a graph showing the change in the gate potential of the FET of the comparative example.
  • FIG. 10 is a graph showing an example of delay in the starting point of the output voltage of the DC/DC converter of the comparative example.
  • the peripheral circuit of the FET 24 according to the comparative example is configured with a resistance element 101 , a voltage-dividing resistance element 104 , a capacitance element 102 , and a smoothing capacitance element 31 .
  • the difference with respect to the circuit structure of the third exemplary embodiment is that a time constant circuit 100 disposed between the gate and the source of the FET 24 is configured with the resistance element 101 and the capacitance element 102 . That is, the time constant circuit 100 of the comparative example is structured with a single resistance element and a single capacitance element, while the time constant circuit of the third exemplary embodiment is structured with two resistance elements and two capacitance elements.
  • the time variation in the gate potential of the comparative example is expressed with Expression 3 described above.
  • V 0 12 V
  • R 100 1.5 M ⁇
  • R 101 1.5 M ⁇
  • C 100 0.01 ⁇ F
  • the FET 24 is a p-channel type MOSFET
  • the actual operating voltage is 2.5 V.
  • the time required to reach the actual operating voltage (2.5 V) of the FET 24 is about 40 ms ( FIG. 4 and FIG. 5 ).
  • the changes in the gate potential at the time where the FET 24 starts up are approximately shown by using Expression 1, Expression 2, and Expression 3 in the third exemplary embodiment and the comparative example, the changes in the gate potential can be calculated easily by using a circuit simulator such as Spice (Simulation Program with Integrated Circuit Emphasis), for example.
  • Spice Simulation Program with Integrated Circuit Emphasis
  • the actual operating voltage of the FET is explained as being 2.5 V in the third exemplary embodiment.
  • the value of the actual operating voltage may vary depending on the FET in some cases.
  • the optimum resistance value and the capacitance value of the time constant circuit 40 can be selected by checking the actual operating voltage of the FET 24 and the changing rate of the gate potential through conducting a simulation on the time constant of the time constant circuit 40 that is loaded between the gate and the source of the FET by using a circuit simulator.
  • the important thing is to select the resistance values R 1 , R 2 , R 3 and the capacitance values C 1 , C 2 so that the charging completion point of the capacitance element 122 comes in the vicinity of the actual operating voltage of the FET 24 .
  • FIG. 11 is a graph showing the simulation result conducted regarding the gate potential of the FET 24 of the third exemplary embodiment, and it corresponds to the gate potential (thick solid line) of the FET 24 extracted from FIG. 4 .
  • FIG. 12 is a graph showing the simulation result regarding the electric current flown in the resistance elements 111 , 112 and the capacitance element 121 , 122 of the third exemplary embodiment. In FIG.
  • the lateral axis (ms) is the time
  • the longitudinal axis is the electric current ( ⁇ A)
  • the electric currents flown in the resistance elements 111 , 112 are ⁇ : I(R 1 ), ⁇ : I(R 2 )
  • the electric currents flown in the capacitance elements 121 , 122 are ⁇ : I(C 1 ), ⁇ : I(C 2 ).
  • the rush current amount at the time of starting up the FET is made to be the same level in the comparative example and the third exemplary embodiment, i.e., when the time variation in the gate potential at the time of starting up the FET is made to be the same level in the comparative example and the third exemplary embodiment, followings can be said.
  • the time required until the FET starts up is delayed in proportional to the time constant of the time constant circuit with the comparative example, while the amount of delay until the FET starts up can be shortened as much as possible with the third exemplary embodiment compared to the comparative example.
  • the time until the display device starts up can be shortened as much as possible while decreasing the rush current generated at the time of starting up the display device.
  • the time constant circuit 100 used between the gate and the source of the FET 24 is formed with a single resistance element 101 and a single capacitance element 102 , and the gate potential of the FET is raised gradually to decrease the rush current generated at the time of starting up the FET 24 (at the time of starting up the DC/DC converter 120 ).
  • the time constant is to be increased in the time constant circuit 100 of the comparative example, the time until the starting point of the FET 24 (starting point of the DC/DC converter 120 ) becomes delayed.
  • the time constant circuit 40 used between the gate and the source of the FET 24 is formed with the two resistance elements 111 , 112 and the two capacitance elements 121 , 122 .
  • the delay time until the starting point of the FET 24 (starting point of the DC/DC converter 60 ) can be shortened compared to the case of the comparative example while decreasing the rush current at the time of starting up the FET 24 .
  • the time constant is set to be 10 times as large with the simple time constant circuit 100 as that of the comparative example when decreasing the rush current at the time of starting up the FET 24 , the starting point of the FET is also delayed by 10 times. In the meantime, the delay amount of the starting point of the FET 24 can be suppressed to about 2.5 times by employing the time constant circuit 40 of the third exemplary embodiment.
  • FIG. 4 shows the changes in the gate potentials of the FET 24 according the comparative example and the third exemplary embodiment.
  • the gate potential of the FET 24 corresponding to the actual operating voltage 2.5 V of the FET 24 (the potential difference between the gate and the source of the FET 24 is 2.5 V) is 9.5 V.
  • the time that reaches the line of 9.5 V is 10 ms with the third exemplary embodiment (thick solid line in FIG. 4 ), while it is 40 ms with the comparative example ( ⁇ in FIG. 4 ).
  • the time until the display device is started up can be shortened as much as possible while decreasing the rush current generated at the time of starting up the display device.
  • the circuit structure of the third exemplary embodiment can be achieved simply at a low cost through using a time constant circuit formed only with a passive element.
  • the circuit structure of the third exemplary embodiment makes it possible to shorten the delay amount of the starting time, while decreasing the rush current at the time of starting up the FET (at the time of starting up the DC/DC converter).
  • FIG. 6 is a block diagram showing a fourth exemplary embodiment of the present invention. Hereinafter, explanations will be provided by referring to FIG. 6 .
  • a display device 62 of the fourth exemplary embodiment is characterized to include: a video display unit 63 having pixels at each of intersection points of matrix of signal lines and scan lines; a scan-line driver 64 and a signal-line driver 65 which apply voltages according to a video signal to each pixel of the video display unit 63 ; a video signal processing circuit 67 which processes the video signal acquired from a video signal source 66 , and outputs it to the scan-line driver 64 and the signal-line driver 65 ; and a supply voltage generating circuit 69 which converts the voltage acquired from a supply voltage supplying source 68 into a prescribed value, and supplies it to the scan-line driver 64 , the signal-line driver 65 , and the video signal processing circuit 67 .
  • the display device 62 is characterized to include the DC/DC converted 60 of the third exemplary embodiment inside the supply voltage generating circuit 69 .
  • the video display unit 63 is a liquid crystal panel
  • the display device 62 is a liquid crystal display device.
  • the video signal processing circuit 67 and the supply voltage generating circuit 69 are required.
  • the video signal processing circuit 67 processes the video signal supplied from the video signal supplying source 66 (rearranging the video signals, generating a reference signal, and the like).
  • the supply voltage generating circuit 69 supplies proper supply voltages to various ICs (the scan-line driver 64 , the signal-line driver 65 , the video signal processing circuit 67 , and the like) for driving the video display unit 63 .
  • the supply voltage generating circuit 69 generates a plurality of supply voltages from one kind of supplied supply voltage.
  • There are a plurality of ICs such as the scan-line driver 64 , the signal-line driver 65 , and the video signal processing circuit 67 for driving the video display unit 63 , and the supply voltages required by each of the ICs are different in many cases. In such case, it is necessary to have a circuit (DC/DC converter 60 or the like) which generates a plurality of supply voltages from a single supplied supply voltage.
  • a switch FET for controlling the starting order and the starting timing of each power source is used for the DC/DC converter 60 .
  • the supply voltage generating circuit 69 that includes the DC/DC converter 60 is used. Therefore, there is no malfunctioning generated due to the rush current at the time of supplying the power, and the time required from the point at which the power is supplied to the point at which a video is displayed becomes short.
  • the display device 62 is not limited only to a liquid crystal display device.
  • any types of display devices such as an organic EL display device and an LED display device may be used.
  • FIG. 7 is a circuit diagram showing a fifth exemplary embodiment of the present invention. Explanations will be provided hereinafter by referring to FIG. 7 . Same reference numerals as those of FIG. 3 are applied to the same structural elements in FIG. 7 as those of FIG. 3 .
  • a serial-parallel circuit 76 is formed with a first parallel circuit 131 , a second parallel circuit 132 , and a third parallel circuit 133 .
  • the first parallel circuit 131 is formed with a resistance element 111 (resistance value R 10 ) and a capacitance element 121 (capacitance value C 10 )
  • the second parallel circuit 132 is formed with a resistance element 112 (resistance value R 11 ) and a capacitance element 122 (capacitance value C 11 )
  • the third parallel circuit 133 is formed with a resistance element 113 (resistance value R 12 ) and a capacitance element 123 (capacitance value C 12 ).
  • a time constant circuit 70 is formed with the serial-parallel circuit 76 and a voltage-dividing resistance element 19 (resistance value R 13 ).
  • a switch circuit 80 includes the time constant circuit 70 and an FET 24 .
  • a DC/DC converter 90 includes the switch circuit 80 and a smoothing capacitance element 31 .
  • the time constant circuit 70 of the fifth exemplary embodiment uses three resistance elements and three capacitance elements, while the time constant circuit of the third exemplary embodiment uses two resistance elements and two capacitance elements.
  • Other structures of the fifth exemplary embodiment are the same as those of the third exemplary embodiment. It is possible with the fifth exemplary embodiment to make the change in the gate potential until reaching the actual operating voltage of the FET 24 steeper. That is, it is possible to shorten the delay amount of the starting point of the FET 24 than the case of the third exemplary embodiment.
  • the time constant circuit 70 that uses three capacitance elements 121 - 123 is provided between the gate and the source of the FET 24 .
  • the part where the gate potential of the FET 24 changes steeply depending on the passage of time described in the third exemplary embodiment (change in the gate potential until reaching the actual operating voltage of the FET 24 ) can be changed more steeply.
  • the delay amount until the FET 24 starts up can be shortened further.
  • Effects of the fifth exemplary embodiment are that the rush current at the time of starting up the display device can be decreased, and that the time until starting up the display device can be shortened as much as possible as in the case of the third exemplary embodiment.
  • the difference with respect to the third exemplary embodiment regarding the effects of the fifth exemplary embodiment is that the time until starting up the display device can be shortened further compared to the case of the third exemplary embodiment by using three capacitance elements for the time constant circuit.
  • the fifth exemplary embodiment makes it possible to provide a simple and low-cost circuit structure by using the time constant circuit formed only with a passive element and to shorten the delay amount in the starting time than the case of the third exemplary embodiment while decreasing the rush current at the time of starting up the FET (at the time of starting up the DC/DC converter).
  • An exemplary object of the present invention is to provide, as a technique for overcoming the above-described issues, a display device and the like having a circuit with which the rush current generated at the time of starting up the DC/DC converter is decreased, the delay time of the starting time of the DC/DC converter is shortened as much as possible, and the scale thereof is minimized.
  • the circuit structure in which the FET is turned ON by using the time constant circuit structured with the resistance element and the capacitance element is employed for controlling the gate potential of the FET.
  • the time constant circuit that simply uses one each of the resistance element and capacitance element, the delay amount of the starting point is determined almost in proportional to the time constant.
  • the present invention employs a following circuit structure.
  • the time constant circuit between the gate and the source of the FET is structured by combining two capacitance elements and two resistance elements.
  • One capacitance element and one resistance element are connected in parallel, two pairs thereof are connected in series, and the both ends thereof are connected to the gate and the source of the FET, respectively.
  • the change in the gate potential of the FET can be expressed with V 1 ( t ) and V 2 ( t ) which are depicted in the third exemplary embodiment and the like.
  • the control of the gate potential of the FET there may be a case that employs a circuit structure in which the resistance element and the capacitance element are disposed between the gate and the source of the FET, and the FET is turned ON by using the time constant thereof.
  • the time constant circuit formed by using one resistance element and one capacitance element between the gate and the source of the FET the delay amount of the starting point is determined almost in proportional to the time constant. It is necessary to have a large value of the time constant in order to decrease the rush current at the time of starting up the FET.
  • the present invention employs the structure in which the time constant circuit provided between the gate and the source of the FET is formed by adding one more capacitance element and one more resistance element and combining those.
  • the feature of the time constant circuit is that the change amount of the gate potential of the FET becomes steep immediately after the voltage is applied to the FET (start to generate potential difference between the gate and the source of the FET) while the change amount of the gate potential of the FET becomes gradual in the vicinity of the voltage (actual operating voltage) at which the FET turns ON.
  • time constant circuit of the present invention to control the change amount of the gate potential of the FET to be steep immediately after the potential difference between the gate and the source of the FET is generated and to control the change amount of the gate potential of the FET to be gradual in the vicinity of the voltage (actual operating voltage) at which the FET turns ON.
  • the voltage changes with the time constant determined by one resistance element and one capacitance element until it reaches the voltage (actual operating voltage) at which the FET is actually turned on.
  • the time for reaching the actual operating voltage of the FET becomes extended for the increased value of the time constant.
  • the time for reaching the actual operating voltage of the FET can be shortened as much as possible through employing the structure of the time constant circuit of the present invention. That is, it is possible to provide a display device capable of decreasing the rush current amount and shortening the delay amount of the DC/DC converter as much as possible, which can be formed in the minimum circuit scale. This makes it possible to decrease the rush current generated at the time of starting up the display device, while suppressing the delay time for displaying a video on the display device as much as possible.
  • the present invention can also be expressed as follows.
  • the present invention can be utilized for a time constant circuit which outputs a voltage that attenuates as the time passes, and for a switch circuit, a DC/DC converter, a display device, and the like, which are provided with the same.

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JP2014068105A (ja) * 2012-09-25 2014-04-17 Nec Embedded Products Ltd 電源用スイッチング回路
US9727073B1 (en) * 2012-10-17 2017-08-08 Marvell International Ltd. Precision current source with programmable slew rate control
JP2014090316A (ja) * 2012-10-30 2014-05-15 Juki Corp ゲート駆動回路
JP2015061456A (ja) * 2013-09-20 2015-03-30 日本無線株式会社 電源回路
US10651739B1 (en) * 2019-02-25 2020-05-12 Nextracker Inc. Power converters and methods of controlling same

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JP2003111460A (ja) 2001-09-28 2003-04-11 Japan Servo Co Ltd 突入電流防止回路を備えるフアンモータ
JP2005223804A (ja) 2004-02-09 2005-08-18 Harison Toshiba Lighting Corp スイッチ回路

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JP2011071863A (ja) 2011-04-07

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