US8455369B2 - Trench embedding method - Google Patents

Trench embedding method Download PDF

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US8455369B2
US8455369B2 US13/334,352 US201113334352A US8455369B2 US 8455369 B2 US8455369 B2 US 8455369B2 US 201113334352 A US201113334352 A US 201113334352A US 8455369 B2 US8455369 B2 US 8455369B2
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film
trench
silicon
si
oxidization
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Masahisa Watanabe
Mitsuhiro Okada
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals

Abstract

A trench embedding method includes forming an oxidization barrier film on a trench; forming an expandable film on the oxidization barrier film; embedding an embedding material that contracts by being fired on the trench; and firing the embedding material, wherein the forming of the oxidization barrier film includes: forming a first seed layer on the trench by supplying an aminosilane-based gas; and forming a silicon nitride film on the first seed layer, wherein the forming of the expandable film includes: forming a second seed layer on the silicon nitride film by supplying an aminosilane-based gas; and forming a silicon film on the second seed layer.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application claims the benefit of Japanese Patent Application No. 2010-290647, filed on Dec. 27, 2010 in the Japan Patent Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a trench embedding method and a film-forming apparatus.

2. Description of the Related Art

Semiconductor integrated circuit devices have a minute trench structure therein. A typical example of the minute trench structure is a STI (shallow trench isolation). An STI is a device isolation area for dividing active areas of a semiconductor device, and is formed by forming a minute trench on a silicon substrate and embedding an insulating material into the minute trench.

For example, an SOD (spin-on dielectric), as disclosed in Patent Reference 1, is known as an embedded insulating material. In particular, an inorganic polymer mainly including PHPS (perhydropolysilazane: SiH2NH) has attracted attention. When PHPS is fired in a vapor atmosphere, PHPS is changed into silicon oxide (SiO2). A reaction formula thereof is as follows.
SiH2NH+2H2O→SiO2+NH3+2H2

However, PHPS contracts when changed into silicon oxide. Thus, a gap is generated on a minute trench on which PHPS is changed into silicon oxide.

Accordingly, in Patent Reference 1, an expandable film is formed on a minute trench and then PHPS is embedded into the minute trench in prediction of contraction of PHPS. Such an expandable film may be a silicon (Si) film. In Patent Reference 1, a silicon film is expanded by being changed into a silicon oxide film, and thus contraction of PHPS is offset, thereby preventing a gap from being generated on a minute trench.

3. Prior Art Reference

  • (Patent Reference 1) U.S. Pat. No. 7,112,513
SUMMARY OF THE INVENTION

In Patent Reference 1, a process of changing a silicon film into a silicon oxide film, that is, an oxidization process, is disclosed. For this, before a silicon film is formed, a film serving as an oxidation barrier through which oxygen may hardly pass is formed on a minute trench so that a silicon substrate may not be oxidized due to oxidization reaching the silicon substrate. In Patent Reference 1, a film serving as an oxidization barrier is a silicon nitride film (Si3N4).

However, if a trench is further miniaturized, it may be difficult or impossible to form a film serving as an oxidization barrier on the trench, in addition to an expandable film.

The present invention is made in view of the above-described problems, and provides a trench embedding method that allows an expandable film and a film serving as an oxidization barrier to be formed on a trench even if the trench is further miniaturized, and a film-forming apparatus capable of performing the trench embedding method.

According to an aspect of the present invention, a trench embedding method includes: forming an oxidization barrier film on a trench formed on a semiconductor substrate; forming an expandable film on the oxidization barrier film; embedding an embedding material that contracts by being fired on the trench where the oxidization barrier film and the expandable film are formed; and firing the embedding material, wherein the forming of the oxidization barrier film includes: forming a first seed layer on the trench by supplying an aminosilane-based gas to the semiconductor substrate on which the trench is formed; and forming a silicon nitride film on the first seed layer, wherein the forming of the expandable film includes: forming a second seed layer on the silicon nitride film by supplying an aminosilane-based gas to the semiconductor substrate on which the silicon nitride film is formed; and forming a silicon film on the second seed layer.

According to another aspect of the present invention, a trench embedding method includes: forming an oxidization film on a trench by oxidizing the semiconductor substrate on which the trench is formed; nitriding the oxidization film; forming an expandable film on a nitrided oxidization film; embedding an embedding material that contracts by being fired on the trench where the oxidization film and the expandable film are formed; and firing the embedding material, wherein the forming of the expandable film includes: forming a seed layer on the nitrided oxidization film by supplying an aminosilane-based gas to the semiconductor substrate on which the nitrided oxidization film is formed; and forming a silicon film on the seed layer.

According to another aspect of the present invention, a film-forming apparatus includes: a process chamber which accommodates a semiconductor substrate on which a trench is formed; a gas supply mechanism which supplies an aminosilane-based gas, a silane-based gas, and a gas including a nitriding agent into the process chamber; a heating device which heats an inside of the process chamber; an exhauster which evacuates the inside of the process chamber; and a controller which controls the gas supply mechanism, the heating device, and the exhauster, wherein the controller controls the gas supply mechanism, the heating device, and the exhauster to perform the trench embedding method according to aspects of the present invention on the semiconductor substrate in the process chamber.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a flowchart showing a sequence of a trench embedding method according to an embodiment of the present invention;

FIGS. 2A through 2I are cross-sectional views schematically showing states of a semiconductor substrate during the sequence shown in FIG. 1;

FIG. 3 is a view showing a relationship between a deposition time and a film thickness of a silicon film;

FIG. 4 is an enlarged view of the portion A of FIG. 3 indicated by the broken line;

FIG. 5 is a view showing a relationship between an ALD cycle and a film thickness of a silicon nitride film; and

FIG. 6 is a cross-sectional view schematically showing an example of a film-forming apparatus capable of performing a trench embedding method according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(Embodiments for Carrying Out the Invention)

An embodiment of the present invention achieved on the basis of the findings given above will now be described with reference to the accompanying drawings. In the following description, the constituent elements having substantially the same function and arrangement are denoted by the same reference numerals, and a repetitive description will be made only when necessary.

(Embedding Method)

FIG. 1 is a flowchart showing a sequence of a trench embedding method according to an embodiment of the present invention. FIGS. 2A through 2I are cross-sectional views schematically showing states of a semiconductor substrate during the sequence shown in FIG. 1.

First, as shown in process 1 of FIG. 1, a trench is formed on the semiconductor substrate.

An example of forming the trench on the semiconductor substrate is as follows.

As shown in FIG. 2A, a surface of the semiconductor substrate, that is, a silicon substrate 1 in the present embodiment, is thermally oxidized to form a pad oxidization film 2. Then, silicon nitride is deposited on the pad oxidization film 2 to form a silicon nitride film 3. Then, a photoresist is coated on the silicon nitride film 3 to form a photoresist film 4. Then, a window 5 corresponding to a trench forming pattern is formed on the photoresist film 4 by using a photolithography method.

Next, as shown in FIG. 2B, anisotropic etching, for example, reactive ion etching, is performed on the silicon nitride film 3, the pad oxidization film 2, and the silicon substrate 1 by using the photoresist film 4 as a mask, thereby forming a trench 6 on the silicon substrate 1.

Next, as shown in process 2 of FIG. 1, an oxidization film is formed on a surface of the semiconductor substrate.

This process is, as shown in FIG. 2C, a process of forming a film that may be hardly oxidized compared to the silicon substrate 1 on a surface of the silicon substrate 1 exposed by at least a side wall of the trench 6. In the present embodiment, an oxidization film 7 is formed on at least the side wall of the trench 6. On the side wall of the trench 6, the oxidization film 7 is silicon oxide. Silicon oxide is hardly oxidized compared to silicon.

Also, in the present embodiment, the oxidization film 7 is formed by radical oxidization. According to radical oxidization, as shown in FIG. 2C, the pad oxidization film 2, the silicon nitride film 3, or the like may also be oxidized as well as the surface of the silicon substrate 1 exposed by the side wall of the trench 6. That is, an entire surface of the silicon substrate 1 on which the trench 6 is formed may be oxidized, and thus the oxidization film 7 is formed on the entire surface of the silicon substrate 1 on which the trench 6 is formed. If the oxidization film 7 is formed on the entire surface of the silicon substrate 1 on which the trench 6 is formed, a seed layer to be formed next may be formed on the oxidization film 7. If the seed layer is formed on both a nitride film and the oxidization film at the same time, there is a possibility that a growing speed of a silicon film to be formed after the seed layer may vary on the nitride film and on the oxidization film. In this regard, as described in the present embodiment, if the seed layer is formed on the oxidization film 7, a difference in growing speeds of the silicon film may be reduced, thereby contributing to improvement of step coverage. Also, even if plasma oxidization is used instead of radical oxidization, the same effect as the radical oxidization may be obtained.

Next, as shown in process 3 of FIG. 1, an oxidization barrier film is formed on the oxidization film 7.

In the present embodiment, the oxidization barrier film is formed in two processes. First, as shown in process 31 of FIG. 1 and in FIG. 2D, a seed layer 8 is formed on the oxidization film 7. In detail, the silicon substrate 1 on which the oxidization film 7 is formed is heated, and an aminosilane-based gas is supplied to a surface of the silicon substrate 1 which is heated to form the seed layer 8 on the surface of the silicon substrate 1, that is, a surface of the oxidization film 7 in the present embodiment.

Examples of the aminosilane-based gas may include BAS (butylaminosilane), BTBAS (bis(tertiarybutylamino)silane), DMAS (dimethylaminosilane), BDMAS (bis(dimethylamino)silane), TDMAS (tri(dimethylamino)silane), DEAS (diethylaminosilane), BDEAS (bis(diethylamino)silane), DPAS (dipropylaminosilane), DIPAS (diisopropylaminosilane), or the like. In the present embodiment, DIPAS is used.

Process conditions in process 31 are as follows:

DIPAS flow rate: 150 sccm,

process time: 0.5 min,

process temperature: 450° C., and

process pressure: 532 Pa (4 Torr). The process 31 is a process hereinafter referred to as a pre-flow.

Process 31 is a process for enabling silicon nitride to be easily adsorbed to the oxidization film 7. Also, although the seed layer 8 is formed in process 31, a film is rarely actually formed. It is preferable that a thickness of the seed layer 8 be about a thickness of a monoatomic layer level. Specifically, the thickness of the seed layer 8 is equal to or greater than 0.1 nm and equal to or less than 0.3 nm.

Next, as shown in process 32 of FIG. 1 and in FIG. 2E, a silicon nitride film 9 is formed on the seed layer 8. In detail, the silicon substrate 1 on which the seed layer 8 is formed is heated, and a gas including silicon and a gas including a nitriding agent are supplied to a surface of the silicon substrate 1 which is heated to form the silicon nitride film 9 on the seed layer 8. In the present embodiment, a silane-based gas, for example, dichlorosilane (DCS: SiH2Cl2), is used as the gas including silicon, and a gas including ammonia is used as the gas including a nitriding agent. Also, in the present embodiment, in order to form the silicon nitride film 9, technique called an ALD (atomic layer deposition) method or an MLD (molecular layer deposition) method that forms a film by alternately supplying a gas including silicon and a gas including a nitriding agent for nitriding silicon is used.

Process conditions in process 32 are as follows:

dichlorosilane flow rate: 1000 sccm,

ammonia flow rate: 5000 sccm,

process temperature: 630° C., and

process pressure: 51 Pa (0.386 Torr).

Under the above-described conditions, when the number of ALD cycles is about 30 cycles, the silicon nitride film 9 having a thin thickness of about 2 nm is formed.

Next, as shown in process 4 of FIG. 1, an expandable film is formed on an oxidization barrier film.

In the present embodiment, the expandable film is formed in two processes.

First, as shown in process 41 of FIG. 1 and in FIG. 2F, a seed layer 10 is formed on the silicon nitride film 9. In detail, the silicon substrate 1 on which the silicon nitride film 9 is formed is heated, and then an aminosilane-based gas is supplied to a surface of the silicon substrate 1 which is heated to form the seed layer 10 on the surface of the silicon substrate 1, that is, on a surface of the silicon nitride film 9 in the present embodiment.

Examples of the aminosilane-based gas may be the same as those of the seed layer 8. In the present embodiment, DIPAS is used.

Process conditions in process 41 are as follows:

DIPAS flow rate: 500 sccm,

process time: 0.5 min,

process temperature: 400° C., and

process pressure: 53 Pa (0.4 Torr).

It is preferable that a thickness of the seed layer 10 be about a thickness of an monoatomic layer level, similar to the seed layer 8. Specifically, the thickness of the seed layer 10 is equal to or greater than 0.1 nm and equal to or less than 0.3 nm.

Next, as shown in process 42 of FIG. 1 and in FIG. 2G, a silicon film 11 is formed on the seed layer 10. In detail, the silicon substrate 1 on which the seed layer 10 is formed is heated, and then a silane-based gas not including an amino group, for example, a monosilane gas, is supplied to a surface of the silicon substrate 1 which is heated to form the silicon film 11 on the surface of the silicon substrate 1, that is, on a surface of the seed layer 10 in the present embodiment.

Process conditions in process 42 are as follows:

monosilane flow rate: 800 sccm,

process time: 4 min,

process temperature: 535° C., and

process pressure: 60 Pa (0.45 Torr).

Under the above-described conditions, the silicon film 11, which is amorphous, is formed to have a thin thickness in a range of about 3 to about 9 nm within a process time (deposition time) in a range of about 3 to about 5 min. A thickness of the silicon film 11 plays an important role in offsetting contraction of an embedding material to be formed later. Of course, an offset amount may be determined according to a sum of the minute thickness of the seed layer 10 and the thickness of the silicon film 11, but the seed layer 10 is a layer for catalyzing adsorption of monosilane and has a negligible thickness. Accordingly, a thickness of the silicon film 11 after being expanded may make up most of the offset amount. That is, the offset amount is substantially determined according to the thickness of the silicon film 11.

Also, in the present embodiment, monosilane is used as a raw material of the silicon film 11.

Also, if a high-order silane having an order higher than monosilane, for example, disilane (Si2H6), is supplied to previously form a silicon layer on the surface of the seed layer 10 before supplying monosilane, step coverage of the silicon film 11 may be improved compared to a case where monosilane is directly supplied to the seed layer 10. However, if the silicon layer formed by the high-order silane is excessively thick, the step coverage of the silicon film 11 may be degraded, and thus the silicon layer may be formed thin. For example, a film thickness of the silicon layer formed by the high-order silane, which does not degrade the step coverage, exceeds 0 nm and is equal to or less than 0.5 nm. Also, process conditions when the thin silicon layer is formed by the high-order silane are as follows:

disilane flow rate: 200 sccm,

process time: 3 min,

process temperature: 400° C., and

process pressure: 133 Pa (1 Torr).

If the step coverage of the silicon film 11 may be improved, a film thickness of the silicon film 11 formed on the side wall of the trench 6 may be almost the same as a film thickness of the silicon film 11 formed on an upper surface of the silicon substrate 1. Accordingly, when the silicon film 11 formed on the side wall of the trench 6 is completely oxidized, the silicon film 11 formed on the upper surface of the silicon substrate 1 may be completely oxidized, and thus the silicon film 11 no longer remains.

However, in an embodiment of the present invention, a raw material other than monosilane may be selected because the oxidization barrier film, that is, the silicon nitride film 9 in the present embodiment, exists on the trench 6. Accordingly, although the film thickness of the silicon film 11 formed on the side wall of the trench 6 is different from the film thickness of the silicon film 11 formed on the upper surface of the silicon substrate 1, even when the silicon film 11 is oxidized under a condition where the thicker of the film thicknesses of the silicon film 11 is completely oxidized, oxidization may be prevented from reaching the silicon substrate 1.

Accordingly, the following raw materials may be used as the raw material of the silicon film 11.

Examples of a silane-based gas not including an amino group may be a gas including at least one of:

SiH2,

SiH4,

SiH6,

Si2H4,

Si2H6,

a silicon hydride that may be expressed as SimH2m+2 (here, m is a natural number equal to or greater than 3), and

a silicon hydride that may be expressed as SinH2n (here, n is a natural number equal to or greater than 3).

Also, when the silicon film 11 is formed using a low-order silane-based gas not including an amino group such as monosilane (SiH4) in one or two processes, it is preferable that a higher-order silane-based gas not including an amino group, for example, disilane (Si2H6), be previously supplied before supplying the low-order silane-based gas not including an amino group, as described above.

As such, according to a method of supplying a low-order silane-based gas not including an amino group after supplying a higher-order silane-based gas not including an amino group, the step coverage of the silicon film 11 may be improved as described above, and also an incubation time of the silicon film 11 may be reduced.

Next, as shown in process 5 of FIG. 1 and in FIG. 2H, the trench 6 is embedded by using an embedding material 12 that contracts by being fired. For example, the trench 6 is embedded by spin coating the embedding material 12 in a liquid phase, which is changed into silicon oxide by being fired, on a surface of the silicon substrate 1 on which the silicon film 11 is formed.

An example of a material that changes into silicon oxide by being fired may include an inorganic polymer mainly including PHPS (perhydropolysilazane: SiH2NH).

Finally, as shown in process 6 of FIG. 1 and in FIG. 2I, the embedding material 12 is fired in an atmosphere including water and/or a hydroxyl group to be changed into a silicon oxide 13 and to change the silicon film 11 and the seed layer 10 into a silicon oxide 14. In detail, the silicon substrate 1 coated with the embedding material 12 is fired in an atmosphere including water and/or a hydroxyl group to change the embedding material 12 into the silicon oxide 13 and to change the silicon film 11 and the seed layer 10 into the silicon oxide 14.

Process conditions in process 6 are as follows:

H2O flow rate: 10 L/min,

process time: 45 min,

process temperature: 750° C., and

process pressure: 53200 Pa (400 Torr).

In process 6, the oxidization barrier film, that is, the silicon nitride film 9 in the present embodiment, serves as an oxidization barrier to the silicon substrate 1. Accordingly, although process 6 is performed, oxidization to the silicon substrate 1 does not occur. When the trench 6 is used in a device isolation area in a semiconductor integrated circuit device, for example, used in a shallow trench isolation, oxidization to the silicon substrate 1 does not occur, and thus a device active area where an active element such as a transistor is formed may be prevented from being reduced due to oxidization.

When the embedding material 12 is fired to be changed into the silicon oxide 13, the embedding material 12 contracts. On the contrary, the silicon film 11 and the seed layer 10 expand when being changed into the silicon oxide 14. As such, the contraction of the embedding material 12 is offset by the expansion of the silicon film 11 and the seed layer 10, thereby preventing a gap from being generated on the trench 6.

(Incubation Time)

A problem of a long incubation time of monosilane has been resolved by pre-flowing an aminosilane-based gas to a surface of the silicon substrate 1, that is, a surface of the silicon nitride film 9 in the present embodiment, to form the seed layer 10, and then forming the silicon film 11.

FIG. 3 is a view showing a relationship between a deposition time and a film thickness of the silicon film 11. A result shown in FIG. 3 is obtained when a base is a silicon nitride film (SiN). In the present embodiment, the silicon nitride film corresponds to the silicon nitride film 9.

Process conditions in the pre-flow process used in the present embodiment are as follows:

DIPAS flow rate: 500 sccm,

process time: 5 min

process temperature: 400° C., and

process pressure: 53.2 Pa (0.4 Torr).

Process conditions in the process for forming the silicon film 11 used in the present embodiment are as follows:

monosilane flow rate: 500 sccm

deposition time: 30 min/45 min/60 min

process temperature: 500° C.

process pressure: 53.2 Pa (0.4 Torr).

The film thickness of the silicon film 11 was measured at three points when the deposition time was 30 min, 45 min, and 60 min.

Line I and line II shown in FIGS. 3 and 4 show a result obtained in a case where the pre-flow process is performed and a result obtained in a case where the pre-flow process is not performed, respectively. The line I and the line II are straight lines obtained by straight-line approximating the three measured film thicknesses by using a least-squares method. Formulas thereof are as follows:
Line I: y=18.011x−27.739  (1), and
Line II: y=18.091x−41.277  (2).

As shown in FIG. 3, in the case where the pre-flow process is performed, the film thickness of the silicon film 11 is much more increased, compared to the case where the pre-flow process is not performed.

In the above-described formulas (1) and (2), when y is 0, that is, when the film thickness of the silicon film 11 is “0”, intersection points between the lines I and II and deposition time are measured, and a result of the measuring is shown in FIG. 4. Also, FIG. 4 is an enlarged view of the portion A of FIG. 3 indicated by the broken line.

As shown in FIG. 4, in a case where the pre-flow process is performed, when a base is a silicon nitride film, deposition of the silicon film 11 begins about 1.5 min (x≈1.540) after the process begins. On the other hand, in a case where the pre-flow process is not performed, when a base is a silicon nitride film, deposition of the silicon film 11 begins about 2.3 min (x≈2.282) after the process begins.

As such, the pre-flow process with the aminosilane-based gas may be performed to the silicon nitride film 9 so as to reduce the incubation time from about 2.3 min to about 1.5 min. Accordingly, the silicon film 11 obtained may be thin.

Also, a problem of a long incubation time of the silicon nitride film 9 has been resolved by pre-flowing an aminosilane-based gas to a surface of the silicon substrate 1, that is, a surface of the silicon nitride film 9 in the present embodiment, to form the seed layer 10, and then forming the silicon film 11.

FIG. 5 is a view showing a relationship between an ALD cycle and a film thickness of the silicon nitride film 9. A result shown in FIG. 5 is obtained when a base is an oxide silicon film (SiO2). In the present embodiment, the oxide silicon film corresponds to the oxidization film 7.

Process conditions in the pre-flow process used in the present embodiment are as follows:

DIPAS flow rate: 150 sccm,

process time: 0.5 min,

process temperature: 450° C., and

process pressure: 532 Pa (4 Torr).

Process conditions in the process for forming the silicon nitride film 9 used in the present embodiment are as follows:

dichlorosilane flow rate: 1000 sccm,

ammonia flow rate: 5000 sccm,

process temperature: 630° C., and

process pressure: 51 Pa (0.386 Torr).

The film thickness of the silicon nitride film 9 was measured when the ALD cycle was 30 cycles, 50 cycles, and 70 cycles.

Line I and line II shown in FIG. 5 show a result obtained in a case where the pre-flow process is performed and a result obtained in a case where the pre-flow process is not performed, respectively. The line I and the line II are straight lines obtained by straight-line approximating the three measured film thicknesses by using a least-squares method. Formulas thereof are as follows:
Line I: y=0.9265x−14.181  (3), and
Line II: y=0.9159x−21.846  (4)

In the above-described formulas (3) and (4), when y is 0, that is, when the film thickness of the silicon nitride film is “0”, the ALD cycles are as follows.

Line I: 19 cycles

Line II: 24 cycles (comparative example)

That is, by performing the pre-flow process on the base before forming the silicon nitride film 9, the number of cycles when the silicon nitride film 9 starts to grow may be shortened from 24 cycles, that is, the number of cycles when the pre-flow process is not performed on the base, to 19 cycles.

Thus, by performing the pre-flow process on the base, the incubation time of the silicon nitride film 9 may be shortened, compared to a case where the silicon nitride film 9 is directly formed on the oxidization film 7. Accordingly, the silicon nitride film 9 obtained may be thin.

According to the trench embedding method of an embodiment of the present invention, the incubation times of the oxidization barrier film (the silicon nitride film 9 in the present embodiment) formed on the trench 6 and of the expandable film (the silicon film 11 and the seed layer 10 in the present embodiment) may be shortened, respectively. Accordingly, since the oxidization barrier film and the expandable film may be formed thin, even if the trench 6 is further miniaturized, the trench embedding method allows the expandable film and a film serving as an oxidization barrier to be formed on the trench 6.

(Film-Forming Apparatus)

Next, a film-forming apparatus capable of performing the trench embedding method according to an embodiment of the present invention will be described hereinafter.

FIG. 6 is a cross-sectional view schematically showing a film-forming apparatus 100 capable of performing the trench embedding method according to an embodiment of the present invention.

As shown in FIG. 6, the film-forming apparatus 100 includes a process chamber 101 having a shape of a bottom-open cylinder with a ceiling. The entire process chamber 101 is formed of quartz, for example. A quartz ceiling plate 102 is provided on the ceiling of the process chamber 101. A manifold 103, which is molded of a stainless steel, for example, and has a cylindrical shape, is connected to a bottom opening of the process chamber 101 via a sealing member 104, such as an O-ring.

The manifold 103 supports the bottom of the process chamber 101. A quartz wafer boat 105, on which a plurality of, for example, 50 to 100, semiconductor substrates (the silicon substrates 1 in the present embodiment) as objects to be processed can be held in multiple layers, may be inserted from below the manifold 103 into the process chamber 101. The wafer boat 105 has a plurality of pillars 106, so that a plurality of the silicon substrates 1 are supported by grooves formed on the pillars 106.

The wafer boat 105 is disposed on a table 108 via a quartz thermos vessel 107. The table 108 is supported by a rotation shaft 110, which penetrates, for example, a stainless steel cover unit 109 for opening and closing the bottom opening of the manifold 103. A magnetic fluid seal 111, for example, is provided on a portion of the rotation shaft 110 penetrating the cover unit 109 so as to tightly seal the rotation shaft 110 and to rotatably support the rotation shaft 110. A sealing member 112, e.g., an O-ring, is installed between the peripheral portion of the cover unit 109 and the bottom of the manifold 103. Accordingly, sealing of the process chamber 101 is held. The rotation shaft 110 is attached to the leading end of an arm 113 supported by an elevating mechanism (not shown), such as a boat elevator, or the like. Therefore, the wafer boat 105, the cover unit 109, and the like are elevated together and are inserted to and pulled out from the process chamber 101.

The film-forming apparatus 100 includes a process gas supply mechanism 114 supplying a gas used in a process into the process chamber 101, and an inert gas supply mechanism 115 supplying an inert gas into the process chamber 101.

The process gas supply mechanism 114 includes an aminosilane-based gas supply source 117, a silane-based gas supply source 118, and a nitriding agent-including gas supply source 119. An example of a nitriding agent-including gas is a gas including ammonia.

The inert gas supply mechanism 115 includes an inert gas supply source 120. An inert gas is used as a purge gas or the like. An example of the inert gas is a nitrogen (N2) gas.

The aminosilane-based gas supply source 117 is connected to a distribution nozzle 123 through a flow rate controller 121 a and an opening/closing valve 122 a. The distribution nozzle 123, for example, a quartz pipe, inwardly passes through a side wall of the manifold 103, is bent upward, and vertically extends. A plurality of gas ejection holes 124 are provided at predetermined intervals in a vertical portion of the distribution nozzle 123. The aminosilane-based gas is substantially uniformly ejected into the process chamber 101 in a horizontal direction from the gas ejection holes 124.

Also, the silane-based gas supply source 118 is connected to, for example, the distribution nozzle 123, through a flow rate controller 121 b and an opening/closing valve 122 b.

The nitriding agent-including gas supply source 119 is connected to a distribution nozzle 125 through a flow rate controller 121 c and an opening/closing valve 122 c. The distribution nozzle 125, for example, a quartz pipe, inwardly passes through the side wall of the manifold 103, is bent upward, and vertically extends. A plurality of gas ejection holes 126 are provided at predetermined intervals in a vertical portion of the distribution nozzle 125. A gas including ammonia is substantially uniformly ejected into the process chamber 101 in a horizontal direction from the gas ejection holes 126.

The inert gas supply source 120 is connected to a nozzle 128 through a flow rate controller 121 d and an opening/closing valve 122 d. The nozzle 128 passes through the side wall of the manifold 103, and allows an inert gas to be ejected into the process chamber 101 in a horizontal direction from a leading end of the nozzle 128.

An exhaust port 129 for evacuating an inside of the process chamber 101 is provided at a portion of the process chamber 101 opposite to the distribution nozzles 123 and 125. The exhaust port 129 is longitudinally and narrowly provided by vertically cutting off a side wall of the process chamber 101. An exhaust port cover member 130 having a U-shaped cross-section and provided to cover the exhaust port 129 is attached by being welded to a portion of the process chamber 101 corresponding to the exhaust port 129. The exhaust port cover member 130 extends upward along the side wall of the process chamber 101 to define a gas outlet 131 at an upper side of the process chamber 101. An exhauster 132 including a vacuum pump or the like is connected to the gas outlet 131. The exhauster 132 exhausts a process gas used in a process from the process chamber 101, and makes a pressure in the process chamber 101 be a process pressure according to a process.

A heating device 133 having a cylindrical shape is provided around an outer circumference of the process chamber 101. The heating device 133 activates a gas supplied into the process chamber 101, and heats the object to be processed, that is, the silicon substrate 1 in the present embodiment, held in the process chamber 101 by heating the inside of the process chamber 101.

Each element of the film-forming apparatus 100 is controlled by a controller 150 including, for example, a microprocessor (computer). A user interface 151 including a keyboard for inputting a command in order for an operator to manage the film-forming apparatus 100, a display that visually displays an operation state of the film-forming apparatus 100, and so on is connected to the controller 150.

A memory unit 152 is connected to the controller 150. A control program for performing various processes performed in the film-forming apparatus 100 under the control of the controller 150, or a program, that is, a recipe, for performing a process in each element of the film-forming apparatus 100 according to process conditions is stored in the memory unit 152. The recipe is stored in, for example, a storage medium, of the memory unit 152. The storage medium may be a hard disk or a semiconductor memory, or a portable type such as a CD-ROM, a DVD, or a flash memory. Also, the recipe may be appropriately transmitted from another device via, for example, a dedicated line. If required, desired processes are performed by the film-forming apparatus 100 under the control of the controller 150 by invoking a recipe from the memory unit 152 according to instructions or the like from the user interface 151 and performing a process based on the recipe in the controller 150.

In the present embodiment, under the control of the controller 150, processes according to processes 31, 32, 41, and 42 of the trench embedding method are sequentially performed.

In the processes for forming the seed layer 8 in process 31 and the seed layer 10 in process 41, an aminosilane-based gas (for example, DIPAS) is supplied to the process chamber 101 from the aminosilane-based gas supply source 117. Also, in the process for forming the silicon nitride film 9 in process 32, a silane-based gas (for example, dichlorosilane) and a gas including a nitriding agent (for example, a gas including ammonia) are supplied to the process chamber 101 from the silane-based gas supply source 118 and the nitriding agent-including gas supply source 119, respectively. Also, in the process for forming the silicon film 11 in process 42, a silane-based gas (for example, monosilane) is supplied from the silane-based gas supply source 118.

The controller 150 controls the process gas supply mechanism 114, the exhauster 132, and the heating device 133 to perform the processes of processes 31, 32, 41, and 42.

Also, in order to form the silicon nitride film 9, an ALD (atomic layer deposition) method or an MLD (molecular layer deposition) method for forming a film by alternately supplying a gas including silicon (for example, a silane-based gas) and a gas including a nitriding agent may be used, or alternatively, a so-called CVD (chemical vapor deposition) method by simultaneously supplying a gas including silicon and a gas including a nitriding agent may be used.

The trench embedding method according to the embodiment of the present invention may be performed by the film-forming apparatus 100 of FIG. 6.

Although the present invention has been explained with reference to the embodiments, the present invention is not limited to the embodiments, and various modifications may be made. Also, the embodiments of the present invention are not unique embodiments.

For example, in the embodiment of the present invention, although the silicon nitride film 9 is formed as the oxidization barrier film, the oxidization film 7 may be nitrided. Examples of a nitriding process of the oxidization film 7 may include a plasma nitriding process, a process of changing the oxidization film 7 into an SiON film by FNC nitriding (NO, N2O, NH3) or the like.

Also, although a thermal ALD method or a thermal MLD method is used to form the silicon nitride film 9 in the above-described embodiment, a plasma ALD method or a plasma MLD method may also be used to form the silicon nitride film 9.

Process conditions when a plasma ALD method or a plasma MLD method is used to form the silicon nitride film 9 are as follows:

dichlorosilane flow rate: 1000 sccm,

ammonia flow rate: 5000 sccm,

process temperature: 630° C.,

process pressure: 51 Pa (0.386 Torr), and

RF power: 100 W.

The above-described process conditions are applicable to the process conditions in process 32 of FIG. 1.

Also, in the above-described embodiment, since an oxidization barrier film is formed or an oxidization film is nitrided, freedom in choosing a raw material of the silicon film 11 may be obtained. Examples of a silane-based gas not including an amino-group have been described as the raw material of the silicon film 11. The examples may include a silicon hydride expressed as SimH2m+2 (here, m is a natural number equal to or greater than 3) and a silicon hydride expressed as SinH2n (here, n is a natural number equal to or greater than 3).

The silicon hydride expressed as SimH2m+2 (here, m is a natural number equal to or greater than 3) may be at least one of:

trisilane (Si3H8),

tetrasilane (Si4H10),

pentasilane (Si5H12),

hexasilane (Si6H14), and

heptasilane (Si7H16).

Furthermore, the silicon hydride expressed as SinH2n (here, n is a natural number equal to or greater than 3) is at least one of:

cyclotrisilane (Si3H6),

cyclotetrasilane (Si4H8),

cyclopentasilane (Si5H10),

cyclohexasilane (Si6H12), and

cycloheptasilane (Si7H14).

Also, in the above-described embodiment, spin coating glass, for example, PHPS, is used as the embedding material 12, which contracts by being fired. However, the embedding material 12 is not limited to the spin coating glass, and a CVD-based embedding material that contracts by being fired may also be used. Examples of the CVD-based embedding material may include a SiO2 film formed by using a HDP (high-density plasma), an SiO2 film formed by using an SiH4-based gas and hydrogen peroxide (H2O2), and the like.

Also, various other modifications may be made in the present invention without departing from the scope of the invention.

The present invention may provide a trench embedding method that allows an expandable film and a film serving as an oxidization barrier to be formed on a trench even if the trench is further miniaturized, and a film-forming apparatus capable of performing the trench embedding method.

While this invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

What is claimed is:
1. A trench embedding method comprising:
forming an oxidization film on a trench formed on a semiconductor substrate by oxidizing the semiconductor substrate on which the trench is formed;
forming an oxidization barrier film on the oxidization film;
forming an expandable film on the oxidization barrier film;
embedding an embedding material that contracts by being fired on the trench where the oxidization barrier film and the expandable film are formed; and
firing the embedding material,
wherein the forming of the oxidization barrier film comprises:
forming a first seed layer on the oxidization film by supplying an aminosilane-based gas to the semiconductor substrate on which the oxidization film is formed; and
forming a silicon nitride film on the first seed layer,
wherein the forming of the expandable film comprises:
forming a second seed layer on the silicon nitride film by supplying an aminosilane-based gas to the semiconductor substrate on which the silicon nitride film is formed; and
forming a silicon film on the second seed layer.
2. The trench embedding method of claim 1, wherein radical oxidization or plasma oxidization is used in the forming of the oxidization film.
3. The trench embedding method of claim 1, wherein the aminosilane-based gas is selected from among gases including at least one of:
BAS (butylaminosilane);
BTBAS (bis(tertiarybutylamino)silane);
DMAS (dimethylaminosilane);
BDMAS (bis(dimethylamino)silane);
TDMAS (tri(dimethylamino)silane);
DEAS (diethylaminosilane);
BDEAS (bis(diethylamino)silane);
DPAS (dipropylaminosilane); and
DIPAS (diisopropylaminosilane).
4. The trench embedding method of claim 1, wherein a silane-based gas not including an amino-group is used in the forming of the silicon film.
5. The trench embedding method of claim 4, wherein the silicon film is formed by supplying a high-order silane-based gas not including an amino group and then supplying a silane-based gas not including an amino group that is lower than the high-order silane-based gas not including an amino group.
6. The trench embedding method of claim 5, wherein a film thickness of the silicon layer formed of the high-order silane-based gas not including an amino group exceeds 0 nm and is equal to or less than 0.5 nm.
7. The trench embedding method of claim 4, wherein the silane-based gas not including an amino group is selected from among gases including at least one of:
SiH2;
SiH4;
SiH6;
Si2H4;
Si2H6;
a silicon hydride expressed as SimH2m+, where m is a natural number equal to or greater than 3; and
a silicon hydride expressed as SinH2n, where n is a natural number equal to or greater than 3.
8. The trench embedding method of claim 7, wherein the silicon hydride expressed as SimH2m+2 is selected from at least one of:
trisilane (Si3H8);
tetrasilane (Si4H10);
pentasilane (Si5H12);
hexasilane (Si6H14); and
heptasilane (Si7H16) and
the silicon hydride expressed as SinH2n is selected from at least one of:
cyclotrisilane (Si3H6);
cyclotetrasilane (Si4H8);
cyclopentasilane (Si5H10);
cyclohexasilane (Si6H12); and
cycloheptasilane (Si7H14).
9. The trench embedding method of claim 1, wherein the trench embedding method is used in a process for manufacturing a semiconductor device.
10. The trench embedding method of claim 9, wherein the trench is used in a device isolation area provided in the semiconductor device.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120028437A1 (en) * 2010-07-29 2012-02-02 Tokyo Electron Limited Trench-filling method and film-forming system
US20120178264A1 (en) * 2010-12-21 2012-07-12 Tokyo Electron Limited Method and apparatus for forming silicon nitride film
US20140187024A1 (en) * 2012-12-27 2014-07-03 Tokyo Electron Limited Method of forming seed layer, method of forming silicon film, and film forming apparatus
US20140187025A1 (en) * 2012-12-27 2014-07-03 Tokyo Electron Limited Method of forming silicon film and film forming apparatus
US20150064929A1 (en) * 2013-09-05 2015-03-05 United Microelectronics Corp. Method of gap filling
US20150270160A1 (en) * 2014-03-19 2015-09-24 Tokyo Electron Limited Method and apparatus for forming silicon oxide film

Families Citing this family (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10378106B2 (en) 2008-11-14 2019-08-13 Asm Ip Holding B.V. Method of forming insulation film by modified PEALD
US9394608B2 (en) 2009-04-06 2016-07-19 Asm America, Inc. Semiconductor processing reactor and components thereof
JP2012138500A (en) * 2010-12-27 2012-07-19 Tokyo Electron Ltd Method for forming silicon oxide film on tungsten film or tungsten oxide film and film forming device
US9793148B2 (en) 2011-06-22 2017-10-17 Asm Japan K.K. Method for positioning wafers in multiple wafer transport
US10364496B2 (en) 2011-06-27 2019-07-30 Asm Ip Holding B.V. Dual section module having shared and unshared mass flow controllers
JP5977002B2 (en) * 2011-08-25 2016-08-24 東京エレクトロン株式会社 Trench filling method and semiconductor integrated circuit device manufacturing method
US9017481B1 (en) 2011-10-28 2015-04-28 Asm America, Inc. Process feed management for semiconductor substrate processing
US8946830B2 (en) 2012-04-04 2015-02-03 Asm Ip Holdings B.V. Metal oxide protective layer for a semiconductor device
KR101862547B1 (en) * 2012-04-13 2018-05-31 삼성전자주식회사 Method of forming a polysilicon layer and method of manufactruing semiconductir devices
US9558931B2 (en) 2012-07-27 2017-01-31 Asm Ip Holding B.V. System and method for gas-phase sulfur passivation of a semiconductor surface
US9659799B2 (en) 2012-08-28 2017-05-23 Asm Ip Holding B.V. Systems and methods for dynamic semiconductor process scheduling
US9021985B2 (en) 2012-09-12 2015-05-05 Asm Ip Holdings B.V. Process gas management for an inductively-coupled plasma deposition reactor
JP6022273B2 (en) 2012-09-14 2016-11-09 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing method, substrate processing apparatus, and program
US9324811B2 (en) 2012-09-26 2016-04-26 Asm Ip Holding B.V. Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same
US8784951B2 (en) 2012-11-16 2014-07-22 Asm Ip Holding B.V. Method for forming insulation film using non-halide precursor having four or more silicons
US9640416B2 (en) 2012-12-26 2017-05-02 Asm Ip Holding B.V. Single-and dual-chamber module-attachable wafer-handling chamber
US9589770B2 (en) 2013-03-08 2017-03-07 Asm Ip Holding B.V. Method and systems for in-situ formation of intermediate reactive species
US9484191B2 (en) 2013-03-08 2016-11-01 Asm Ip Holding B.V. Pulsed remote plasma method and system
US8993054B2 (en) 2013-07-12 2015-03-31 Asm Ip Holding B.V. Method and system to reduce outgassing in a reaction chamber
US9018111B2 (en) 2013-07-22 2015-04-28 Asm Ip Holding B.V. Semiconductor reaction chamber with plasma capabilities
US9793115B2 (en) 2013-08-14 2017-10-17 Asm Ip Holding B.V. Structures and devices including germanium-tin films and methods of forming same
US9240412B2 (en) 2013-09-27 2016-01-19 Asm Ip Holding B.V. Semiconductor structure and device and methods of forming same using selective epitaxial process
US9556516B2 (en) 2013-10-09 2017-01-31 ASM IP Holding B.V Method for forming Ti-containing film by PEALD using TDMAT or TDEAT
US10179947B2 (en) 2013-11-26 2019-01-15 Asm Ip Holding B.V. Method for forming conformal nitrided, oxidized, or carbonized dielectric film by atomic layer deposition
US10167557B2 (en) 2014-03-18 2019-01-01 Asm Ip Holding B.V. Gas distribution system, reactor including the system, and methods of using the same
US9447498B2 (en) 2014-03-18 2016-09-20 Asm Ip Holding B.V. Method for performing uniform processing in gas system-sharing multiple reaction chambers
US9404587B2 (en) 2014-04-24 2016-08-02 ASM IP Holding B.V Lockout tagout for semiconductor vacuum valve
US9543180B2 (en) 2014-08-01 2017-01-10 Asm Ip Holding B.V. Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
US9890456B2 (en) 2014-08-21 2018-02-13 Asm Ip Holding B.V. Method and system for in situ formation of gas-phase compounds
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US10087525B2 (en) 2015-08-04 2018-10-02 Asm Ip Holding B.V. Variable gap hard stop design
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US9711345B2 (en) 2015-08-25 2017-07-18 Asm Ip Holding B.V. Method for forming aluminum nitride-based film by PEALD
US9960072B2 (en) 2015-09-29 2018-05-01 Asm Ip Holding B.V. Variable adjustment for precise matching of multiple chamber cavity housings
US9909214B2 (en) 2015-10-15 2018-03-06 Asm Ip Holding B.V. Method for depositing dielectric film in trenches by PEALD
US10211308B2 (en) 2015-10-21 2019-02-19 Asm Ip Holding B.V. NbMC layers
US10322384B2 (en) 2015-11-09 2019-06-18 Asm Ip Holding B.V. Counter flow mixer for process chamber
US9455138B1 (en) 2015-11-10 2016-09-27 Asm Ip Holding B.V. Method for forming dielectric film in trenches by PEALD using H-containing gas
US10121655B2 (en) 2015-11-20 2018-11-06 Applied Materials, Inc. Lateral plasma/radical source
US9905420B2 (en) 2015-12-01 2018-02-27 Asm Ip Holding B.V. Methods of forming silicon germanium tin films and structures and devices including the films
US9607837B1 (en) 2015-12-21 2017-03-28 Asm Ip Holding B.V. Method for forming silicon oxide cap layer for solid state diffusion process
US9627221B1 (en) 2015-12-28 2017-04-18 Asm Ip Holding B.V. Continuous process incorporating atomic layer etching
US9735024B2 (en) 2015-12-28 2017-08-15 Asm Ip Holding B.V. Method of atomic layer etching using functional group-containing fluorocarbon
US10529554B2 (en) 2016-02-19 2020-01-07 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US9754779B1 (en) 2016-02-19 2017-09-05 Asm Ip Holding B.V. Method for forming silicon nitride film selectively on sidewalls or flat surfaces of trenches
US10468251B2 (en) 2016-02-19 2019-11-05 Asm Ip Holding B.V. Method for forming spacers using silicon nitride film for spacer-defined multiple patterning
US10501866B2 (en) 2016-03-09 2019-12-10 Asm Ip Holding B.V. Gas distribution apparatus for improved film uniformity in an epitaxial system
US10343920B2 (en) 2016-03-18 2019-07-09 Asm Ip Holding B.V. Aligned carbon nanotubes
US9892913B2 (en) 2016-03-24 2018-02-13 Asm Ip Holding B.V. Radial and thickness control via biased multi-port injection settings
US10190213B2 (en) 2016-04-21 2019-01-29 Asm Ip Holding B.V. Deposition of metal borides
US10087522B2 (en) 2016-04-21 2018-10-02 Asm Ip Holding B.V. Deposition of metal borides
US10032628B2 (en) 2016-05-02 2018-07-24 Asm Ip Holding B.V. Source/drain performance through conformal solid state doping
US10367080B2 (en) 2016-05-02 2019-07-30 Asm Ip Holding B.V. Method of forming a germanium oxynitride film
KR20170129475A (en) 2016-05-17 2017-11-27 에이에스엠 아이피 홀딩 비.브이. Method of forming metal interconnection and method of fabricating semiconductor device using the same
US10388509B2 (en) 2016-06-28 2019-08-20 Asm Ip Holding B.V. Formation of epitaxial layers via dislocation filtering
US9859151B1 (en) 2016-07-08 2018-01-02 Asm Ip Holding B.V. Selective film deposition method to form air gaps
JP2018010950A (en) 2016-07-13 2018-01-18 東京エレクトロン株式会社 Deposition method of silicon nitride film
US9793135B1 (en) 2016-07-14 2017-10-17 ASM IP Holding B.V Method of cyclic dry etching using etchant film
KR20180012727A (en) 2016-07-27 2018-02-06 에이에스엠 아이피 홀딩 비.브이. Method of processing a substrate
US9812320B1 (en) 2016-07-28 2017-11-07 Asm Ip Holding B.V. Method and apparatus for filling a gap
US10177025B2 (en) 2016-07-28 2019-01-08 Asm Ip Holding B.V. Method and apparatus for filling a gap
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US10395919B2 (en) 2016-07-28 2019-08-27 Asm Ip Holding B.V. Method and apparatus for filling a gap
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US10410943B2 (en) 2016-10-13 2019-09-10 Asm Ip Holding B.V. Method for passivating a surface of a semiconductor and related systems
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US10290508B1 (en) 2017-12-05 2019-05-14 Asm Ip Holding B.V. Method for forming vertical spacers for spacer-defined patterning
EP3553815A3 (en) * 2018-03-20 2020-01-08 Samsung Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US10510536B2 (en) 2018-03-29 2019-12-17 Asm Ip Holding B.V. Method of depositing a co-doped polysilicon film on a surface of a substrate within a reaction chamber
US10388513B1 (en) 2018-07-03 2019-08-20 Asm Ip Holding B.V. Method for depositing silicon-free carbon-containing film as gap-fill layer by pulse plasma-assisted deposition
US10483099B1 (en) 2018-07-26 2019-11-19 Asm Ip Holding B.V. Method for forming thermally stable organosilicon polymer film
US10381219B1 (en) 2018-10-25 2019-08-13 Asm Ip Holding B.V. Methods for forming a silicon nitride film

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030068855A1 (en) * 2000-02-22 2003-04-10 Moore John T. Method for forming protective films and spacers
US20050085054A1 (en) * 2003-10-15 2005-04-21 Chakravarti Ashima B. Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
US20050186755A1 (en) * 2004-02-19 2005-08-25 Smythe John A.Iii Sub-micron space liner and densification process
US20090029532A1 (en) * 2007-07-23 2009-01-29 Industrial Technology Research Institute Method for forming a microcrystalline silicon film
US20100311251A1 (en) * 2009-06-04 2010-12-09 Tokyo Electron Limited Batch processing method for forming structure including amorphous carbon film
US20100314672A1 (en) * 2009-06-11 2010-12-16 Sony Corporation Semiconductor device, method for manufacturing same, and solid-state image sensing device
US20110275197A1 (en) * 2010-05-04 2011-11-10 Park Hong-Bum Semiconductor memory device, method of forming the same, and memory system

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003258082A (en) * 2002-03-04 2003-09-12 Toshiba Corp Manufacturing method for semiconductor device
JP2004273519A (en) * 2003-03-05 2004-09-30 Clariant (Japan) Kk Method of forming trench isolation structure
JP2005347636A (en) * 2004-06-04 2005-12-15 Az Electronic Materials Kk Method for forming trench isolation structure
CN100554506C (en) * 2005-03-09 2009-10-28 东京毅力科创株式会社 Film formation method and apparatus for semiconductor process
US7498273B2 (en) * 2006-05-30 2009-03-03 Applied Materials, Inc. Formation of high quality dielectric films of silicon dioxide for STI: usage of different siloxane-based precursors for harp II—remote plasma enhanced deposition processes
JP2008124211A (en) * 2006-11-10 2008-05-29 Fujitsu Ltd Method for manufacturing semiconductor device
KR101446331B1 (en) * 2008-02-13 2014-10-02 삼성전자주식회사 Method of manufacturing semiconductor device
JP5155070B2 (en) * 2008-09-02 2013-02-27 株式会社日立国際電気 Semiconductor device manufacturing method, substrate processing method, and substrate processing apparatus
JP4967066B2 (en) * 2010-04-27 2012-07-04 東京エレクトロン株式会社 Method and apparatus for forming amorphous silicon film
JP5490753B2 (en) * 2010-07-29 2014-05-14 東京エレクトロン株式会社 Trench filling method and film forming system

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030068855A1 (en) * 2000-02-22 2003-04-10 Moore John T. Method for forming protective films and spacers
US20050085054A1 (en) * 2003-10-15 2005-04-21 Chakravarti Ashima B. Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
US20050186755A1 (en) * 2004-02-19 2005-08-25 Smythe John A.Iii Sub-micron space liner and densification process
US7112513B2 (en) 2004-02-19 2006-09-26 Micron Technology, Inc. Sub-micron space liner and densification process
US20090029532A1 (en) * 2007-07-23 2009-01-29 Industrial Technology Research Institute Method for forming a microcrystalline silicon film
US20100311251A1 (en) * 2009-06-04 2010-12-09 Tokyo Electron Limited Batch processing method for forming structure including amorphous carbon film
US20100314672A1 (en) * 2009-06-11 2010-12-16 Sony Corporation Semiconductor device, method for manufacturing same, and solid-state image sensing device
US20110275197A1 (en) * 2010-05-04 2011-11-10 Park Hong-Bum Semiconductor memory device, method of forming the same, and memory system

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120028437A1 (en) * 2010-07-29 2012-02-02 Tokyo Electron Limited Trench-filling method and film-forming system
US8722510B2 (en) * 2010-07-29 2014-05-13 Tokyo Electron Limited Trench-filling method and film-forming system
US20120178264A1 (en) * 2010-12-21 2012-07-12 Tokyo Electron Limited Method and apparatus for forming silicon nitride film
US8753984B2 (en) * 2010-12-21 2014-06-17 Tokyo Electron Limited Method and apparatus for forming silicon nitride film
US20140187024A1 (en) * 2012-12-27 2014-07-03 Tokyo Electron Limited Method of forming seed layer, method of forming silicon film, and film forming apparatus
US20140187025A1 (en) * 2012-12-27 2014-07-03 Tokyo Electron Limited Method of forming silicon film and film forming apparatus
US9263256B2 (en) * 2012-12-27 2016-02-16 Tokyo Electron Limited Method of forming seed layer, method of forming silicon film, and film forming apparatus
US9293323B2 (en) * 2012-12-27 2016-03-22 Tokyo Electron Limited Method of forming silicon film
US20150064929A1 (en) * 2013-09-05 2015-03-05 United Microelectronics Corp. Method of gap filling
US20150270160A1 (en) * 2014-03-19 2015-09-24 Tokyo Electron Limited Method and apparatus for forming silicon oxide film

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