CN113013171A - 3D NAND memory device, manufacturing method thereof and semiconductor machine - Google Patents

3D NAND memory device, manufacturing method thereof and semiconductor machine Download PDF

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CN113013171A
CN113013171A CN202110232412.8A CN202110232412A CN113013171A CN 113013171 A CN113013171 A CN 113013171A CN 202110232412 A CN202110232412 A CN 202110232412A CN 113013171 A CN113013171 A CN 113013171A
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channel
silicon
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王秉国
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The invention provides a 3D NAND memory device and a manufacturing method thereof, and a semiconductor machine, comprising: providing a substrate, wherein a stacking layer is formed on the substrate, and a channel hole is formed in the stacking layer; and sequentially forming a storage function layer, a seed layer and a channel layer in the channel hole, wherein the channel layer comprises a silicon-germanium layer. In this way, a seed layer is formed on the storage function layer, and then the silicon germanium layer grows on the seed layer, so that the high-quality silicon germanium layer can be epitaxially grown on the seed layer due to the fact that the seed layer is the monoatomic layer, and the electrical performance of the 3D NAND memory device can be improved due to the fact that the silicon germanium layer has high carrier mobility.

Description

3D NAND memory device, manufacturing method thereof and semiconductor machine
Technical Field
The invention relates to the technical field of semiconductors, in particular to a 3D NAND memory device, a manufacturing method thereof and a semiconductor machine.
Background
In the preparation process of the 3D NAND memory, a first layer of a first Metal Oxide Semiconductor (MOS) layer is formed on a substrateSilicon nitride (SiN) layer and silicon oxide (SiO)2) A stacked structure in which layers are alternately stacked; the stack is then etched to form a Channel hole through the stack to the substrate. And then depositing a storage function layer on the side wall and the bottom of the channel hole, etching the storage function layer at the bottom of the channel hole to form an epitaxial structure at the bottom of the channel hole, and depositing a channel layer on the side wall and the bottom of the storage function layer and the surface of the exposed epitaxial structure.
At present, polysilicon is commonly used as a material of a channel layer, but the depth of a channel hole is continuously increased along with the increase of the number of stacked layers, and channel current is smaller and smaller when the polysilicon is used as the material of the channel layer, so that the performance of a device is influenced.
Disclosure of Invention
In view of the above, the present invention provides a 3D NAND memory device, a method for fabricating the same, and a semiconductor device to form a high quality sige layer in a channel hole.
In order to achieve the purpose, the invention has the following technical scheme:
a method of manufacturing a 3D NAND memory device, comprising:
providing a substrate, wherein a stacking layer is formed on the substrate, and a channel hole is formed in the stacking layer;
and sequentially forming a storage function layer, a seed layer and a channel layer in the channel hole, wherein the channel layer comprises a silicon-germanium layer.
Optionally, the seed layer is a silicon layer.
Optionally, forming a seed layer in the channel hole includes:
and forming a silicon layer by using diisopropylamine silane as a gas source at the temperature of 300-400 ℃.
Optionally, forming a channel layer in the channel hole includes:
and forming the silicon-germanium layer by using silane and germane as gas sources when the temperature is 500-600 ℃ and the pressure is less than 1 mTorr.
Optionally, the ratio of silicon and germanium in the silicon germanium layer is adjusted by adjusting the flow rate of the silane and/or the germane.
Optionally, the storage function layer includes a blocking layer, a charge storage layer, and a tunneling layer stacked in sequence, and the tunneling layer is made of silicon oxide or nitrogen-doped silicon oxide.
Optionally, the stacked layer includes an insulating layer and a sacrificial layer that are alternately stacked.
A 3D NAND memory device comprising:
a substrate having a stack layer formed thereon, the stack layer having a channel hole formed therein;
and a storage function layer, a seed layer and a channel layer are sequentially formed in the channel hole, and the channel layer comprises a silicon-germanium layer.
Optionally, the seed layer is a silicon layer.
Optionally, the storage function layer includes a blocking layer, a charge storage layer, and a tunneling layer stacked in sequence, and the tunneling layer is made of silicon oxide or nitrogen-doped silicon oxide.
A semiconductor machine for forming the memory device, comprising:
a reaction chamber for forming the seed layer and the channel layer;
the first input pipeline is used for introducing a gas source for forming the seed layer into the reaction chamber;
and the second input pipeline is used for introducing an air source for forming the channel layer into the reaction chamber.
The embodiment of the invention provides a manufacturing method of a 3D NAND memory device, which comprises the following steps: providing a substrate, wherein a stacking layer is formed on the substrate, and a channel hole is formed in the stacking layer; and sequentially forming a storage function layer, a seed layer and a channel layer in the channel hole, wherein the channel layer comprises a silicon-germanium layer. In this way, a seed layer is formed on the storage function layer, and then the silicon germanium layer grows on the seed layer, so that the high-quality silicon germanium layer can be epitaxially grown on the seed layer due to the fact that the seed layer is the monoatomic layer, and the electrical performance of the 3D NAND memory device can be improved due to the fact that the silicon germanium layer has high carrier mobility.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 shows a schematic diagram of a 3D NAND memory device;
FIG. 2 illustrates a flow diagram of a method of fabricating a 3D NAND memory device in accordance with an embodiment of the present invention;
FIGS. 3-5 illustrate schematic structural diagrams of a 3D NAND memory device in accordance with embodiments of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background, in the fabrication process of the 3D NAND memory, a silicon nitride (SiN) layer 122 and a silicon oxide (SiO) layer are first formed on a substrate 1002) A stacked structure in which the layers 121 are alternately stacked; the stack is then etched to form a Channel hole 124 in the stack. And epitaxially growing an epitaxial structure 110 at the bottom of the channel hole 124, the epitaxial structure 110 may serve as a channel layer of the lower select device. Then, a memory function layer 130 is deposited on the sidewall and the bottom of the channel hole 124, and the memory function layer 130 at the bottom of the channel hole 124 is etched by using a dry etching process until the epitaxial structure 110 at the bottom of the channel hole 124 is opened. Forming a channel layer 134 on the exposed epitaxial structure 110 and the sidewalls and bottom of the memory function layer 130 in the channel hole 124, as described with reference to fig. 1Shown in the figure.
At present, polysilicon is commonly used as a material of a channel layer, but the depth of a channel hole is continuously increased along with the increase of the number of stacked layers, and channel current is smaller and smaller when the polysilicon is used as the material of the channel layer, so that the performance of a device is influenced.
The applicant has found that silicon germanium (Si)1-xGex) The semiconductor alloy material has higher carrier mobility than polysilicon and can be used as the material of a channel layer. However, it is difficult to form a silicon germanium thin film on silicon oxide (SiO)2) Or silicon oxynitride (SiON) is grown on the memory function layer of the material and has more defects.
To this end, an embodiment of the present application provides a method of manufacturing a 3D NAND memory device, including: providing a substrate, wherein a stacking layer is formed on the substrate, and a channel hole is formed in the stacking layer; and sequentially forming a storage function layer, a seed layer and a channel layer in the channel hole, wherein the channel layer comprises a silicon-germanium layer. In this way, a seed layer is formed on the storage function layer, and then the silicon germanium layer grows on the seed layer, so that the high-quality silicon germanium layer can be epitaxially grown on the seed layer due to the fact that the seed layer is the monoatomic layer, and the electrical performance of the 3D NAND memory device can be improved due to the fact that the silicon germanium layer has high carrier mobility.
In order to facilitate understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2 and 3, in step S01, a substrate 200 is provided, the substrate 200 having a stack of layers formed thereon, the stack of layers having a channel hole 224 formed therein.
In the embodiment of the present application, the substrate 200 is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, InP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be other epitaxial structures, such as SGOI (silicon germanium on insulator) or the like. In the present embodiment, the substrate 200 is a bulk silicon substrate.
The stacked layer is used for forming a memory cell string perpendicular to the substrate direction, the stacked layer may include insulating layers 221 and sacrificial layers 222 which are alternately stacked, the stacked layer may be formed by a Single stack (Single stack) or may be formed by sequentially stacking a plurality of sub-stacks (Multiple stacks), and the more the number of insulating layers 221 or sacrificial layers 222 in the stacked layer is, the more memory cells are included in the formed memory cell string, and the higher the integration degree of the device is. The sacrificial layer 222 is used to occupy a position for a subsequently formed gate layer, the insulating layer 221 is located between adjacent sacrificial layers 222, between the sacrificial layers 222 and the substrate 200, and on the sacrificial layer 222 at the top layer, in a specific embodiment, the insulating layer 221 may be silicon oxide, and the sacrificial layer 222 may be silicon nitride.
In the embodiment of the present application, a channel hole 224 penetrating through the stacked layers to the substrate 200 is formed in the stacked layers, as shown in fig. 3, an epitaxial structure 210 may be formed at the bottom of the channel hole 224, and as shown in fig. 4, the epitaxial structure 210 may serve as a channel of the lower select device. The epitaxial structure 210 may be formed by epitaxially growing a semiconductor material, such as single crystal silicon, on the substrate 200. The process of forming the channel hole 224 may be to form a hard mask layer on the stack layer, spin-coat a photoresist layer on the hard mask layer, form a patterned photoresist layer through processes such as exposure and development, and the cured pattern of the photoresist layer may be determined by a mask used to form the channel hole in the 3D NAND memory manufacturing process. Then, the photoresist pattern is transferred onto the hard mask layer by an etching process, and the insulating layer 221 and the sacrificial layer 222 in the stack layer are etched with the hard mask layer as a mask. The layers are stacked, for example, using a dry etch to form a trench hole 224 exposing the substrate 200, and then the hard mask layer and photoresist layer may be removed.
In step S02, a memory function layer 230, a seed layer 234 and a channel layer 235 are sequentially formed in the channel hole 224, wherein the channel layer 235 includes a silicon germanium layer, as shown with reference to fig. 5.
In the embodiment of the present application, the storage function layer 230 is formed in the trench hole 224, and as shown in fig. 4, the storage function layer 230 is included at the sidewall and the bottom of the trench hole 224A blocking layer 231, a charge storage layer 232, and a Tunneling layer 233 are sequentially stacked. The blocking layer 231, the charge storage layer 232 and the tunneling layer 233 may be an ONO (Oxide-Nitride-Oxide) stack, i.e., a stack of Oxide, Nitride and Oxide, and specifically, the material of the tunneling layer 233 may be silicon Oxide or silicon Nitride-doped silicon Oxide. Subsequently, the blocking layer 231, the charge storage layer 232, and the tunneling layer 233 at the bottom of the trench hole 224 are etched to open the epitaxial structure 210. A seed layer 235 is grown on the sidewalls and bottom of the storage function layer 230 and the exposed surface of the epitaxial structure 210, and as shown in fig. 5, the seed layer 235 may be, for example, a silicon layer, and the silicon layer is a monoatomic layer, so as to facilitate the subsequent growth of a high-quality silicon germanium layer on the silicon layer. In the embodiment, Di-iso-propyllaminosilane (H) can be used at the temperature of 300-400 DEG C3Si[N(C3H7)2]) As a gas source, an atomic layer deposition process (ALD) is used to form a silicon layer. Specifically, a silicon layer is formed on the sidewalls and bottom of tunnel layer 233 and on the exposed surface of epitaxial structure 210.
Then, a channel layer 235 is formed on the surface of the seed layer 234, the channel layer 235 may be a silicon germanium layer, the silicon germanium is a semiconductor alloy material, and the silicon germanium has higher carrier mobility so as to improve channel current, thereby improving electrical performance of the device. Because the silicon layer is a monoatomic layer and the silicon germanium layer is grown on the surface of the silicon layer by utilizing an epitaxial growth technology, the silicon germanium layer can be orderly grown on the surface of the silicon layer so as to obtain a high-quality silicon germanium layer, and further, the channel current is improved. In this embodiment, the silicon-germanium layer may be formed by using silane and germane as a gas source and an Ultra High Vacuum Chemical Vapor Deposition (UHVCVD) process at a temperature of 500 to 600 ℃ and a pressure of less than 1 mTorr. The silane can be, for example, monosilane (SiH)4) Disilane (Si)2H4) The germane may be, for example, geremane (GeH-4). In specific application, the proportion of Si and Ge in the silicon-germanium layer can be adjusted by adjusting the flow of silane and/or germane, so that the Si and the Ge can be mixed and dissolved in any proportion, the energy band can be adjusted, and the electrical property of the device can be adjusted. For example, can be adjustedThe flow rate of silane is adjusted, or the flow rate of germane is adjusted, or the flow rates of silane and germane are adjusted simultaneously. Subsequently, a filling layer filled with an insulating material, such as silicon oxide, may be formed between the channel layers 235.
In this embodiment, the gate line gap is formed in the stacked layer, for example, the stacked layer may be etched by using a reactive ion etching method, so that the gate line gap exposing the substrate is formed in the stacked layer. After the gate line gap is formed, the sacrificial layer 222 in the stacked layer is removed through the gate line gap, the sacrificial layer 222 may be selectively corroded by an acid solution having a high selection ratio to the sacrificial layer 222 and the insulating layer 221, and after the sacrificial layer 222 is removed, a gate layer is formed by filling a metal in an area of the original sacrificial layer, where the filled metal may be tungsten or other metal that may be used as a gate. The Gate layers in the stack layer may include a Gate layer of the memory cell and a Gate layer of the select Gate, and the select Gate may include a Source Selection Gate (SSG) and/or a Drain Selection Gate (DSG). In a specific embodiment, a high-K gate dielectric layer material may be deposited prior to metal filling, thereby forming a high-K gate dielectric layer between the insulating layer 221 and the gate layer.
And then, other processing processes of the device, such as a common source process, a gate line gap filling process and the like, can be completed.
The above detailed description of the method for manufacturing a 3D NAND memory device provided by the embodiments of the present application, and the embodiments of the present application also provide a 3D NAND memory device, including:
a substrate 200, the substrate 200 having a stack of layers formed thereon, the stack of layers having a channel hole 224 formed therein;
a memory function layer 230, a seed layer 234 and a channel layer 235 are sequentially formed in the channel hole 224, and the channel layer 235 is a silicon germanium layer.
In the embodiment of the present application, a stack layer is formed on the substrate 200, and the stack layer may include alternately stacked insulating layers 221 and gate layers, where the insulating layers 221 are located between adjacent gate layers and between the gate layers and the substrate 200 for electrical isolation. The stack layer has a channel hole 224 formed therein, a storage function layer 230, a seed layer 234 and a channel layer 235 are sequentially formed in the channel hole 224, and the storage function layer 230 includes a blocking layer 231, a charge storage layer 232 and a tunneling layer 233, which are sequentially stacked at sidewalls and a bottom of the channel hole 224. The blocking layer 231, the charge storage layer 232, and the tunneling layer 233 may be an ONO stack, i.e., a stack of Oxide, Nitride, and Oxide. Specifically, the tunneling layer is made of silicon oxide or nitrogen-doped silicon oxide. In this embodiment, the seed layer 234 is a monoatomic silicon layer. The channel layer 235 is a silicon germanium layer, and since silicon germanium has high carrier mobility, channel current can be increased when the silicon germanium layer is used as the channel layer, and thus electrical properties of the device can be improved.
An embodiment of the present invention further provides a semiconductor device for forming the 3D NAND memory device, including:
a reaction chamber for forming the seed layer and the channel layer;
the first input pipeline is used for introducing a gas source for forming the seed layer into the reaction chamber;
and the second input pipeline is used for introducing a gas source for forming the channel layer into the reaction chamber.
In a specific application, the device is placed in a reaction chamber, a first input pipeline is opened, a second input pipeline is closed, and a gas source for forming a seed layer, such as H, is introduced into the reaction chamber by using the first input pipeline3Si[N(C3H7)2Meanwhile, the temperature of the reaction chamber can be controlled to be 300-400 ℃ to form a seed layer. And then, closing the first input pipeline, opening the second input pipeline, introducing a gas source for forming a channel layer, such as a mixed gas of silane and germane, into the reaction chamber by using the second input pipeline, and simultaneously controlling the temperature of the reaction chamber to be 500-600 ℃ and the pressure to be within 1mTorr so as to form a silicon-germanium layer on the surface of the seed layer.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for device embodiments, since they are substantially similar to method embodiments, they are described relatively simply, and reference may be made to some descriptions of the method embodiments for relevant points.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims (11)

1. A method of manufacturing a 3D NAND memory device, comprising:
providing a substrate, wherein a stacking layer is formed on the substrate, and a channel hole is formed in the stacking layer;
and sequentially forming a storage function layer, a seed layer and a channel layer in the channel hole, wherein the channel layer comprises a silicon-germanium layer.
2. The method of manufacturing of claim 1, wherein the seed layer is a silicon layer.
3. The method of manufacturing of claim 2, wherein forming a seed layer in the channel hole comprises:
and forming a silicon layer by using diisopropylamine silane as a gas source at the temperature of 300-400 ℃.
4. The manufacturing method according to any one of claims 1 to 3, wherein forming a channel layer in the channel hole includes:
and forming the silicon-germanium layer by using silane and germane as gas sources when the temperature is 500-600 ℃ and the pressure is less than 1 mTorr.
5. The method of manufacturing according to claim 4, wherein the ratio of silicon and germanium in the silicon germanium layer is adjusted by adjusting the flow rate of the silane and/or the germane.
6. The manufacturing method according to any one of claims 1 to 3, wherein the storage function layer comprises a blocking layer, a charge storage layer and a tunneling layer which are sequentially stacked, and the tunneling layer is made of silicon oxide or nitrogen-doped silicon oxide.
7. The manufacturing method according to any one of claims 1 to 3, wherein the stacked layers include insulating layers and sacrificial layers that are alternately stacked.
8. A 3D NAND memory device, comprising:
a substrate having a stack layer formed thereon, the stack layer having a channel hole formed therein;
and a storage function layer, a seed layer and a channel layer are sequentially formed in the channel hole, and the channel layer comprises a silicon-germanium layer.
9. The device of claim 8, wherein the seed layer is a silicon layer.
10. The device according to claim 8 or 9, wherein the storage function layer comprises a blocking layer, a charge storage layer and a tunneling layer which are sequentially stacked, and the tunneling layer is made of silicon oxide or nitrogen-doped silicon oxide.
11. A semiconductor tool for forming the memory device of any one of claims 8-10, comprising:
a reaction chamber for forming the seed layer and the channel layer;
the first input pipeline is used for introducing a gas source for forming the seed layer into the reaction chamber;
and the second input pipeline is used for introducing an air source for forming the channel layer into the reaction chamber.
CN202110232412.8A 2021-03-01 2021-03-01 3D NAND memory device, manufacturing method thereof and semiconductor machine Pending CN113013171A (en)

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