US8274840B2 - Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same - Google Patents

Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same Download PDF

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US8274840B2
US8274840B2 US12/498,508 US49850809A US8274840B2 US 8274840 B2 US8274840 B2 US 8274840B2 US 49850809 A US49850809 A US 49850809A US 8274840 B2 US8274840 B2 US 8274840B2
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memory
block
programming
memory cell
erased
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US20100091578A1 (en
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Yong-June Kim
Jae-Hong Kim
Kyoung-lae Cho
Seung-Hwan Song
Jun-jin Kong
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHO, KYOUNG LAE, KIM, JAE HONG, KIM, YONG JUNE, KONG, JUN JIN, SONG, SEUNG HWAN
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

Definitions

  • the present invention relates to integrated circuit memory devices and methods of operating same and, more particularly, to nonvolatile memory devices and methods of operating same.
  • Nonvolatile memory devices include electrically erasable programmable read only memory (EEPROM), which may be used in many applications including embedded applications and mass storage applications.
  • EEPROM electrically erasable programmable read only memory
  • embedded applications an EEPROM device may be used to provide code storage in personal computers or mobile phones, for example, where fast random access read times may be required.
  • mass storage applications include memory card applications requiring high capacity and low cost.
  • FIG. 1A illustrates a conventional flash memory array 10 having a plurality of NAND-type strings therein.
  • Each of these NAND-type strings includes a plurality of EEPROM cells, which are associated with respective even and odd bit lines (BL 0 _e, BL 0 _o, . . . , BLn_e, BLn_o).
  • BL 0 _e even and odd bit lines
  • BL 0 _o bit lines
  • Each EEPROM cell includes a floating gate electrode and a control gate electrode, which is electrically connected to a respective word line (WL 0 , WL 1 , . . . , WLn). Access to each NAND string is enabled by driving a string select line (SSL) to a logic 1 voltage during reading and programming operations. Each NAND string also includes a respective ground select transistor, which is electrically connected to a ground select line (GSL).
  • SSL string select line
  • GSL ground select line
  • the EEPROM cells within the flash memory array 10 of FIG. 1A may be cells that support a single programmed state.
  • EEPROM cells that support only a single programmed state are typically referred to as single level cells (SLC).
  • SLC single level cells
  • an SLC may support an erased state, which may be treated as a logic 1 storage value, and a programmed state, which may be treated as a logic 0 storage value.
  • the SLC may have a negative threshold voltage (Vth) when erased (e.g., ⁇ 3V ⁇ Vth ⁇ 1V) and a positive threshold voltage when programmed (e.g., 1V ⁇ Vth ⁇ 3V).
  • This programmed state may be achieved by setting the bit line BL to a logic 0 value (e.g., 0 Volts), applying a program voltage (Vpgm) to a selected EEPROM cell and applying a pass voltage (Vpass) to the unselected EEPROM cells within a string, as illustrated by FIG. 1C .
  • the NAND string may be enabled by applying a positive voltage (e.g., power supply voltage Vdd) to the string select line (SSL) and a ground voltage (e.g., 0 Volts) to the ground select line (GSL).
  • the programmed state or erased state of an EEPROM cell may be detected by performing a read operation on a selected cell.
  • a NAND string will operate to discharge a precharged bit line BL when a selected cell is in an erased state and the selected word line voltage (e.g., 0 Volts) is greater than the threshold voltage of the selected cell.
  • the selected word line voltage e.g., 0 Volts
  • the corresponding NAND string will provide an open circuit to the precharged bit line BL because the selected word line voltage (e.g., 0 Volts) is less than the threshold voltage of the selected cell and the selected cell remains “off”.
  • NAND-type flash memories are disclosed in an article by Jung et al., entitled “A 3.3 Volt Single Power Supply 16-Mb Nonvolatile Virtual DRAM Using a NAND Flash Memory Technology,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1748-1757, November (1997), the disclosure of which is hereby incorporated herein by reference.
  • EEPROM cells that support multiple programmed states are typically referred to as multi-level cells (MLC).
  • MLC multi-level cells
  • FIG. 2 an MLC that supports an erased state and three different programmed states operates to store two data bits per cell.
  • Nonvolatile memory systems support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells.
  • a nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device.
  • the memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.
  • the first instruction(s) can cause one-shot programming of all memory cells in the block of memory, including erased memory cells and previously programmed memory cells
  • the second instruction(s) can cause all memory cells within the block of memory to become fully erased, including the at least partially programmed memory cells.
  • the memory controller may utilize a timer that is activated in response to issuance of the first instruction(s).
  • the timer may be used by the memory controller to suspend issuance of the second instruction(s) during at least a time interval when the timer is active in response to issuance of the first instruction.
  • Additional embodiments of the present invention include methods of erasing a block of nonvolatile memory cells in a nonvolatile memory device by initially programming at least one of the nonvolatile memory cells in the block under conditions that cause a threshold voltage of the at least one of the nonvolatile memory cells to increase and then reducing threshold voltages of the at least one of the nonvolatile memory cells and other memory cells in the block to an erased threshold voltage level.
  • This programming of the at least one of the nonvolatile memory cells includes increasing a threshold voltage of a nonvolatile memory cell in the block from an erased threshold voltage level to an at least partially programmed threshold voltage level.
  • This programming of the at least one of the nonvolatile memory cells may also include increasing a threshold voltage of at least one already programmed nonvolatile memory cell in the block, such as during a one-shot programming operation.
  • Methods of operating nonvolatile memory devices include performing a block erase operation on a block of nonvolatile memory cells in the memory device by at least partially programming at least one erased memory cell in the block in advance of rendering all memory cells in the block as erased memory cells.
  • this performing a block erase operation may include executing a one-shot program operation by at least partially programming all memory cells in the block in advance of erasing all memory cells in the block.
  • a method of operating a nonvolatile memory device includes performing a block erase operation on a block of nonvolatile memory cells in the memory device by performing a memory cell recovery operation on the block of nonvolatile memory cells in advance of erasing the block of nonvolatile memory cells.
  • This memory cell recovery operation includes programming a first plurality of erased memory cells in the block to a first programmed state using a first verify voltage to confirm the programming and then further programming the first plurality of non-voltage memory cells within the first programmed state to achieve a narrower threshold voltage variation therein using a second verify voltage to confirm the further programming.
  • the step of programming the first plurality of nonvolatile memory cells in the block may be preceded by erasing all of the first plurality of nonvolatile memory cells in the block.
  • FIG. 1A is an electrical schematic of a conventional nonvolatile memory device having NAND-type strings of EEPROM cells therein.
  • FIG. 1B is a graph illustrating the relative threshold voltages of an erased and programmed EEPROM cell, according to the prior art.
  • FIG. 1C is an electrical schematic of a NAND-type string of EEPROM cells showing programming bias conditions.
  • FIG. 1D illustrates current flow in a NAND-type string during operations to read data from an erased EEPROM cell and a programmed EEPROM cell according to the prior art.
  • FIG. 2 is a graph illustrating the relative threshold voltages of a four-state EEPROM cell according to the prior art.
  • FIG. 3B is a flow-diagram of operations performed by a non-volatile memory system, according to embodiments of the present invention.
  • FIG. 4A is a flow-diagram of operations performed by a non-volatile memory system, according to embodiments of the present invention.
  • FIGS. 4B-4D illustrate memory cell recovery operations according to embodiments of the present invention.
  • FIG. 5A is a flow-diagram of operations performed by a non-volatile memory system, according to embodiments of the present invention.
  • FIGS. 5B-5D illustrate memory cell recovery operations according to embodiments of the present invention.
  • FIG. 6A is a flow-diagram of operations performed by a non-volatile memory system, according to embodiments of the present invention.
  • FIGS. 6B-6E illustrate memory cell recovery operations according to embodiments of the present invention.
  • FIG. 7A is a block diagram of a memory system, according to embodiments of the present invention.
  • FIG. 7B is a block diagram of a memory system, according to embodiments of the present invention.
  • FIG. 3A illustrates a nonvolatile memory system 30 according to embodiments of the present invention, which includes a memory controller 34 and a nonvolatile memory (e.g., flash memory) device 36 .
  • the memory controller 34 is electrically coupled to the nonvolatile memory device 36 .
  • the memory controller 34 can be configured to provide, among other things, instructions/commands, configuration information and write data to the nonvolatile memory device 36 and receive read data and other information from the memory device 36 .
  • the memory controller 34 is configured to control memory cell recovery operations within the memory device 36 during operations to erase one or more memory blocks therein.
  • the memory controller 34 may also be configured to communicate with a host processor 32 using conventional techniques.
  • the memory cell recovery operations described herein may operate to increase memory device lifetime and reliability by reducing a likelihood that memory cells may become over-erased after experiencing repeated program/erase cycles. In particular, the recovery operations take advantage of the fact that the recovery effect associated with a programmed memory cell is more significant than the recovery effect associated with an erased memory cell.
  • These memory cell recovery operations include the memory cell recovery operations 100 of FIG. 3B .
  • the recovery operations 100 of FIG. 3B include an operation 102 to identify erased memory cells in a nonvolatile memory cell block selected for block erasure (e.g., by a memory controller). Thereafter, an operation 104 is performed to at least partially program the erased memory cells within the block by increasing the threshold voltages of the erased memory cells. This programming operation is performed so that all memory cells in the block are at least partially programmed before any subsequent block erasure operation is performed.
  • This operation 104 to at least partially program the erased memory cells within a block selected for erasure may then be followed by an operation 106 to allocate the selected memory block to a free block list, which indicates that the block is available for erasure (e.g., flash erasure) using conventional or other erasure techniques that may be controlled by the memory controller 34 .
  • erasure e.g., flash erasure
  • operations to allocate a memory block to a free block list may utilize firmware to manage the free block list by classifying memory blocks into a garbage queue first before allocating them to a ready queue.
  • the memory blocks in the garbage queue undergo the recovery operations described herein in advance of being erased an allocated to the ready queue for subsequent use (i.e., programming).
  • memory cell recovery operations 110 include an operation 112 to identify erased memory cells in a selected block of nonvolatile memory cells containing both previously programmed memory cells and at least some unprogrammed (i.e., erased) memory cells. Thereafter, an operation 114 is performed to program the erased memory cells for a predetermined “count” time interval, which may be a fixed or programmable time interval measured by a counter (not shown). This count time interval may correspond to a time interval during which a program word line voltage (e.g., Vpgm) is applied to a selected word line(s) within the selected block.
  • a program word line voltage e.g., Vpgm
  • an operation 118 may be performed to allocate the selected block of memory cells to a free block list, which identifies the block as an available block to be erased (e.g., flash erased) prior to reuse.
  • FIGS. 4B and 4C illustrates a plurality of threshold voltage (Vth) ranges for 2-bit nonvolatile memory cells (e.g., EEPROM cells).
  • These threshold voltage ranges include: E 0 , corresponding to erased memory cells; P 1 , corresponding to memory cells programmed to a first programmed state; P 2 , corresponding to memory cells programmed to a second programmed state; and P 3 , corresponding to memory cells programmed to a third programmed state.
  • E 0 corresponding to erased memory cells
  • P 1 corresponding to memory cells programmed to a first programmed state
  • P 2 corresponding to memory cells programmed to a second programmed state
  • P 3 corresponding to memory cells programmed to a third programmed state.
  • FIG. 4C illustrates a program recovery operation, which includes programming erased memory cells to the first programmed state P 1 .
  • the program recovery operation need not fully program the erased memory cells to the first programmed state P 1 .
  • the count time interval illustrated by Blocks 114 and 116 in FIG. 4A may be sufficient to program an erased memory cell to an undefined state that is higher than the erased state, but less than or intermediate a fully programmed state.
  • the program recovery operation may include programming erased memory cells to program states beyond the first programmed state (e.g., states P 2 , P 3 ).
  • each memory block allocated to a free memory block list should be placed at a bottom of the list so that a maximum amount of time occurs between initial allocation to the list and the ultimate erasure of the listed block and a maximum recovery effect can be achieved.
  • memory cell recovery operations 120 include an operation 122 to program all nonvolatile memory cells within a block selected for erasure for a predetermined time interval.
  • This programming of all nonvolatile memory cells for a predetermined time interval may be treated as a “one-shot” program operation, which may include simultaneously driving a plurality of word lines in the selected memory block at program voltages (Vpgm) while concurrently biasing bit lines associated with columns of memory cells in the block at equivalent bit line voltages that support programming.
  • This time interval may be set by a timer, Block 124 , which specifies a duration sufficient to at least partially program all erased memory cells within the selected block.
  • an operation 126 is performed to allocate the selected block to a free block list.
  • FIG. 5B illustrates the relative threshold voltages of memory cells within a selected block that remain erased (E 0 ) or have been programmed to one of three programmed states (P 1 , P 2 and P 3 ).
  • FIG. 5C illustrates the increased threshold voltages of the memory cells after a one-shot program operation has been performed on all memory cells within the selected block. This one-shot program operation can be performed to reduce the likelihood that erased memory cells within a block may become “over-erased” by virtue of being subjected to repeated erase cycles without undergoing sufficient programming cycles.
  • FIG. 5D illustrates the changes in threshold voltages that occur when a block erase operation is performed to erase all memory cells within a block after the block has been allocated to a free block list.
  • memory cell recovery operations 130 include an operation 132 to erase memory cells within a selected block containing programmed and erased memory cells. Thereafter, a first phase programming operation 134 is performed on all memory cells within the block using a first verify voltage (V 1 ) to confirm that all memory cells have been sufficiently programmed (e.g., to program state P 1 ). Following the first phase programming operation, the threshold voltages of the programmed memory cells are narrowed so that these cells will have more uniform characteristics during repeated program/erase cycles.
  • V 1 first verify voltage
  • a second phase programming operation 136 which may have a relatively short duration, is performed to narrow the variation of threshold voltages of the memory cells within the program state (e.g., program state P 1 ) established by the first phase programming.
  • This second phase programming operation 136 may be performed using a second verify voltage (V 2 ) to verify the narrowing of the threshold voltage variation.
  • An operation 138 to allocate the selected memory block to a free block list is then performed to identify the selected memory block as one that is available for erasure using conventional block erase operations (e.g., flash erase).
  • FIGS. 6B-6E further illustrate the memory cell recovery operations 130 of FIG. 6A . In particular, FIGS.
  • FIG. 6B-6C illustrate operations 132 to erase all memory cells within the selected memory block using a conventional block erase operation (e.g., flash erase).
  • a conventional block erase operation e.g., flash erase
  • FIG. 6D all memory cells within the selected block are programmed to an equivalent program state, using a first verify voltage (e.g., V 1 ) to set a minimum threshold voltage for the programmed cells.
  • this equivalent program state may be the first programmed state (e.g., P 1 ), as illustrated.
  • P 1 the first programmed state
  • FIG. 6E a second phase programming operation is performed to increase the lower-end threshold voltages of the memory cells in the previously established program state.
  • This second phase programming includes using a second verify voltage (e.g., V 2 >V 1 ) to set the minimum program voltage within the narrower range of program voltages, shown as P 1 ′.
  • FIG. 7A is a block diagram of a memory system 200 that may include a nonvolatile memory device according to embodiments of the present invention.
  • This system 200 is illustrated as including a nonvolatile memory system 210 , such as the memory system 30 of FIG. 3A .
  • This nonvolatile memory system 210 includes a memory controller 212 and a flash memory device 211 .
  • the memory controller 212 which may be configured to perform the memory cell recovery operations described herein, is electrically coupled to other components within the memory system 200 . These other components include a central processing unit 230 , volatile memory 240 (e.g., RAM), a user interface 250 and a power supply 220 .
  • FIG. 7B is a block diagram of a memory system 300 that may include a nonvolatile memory device according to embodiments of the present invention.
  • This system 300 is illustrated as including a flash memory system 310 , such as the memory system 30 of FIG. 3A .
  • This flash memory system 310 is illustrated as communicating with an external memory interface system 320 .
  • the interface system 320 is illustrated as including a memory interface circuit 325 , which is electrically coupled to a central bus.
  • Other components connected to this central bus include a central processing unit 322 , a volatile memory device 321 (e.g., SRAM), an error correction circuit 324 (ECC) and a host interface circuit 323 .
  • a volatile memory device 321 e.g., SRAM
  • ECC error correction circuit
US12/498,508 2008-10-10 2009-07-07 Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same Active 2029-10-15 US8274840B2 (en)

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