US7864078B2 - Method and device for decoding a signal - Google Patents

Method and device for decoding a signal Download PDF

Info

Publication number
US7864078B2
US7864078B2 US12/063,392 US6339206A US7864078B2 US 7864078 B2 US7864078 B2 US 7864078B2 US 6339206 A US6339206 A US 6339206A US 7864078 B2 US7864078 B2 US 7864078B2
Authority
US
United States
Prior art keywords
edge
sampling
bit
signal
values
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US12/063,392
Other languages
English (en)
Other versions
US20100219992A1 (en
Inventor
Andreas-Juergen Rohatschek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Assigned to ROBERT BOSCH GMBH reassignment ROBERT BOSCH GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ROHATSCHEK, ANDREAS-JUERGEN
Publication of US20100219992A1 publication Critical patent/US20100219992A1/en
Application granted granted Critical
Publication of US7864078B2 publication Critical patent/US7864078B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit

Definitions

  • the present invention relates to a method for decoding a signal, transmitted via at least one transmission line of a data transmission system, in a user of the data transmission system receiving the signal. Furthermore, the present invention relates to a method for decoding a signal. In addition, the present invention relates to a system for transmitting data. Furthermore, the present invention relates to a user of a data transmission system. Finally, the present invention also relates to a communications controller of a user of a data transmission system.
  • control units sensor systems and actuator systems with the aid of a communications system and a communication connection, for instance in the form of a bus system
  • a communications system and a communication connection for instance in the form of a bus system
  • Synergistic effects can be achieved by distributing functions to a plurality of control units. This is referred to as distributed systems.
  • the communication between various users of such a data transmission system is increasingly being implemented via a bus system.
  • the communication traffic on the bus system, access and receiving mechanisms, as well as error handling are regulated by a protocol.
  • One known protocol is, for instance, the FlexRay protocol, which is currently based on the FlexRay protocol specification v2.1.
  • FlexRay is a fast, deterministic and error-tolerant bus system, especially for use in motor vehicles.
  • the FlexRay protocol operates according to the principle of time division multiple access (TDMA), in which the users or the messages to be transmitted are assigned fixed time slots during which they have exclusive access to the communications link. The time slots repeat at a fixed cycle, so that the instant at which a message is transmitted via the bus can be predicted exactly, and the bus access takes place deterministically.
  • TDMA time division multiple access
  • FlexRay subdivides the cycle into a static and a dynamic portion.
  • the fixed time slots are in the static portion at the beginning of a bus cycle.
  • the time slots are assigned dynamically.
  • the exclusive bus access is always provided for only a short time, for the duration of at least one so-called mini slot.
  • FlexRay communicates via one or two physically separate lines at a data rate of maximally 10 Mbit/sec in each case.
  • the two channels correspond to the physical layer, in particular of the so-called OSI (open system interconnection) layer model. They are used chiefly for the redundant and therefore error-tolerant transmission of messages, but are also able to transmit different messages, whereby the data rate would then double.
  • OSI open system interconnection
  • the signal transmitted via the transmission lines results from the difference of signals transmitted via the two lines.
  • the physical layer is designed such that it allows an electrical but also an optical transmission of the signal(s) via the line(s) or a transmission in some other manner.
  • the users in the communications network require a common time base, which is referred to as global time.
  • global time For the clock synchronization, synchronization messages are transmitted in the static portion of the cycle, and the local clock time of a user is corrected with the aid of a special algorithm according to the FlexRay specification in such a way that all local clocks run in synchronism with a global clock.
  • pulses are distorted because high-to-low or low-to-high edges are delayed to different degrees on the transmission path.
  • the transmitted pulse is sampled repeatedly (for instance, n-times per bit) in the receiver using the sample clock (the so-called sampling rate) available there, then the position of the sampling point, i.e., the selection of precisely one of these n sampling values, decides whether the datum is sampled correctly or incorrectly. This is difficult especially when the sampling instant refers to an edge of the signal and also analyzes a plurality of binary data values (bits) of the transmitter relative thereto, over many periods of the sampling period.
  • the clock frequency deviation between transmitter and receiver also has an effect in this context. It has become apparent that the rigid specification of the sampling instant without considering the asymmetrical delays on the different transmission paths leads to problems.
  • a sampling counter is synchronized, i.e., reset, in response to a falling BSS (byte start sequence) edge. Sampling occurs at a counter reading of 5.
  • decoding errors may actually be detected by suitable error detection algorithms, so that renewed transmission of the bit or the entire data frame may be initiated.
  • a cyclic redundancy check (CRC), for example, may be used as error detection algorithm.
  • CRC cyclic redundancy check
  • the error detection algorithm responds too frequently, there is the disadvantage of reduced availability of the data transmission system.
  • the FlexRay protocol sets down stipulations that the physical layer, at least with complex network topologies, is unable to meet.
  • Example embodiments of the present invention address this contradiction and provide a possibility for transmitting data via the data transmission system at a high transmission rate, with high reliability and high availability of the data transmission system, and the ability of decoding the data in the receiving user.
  • a position for a potential edge change of the signal present at the receiving user be determined without taking asymmetrical delays into account; the applied signal is sampled at least one sampling period in front of the position for a potential edge change, and/or at least one sampling period after the position for a potential edge change; the sampled values of the applied signal are compared to corresponding values that were determined previously and stored, and the value of a bit received between two potential edge changes is determined as a function of the result of the comparison.
  • Example embodiments of the present invention are described by way of example based on a FlexRay data transmission system. However, this should not be understood as a restriction. Example embodiments of the present invention may be used for many different types of data transmission systems and is easily transferable to comparable systems.
  • sampling is implemented early enough in advance of and following a possible edge position.
  • Sampling does not take place at a specific sampling position, but the location of an edge is detected.
  • an edge change may take place at the periodicity of n sampling cycles.
  • the so-called potential edge position denotes the position of a potential edge change without stochastic or systematic influence of an EMC jitter or some other asymmetrical delay. If the decoding is synchronized to a falling edge, for instance to the falling BSS (byte start sequence) edge, the nominal position of the rising potential edge change is affected by asymmetrical delay times. However, the nominal position of the falling potential edge change is not affected by systematic, asymmetrical delay times.
  • sampling range The range in a sequence of successive sampling values in which a check for an actual edge change takes place is known as sampling range or also sensitivity range.
  • the actual edge change is shifted relative to the potential edge position due to asymmetrical delay times and EMC jitter.
  • the sensitivity range of a rising edge lies in an interval between six sampling periods before and six sampling periods after the nominal potential edge position.
  • the sensitivity range of a falling edge lies in the interval between two sampling periods before and two sampling periods after the nominal potential edge position.
  • the indicated numbers for the number of sampling periods before and after the nominal potential edge position are exemplary values only. They may be varied virtually at random for different oversamplings or while specifying and considering specific marginal conditions. Sampling values outside of the sensitivity range are not considered, but may be recorded.
  • An edge acceptance vector is an ordered combination of the 2n sampling values of a potential edge change. For a particular type of edge (rising or falling) there are a plurality of edge acceptance vectors. The bit that is inverse to the last bit (if a rising edge is expected, the current bit is zero and the bit inverse thereto would be one) must be included at least once in each one of the edge acceptance vectors. For this reason, a vector having only zeroes is not allowed for rising edges. The number of required edge acceptance vectors is based on the maximally tolerable asymmetrical delay of the entire causal loop and on the degree of oversampling.
  • a subset is selected from the set of determined edge acceptance vectors, which allows the detection and assignment of a rising edge to its potential edge position in an unambiguous manner.
  • the trend of the asymmetrical delay is advantageously determined by measuring the delay of one or a plurality of changes, either required in the protocol or occurring randomly, of rising and falling edge.
  • the edge acceptance vectors utilized for the evaluation are selected such that they expect an edge change around the determined tendential position. In particular when decoding successive zeroes, the selected subset must ensure that no ambiguity will be possible in the edge detection.
  • edge acceptance vector set For one, the subset encompasses the edge acceptance vector by which an edge change at the expected edge change position is able to be detected.
  • the subset includes a particular number of edge acceptance vectors before this first vector and following this first vector. The number of additional edge acceptance vectors before and after this vector depends on the magnitude of the EMC component in the asymmetrical delay. For instance, if one may assume that the EMC influence on the delay is smaller than two sampling periods, then two additional edge acceptance vectors before and after the first vector will suffice. In this case the edge acceptance vector set would be made up of five edge acceptance vectors.
  • an edge acceptance vector set results accordingly, the sensitivity range and thus the number of sampling values to be taken into account within the edge acceptance vectors being lower than in an expected rising edge.
  • Bits arriving first are sampled first in the method. Prior to the sampling of a bit, the potential following edge is specified based on the detected value of the previously sampled bit, and the correct edge acceptance vector set is determined based on this specification. If the last bit was a one, then the corresponding edge acceptance vector set for falling edges is selected. If the last bit was a zero, then the corresponding edge acceptance vector set for rising edges is selected.
  • the evaluation of the detected sampling values and thus the determination of the corresponding bit value takes place at evaluation instants BEW.
  • the detection of the sampling values and the evaluation may also be restricted to the sampling values of the sensitivity range. It would also be possible to begin with the evaluation already when the limit of the sensitivity range has been reached since the sampling values outside the sensitivity range are not relevant to the evaluation.
  • the memory of the sampling values includes at least one vector that is part of the set of selected edge acceptance vector set, then the associated edge is considered detected and the associated bit value is determined. Otherwise, no edge has been detected, and it is assumed that the instantaneous bit is the same as the predecessor bit.
  • the users of the data transmission system but at least the receiving users, advantageously include two memories, which may be written to in alternation.
  • two memories which may be written to in alternation.
  • one or a plurality of the following marginal conditions may be specified.
  • the filter effect of a majority voting machine must be taken into account.
  • the time discretization error of the sampling must be taken into consideration.
  • the edge acceptance vector that, in addition to the “don't cares” “X”, includes zeros and/or ones exclusively, is used to increase the robustness of the method.
  • edge change and the position of the detected changes in relation to the counter reading may be detected and ascertained also without the use of vectors. Determining the position of an edge change allows a reliable and safe evaluation of the instantaneous bit value.
  • the sensitivity ranges may deviate from the indicated examples. Instead of the eightfold oversampling mentioned here, any other n-fold oversampling may be selected as well.
  • a synchronization to the falling edge a synchronization to a rising edge may be implemented.
  • the number of bits to be sampled after the synchronization edge varies. The evaluation of the sampled values allows the diagnosis of implausible combinations as input bit errors (such as oscillating input bit streams).
  • the majority voting requires a minimum duration of the one or zero phase of three sampling periods. As an alternative, the majority voting could also be reduced to two consecutive edges (rising and falling) of the sampling period, or filtering could be achieved by suitable selection of edge acceptance vectors.
  • FIG. 1 is a transition diagram of bits received in a data transmission system according to an example embodiment of the present invention
  • FIG. 2 illustrates sensitivity ranges for expected rising and falling edges
  • FIG. 3 a illustrates a first example for the configuration of edge acceptance vectors for rising edges
  • FIG. 3 b illustrates a second example for the configuration of edge acceptance vectors for rising edges
  • FIG. 4 a illustrates a subset of the edge acceptance vectors from FIG. 3 a
  • FIG. 4 b illustrates subsets of the edge acceptance vectors from FIG. 3 b;
  • FIG. 5 a illustrates a first example for the configuration of edge acceptance vectors for falling edges
  • FIG. 5 b illustrates a second example for the configuration of edge acceptance vectors for falling edges
  • FIG. 6 illustrates a first example for the realization of the method according to an example embodiment of the present invention for a first exemplary bit sequence
  • FIG. 7 illustrates a second example for the realization of the method according to an example embodiment of the present invention for a second exemplary bit sequence
  • FIG. 8 illustrates a third example for the realization of the method according to an example embodiment of the present invention for a third exemplary bit sequence
  • FIG. 9 illustrates a fourth example for the realization of the method according to an example embodiment of the present invention for a fourth exemplary bit sequence
  • FIG. 10 illustrates a fifth example for the realization of the method according to an example embodiment of the present invention for a fifth exemplary bit sequence
  • FIG. 11 illustrates a first example for the realization of the method according to an example embodiment of the present invention for measuring the delay of rising and falling edge
  • FIG. 12 illustrates a second example for the realization of the method according to an example embodiment of the present invention for measuring the delay of rising and falling edge
  • FIG. 13 is a flow chart illustrating a method of an example embodiment of the present invention.
  • FIG. 14 a illustrates a signal characteristic in the case of a falling and rising edge in a data transmission system
  • FIG. 14 b illustrates characteristics of a signal transmitted by a transmitting user and received by a receiving user
  • FIG. 15 illustrates a conventional functioning method for decoding a signal at the fifth sampling point
  • FIG. 16 illustrates a conventional method for decoding a signal at the fifth sampling point with a decoding error
  • FIG. 17 illustrates one example for a signal chain of a data transmission system with corresponding exemplary values for the resulting asymmetrical delay without the EMC component.
  • the communication between various users of such a data transmission system is increasingly being implemented via a bus system.
  • the communication traffic on the bus system, access and receiving mechanisms, as well as error handling are regulated by a protocol.
  • One known protocol is, for instance, the FlexRay protocol, which is currently based on the FlexRay protocol specification v2.1.
  • FlexRay is a rapid, deterministic and error-tolerant bus system, especially for the use in motor vehicles.
  • the FlexRay protocol operates according to the method of time division multiple access (TDMA), in which the users or the messages to be transmitted are assigned fixed time slots in which they have an exclusive access to the communications link.
  • TDMA time division multiple access
  • the time slots repeat in a fixed cycle, so that the instant at which a message is transmitted via the bus can be predicted exactly, and the bus access takes place deterministically.
  • FlexRay communicates via one or two physically separate lines at a data rate of maximally 10 Mbit/sec in each case.
  • the two channels correspond to the physical layer, in particular of the so-called OSI (open system interconnection) layer model. They are used chiefly for the redundant and therefore error-tolerant transmission of messages, but are also able to transmit different messages, whereby the data rate would then double.
  • OSI open system interconnection
  • the transmitted signal results from the difference of the two signals transmitted via the lines, as differential signal.
  • the signal transmission via the physical layer may be implemented electrically, optically or in any other manner.
  • the users in the communications network need a common time base, which is known as global time.
  • global time For the clock synchronization, synchronization messages are transmitted in the static portion of the cycle, and the local clock time of a user is corrected with the aid of a special algorithm according to the FlexRay specification in such a way that all local clocks run in synchronism with a global clock.
  • FIG. 14 a shows that signals in the region of edge changes from high to low or from low to high have no ideal rectangular characteristic, but a slanted, ramp-like characteristic. It can be seen that the gradient of the falling edge and the rising edge are of different magnitude. This difference causes a difference in the resulting delays for rising and falling edges (cf. FIG. 14 b ). An asymmetrical delay 15 results as a function of the difference in the delays for rising edges 13 and falling edges 14 .
  • the characteristic of emitted signal 10 is shown on top, and the characteristic of received signal 10 is shown at the bottom. Delays 13 , 14 concern the difference in the corresponding edges between emitted signal TxD and received signal RxD.
  • pulses are distorted because high-to-low or low-to-high edges are delayed to different degrees on the transmission path.
  • the transmitted pulse is sampled repeatedly in the receiver (for instance, eight times per bit) using the sampling period cycle (the so-called sampling rate) available there, then the position of the sampling point, i.e., the selection of precisely one of these eight sampling values, decides whether the datum is sampled correctly or incorrectly. This will be elucidated in greater detail in the following text based on FIGS. 15 and 16 .
  • a signal to be decoded is denoted by reference numeral 10 .
  • the decoding is synchronized to the falling BSS (byte start sequence) edge.
  • BSS byte start sequence
  • a sampling counter begins running and is reset whenever counter reading 8 is reached.
  • the signal is sampled at the fifth sampling point in each case.
  • the rigid specification of the sampling instant without consideration of the asymmetrical delays on different transmission paths, causes problems.
  • the pending edge change should actually take place precisely at counter reading 8 between FES “0” and FES “1”.
  • the asymmetrical delays it is shifted in the advance direction in FIG. 15 , to such an extent that the edge change occurs precisely between the fifth and sixth sampling value. This is non-critical in this example insofar as the sampling instant still lies before the edge change, and the bit (0) preceding the edge change is able to be decoded correctly.
  • the sampling counter is synchronized, i.e., reset, with a falling BSS (byte start sequence) edge. Sampling occurs at a counter reading of 5.
  • the data transmission path includes a transmitting user 14 having a communications controller (CC) 16 , a printed circuit board having circuit traces and components (PCB) 18 , and a transmitter.
  • the transmitter includes a bus driver (BD) 20 and a termination element (common mode choke CMC) 22 .
  • BD bus driver
  • CMC common mode choke
  • first star node 26 is in connection with a second active star node 30 , which likewise includes two bus drivers.
  • star node 30 Via a second passive network 34 , star node 30 is connected to a receiving user 36 , having a communications controller (CC) 38 , a printed circuit board (PCB) 40 , and a receiver.
  • the receiver includes a termination element (CMC) 42 , and a bus driver (BD) 44 .
  • the corresponding estimated, modeled and/or calculated time data for the asymmetrical delay are indicated for the various components and must be added up to determine the entire asymmetrical delay.
  • an asymmetrical delay of approximately 72 ns results. This is above the previously determined time budget of approx. 37.5 ns.
  • the conventional decoding method can no longer function properly at certain instants in the network topology from FIG. 17 when maintaining the desired high data rate of approximately 10 Mbit/sec.
  • the FlexRay protocol makes demands that the physical layer, at least in the case of complex network topologies, is unable to satisfy.
  • Example embodiments of the present invention are able to remedy this.
  • a decoding method in which a signal is not sampled at a specific instant (such as when the sampling counter reads 5 ).
  • a first step an estimation is performed as to where a possible edge position of the signal to be decoded might be located.
  • the interval between at least one mandatory sequence of rising and falling edges prescribed in the protocol, or a random sequence of rising and falling edges is measured with the aid of a counter, and the systematic component of the asymmetrical delay is determined therefrom.
  • sampling takes place sufficiently before and sufficiently after the possible edge position.
  • the sampled values are compared with previously recorded sampling values, and the corresponding bit value is determined on the basis of the comparison.
  • One set of a plurality of sampling values was recorded and stored for a position of an edge change in each case. That is to say, when the sampled values agree with a specific stored set of sampling values, then it is assumed that the edge change has occurred at the position that corresponds to the set of sampling values.
  • the use of the method of example embodiments of the present invention makes it possible to take the characteristics of the transmission channel into account. It is especially robust with regard to asymmetrical delays.
  • a 0 must be followed by a 0 or a 1.
  • a 1 is followed by a 1 or a 0.
  • a rising edge may follow only after a 0.
  • a falling edge may follow only after a 1. It is impossible for a rising edge to follow a 1, or for a falling edge to follow a 0.
  • the decoding method is elucidated in greater detail in the following text with the aid of FIG. 6 .
  • FlexRay protocol specification 2.1 the synchronization takes place to the falling BSS edge.
  • a first counter A is set to 1
  • a second counter B is set to 9.
  • the method may also be realized by one counter only.
  • counter A is actually set to 2 and counter B to 10 since one period is lost to signal processing, but, viewed macroscopically from outside, counters A, B are initialized to 1 and 9, respectively.
  • an edge change may take place but is not mandatory (cf. FIG. 1 and associated description).
  • PEP potential edge position
  • the edge changes always occur precisely at the PEPs, in particular PEP 1 - 2 , PEP 3 - 4 , PEP 4 - 5 , and PEP 5 - 6 . Because of asymmetrical delay times, as a result of the synchronization to the falling (and not to the rising) BSS edge, the nominal position of the rising potential edge change is influenced.
  • the rising edge changes are shifted to advance or to delay relative to the PEPs.
  • the falling edge changes are shifted to a clearly lesser degree since they are affected only by the EMC component of the asymmetrical delay. That is to say, with the exception of stochastic influences, discernible as EMC jitter, the asymmetrical delay times have only a negligible effect on the actual position of the falling potential edge changes.
  • a potential edge change is sampled maximally 8 sampling cycles prior to and maximally 8 sampling cycles following the nominal position. This is denoted as a sequence of sampling values.
  • the sampling may also involve fewer than eight sampling cycles prior to and/or following the nominal position of a potential edge change.
  • Sensitivity range 50 for a rising edge lies in an interval between six sampling periods before and six sampling periods after the nominal PEP.
  • Sensitivity range 52 of a falling edge lies in the interval between two sampling periods before and two sampling periods after the nominal PEP.
  • both sensitivity range 50 , 52 for a rising edge and that for a falling edge could also include an interval having more or fewer sampling periods than indicated prior to and/or following the nominal PEP. Sampling values outside of sensitivity range 50 , 52 are not considered.
  • FIGS. 3 a and 3 b illustrate different EAVs one underneath the other for rising edges by way of example, the left occurring first chronologically.
  • the bit (‘1’) inverse relative to the preceding bit (‘0’) must be included at least once in an EAV. As a result, an EAV consisting exclusively of zeroes is not allowed.
  • the ‘X’ at the beginning and the end of the EAVs result from the fact that sampling values outside of the sensitivity range are unimportant for the evaluation.
  • a subset is selected from the EAVs, shown in FIGS. 3 a and 3 b , respectively, for the detection of a rising edge, which allows the detection and assignment of a rising edge to its PEP in an unambiguous manner.
  • the EAVs utilized for the evaluation are selected such that they expect an edge change around the determined tendential position.
  • the selected subset must ensure that there will be no potential ambiguity in the edge detection. There would be ambiguity if a detected rising edge could be shifted both from the PEP(i) to retard and from the PEP(i+1) to advance, and two EAVs would apply (one at BEW(i) and one at BEW(i+1)).
  • FSS frame start sequence
  • BSS BSS
  • FIGS. 4 a and 4 b such subsets of the EAVs from FIGS. 3 a and 3 b are shown by way of example.
  • An edge change from ‘0’ to ‘1’ at position 4 before PEP is detected by the third EAV from the subset of EAVs in FIG. 3 a .
  • this EAV is definitely part of the selected subset.
  • a particular number of EAVs before the third EAV and a specific number of EAVs after the third EAV is incorporated in the subset.
  • the set of edge-acceptance vectors for rising edges includes a total of five EAVs.
  • the present invention is not limited to this number of EAVs as set of edge-acceptance vectors.
  • the EMC influence on the asymmetrical delay must thus not be greater than two sampling periods, i.e., approximately 25 ns.
  • the vectors of the subsets selected as a function of m selected vectors of the subsets are marked by an asterisk “*” in FIG. 4 b.
  • FIGS. 5 a and 5 b show EAVs for falling edges by way of example, the left being first chronologically. Since the sensitivity range includes only two sampling periods before and two sampling periods after the nominal PEP and all other measuring values are unimportant for the evaluation, only four EAVs result in this example.
  • the bit (‘0’) inverse relative to the preceding bit (‘1’) must be included at least once in an EAV. A vector consisting exclusively of ones is therefore not allowed.
  • FIG. 13 shows a flow chart of the method according to an example embodiment of the present invention. Bits arriving first are sampled first within the scope of the sampling or decoding. The method begins in a functional block 60 . Prior to sampling a bit, the potential following edge (cf. FIG. 1 ) is specified on the basis of the detected value of the previously sampled bit (i). For this purpose, a query block 62 is provided, from which branching to a functional block 64 takes place in the case of an expected rising edge, and to a functional block 66 in the case of a falling edge. If the last bit was a ‘0’, then the applicable edge acceptance vector set according to FIG. 4 (or FIG. 3 ) is to be selected.
  • FIG. 4 or FIG. 3
  • the applicable edge acceptance vector set according to FIG. 5 is to be selected. Due to this specification, the corresponding edge acceptance vector set is determined. As obvious modification, in reversing this sequence, it is also possible to first detect an edge and then to determine the following bit value based on knowledge of the preceding data bit value.
  • an evaluation takes place at instant BEW in a functional block 68 or 70 .
  • the value of bit # 2 is determined at instant BEW 2 .
  • the evaluation may be implemented even before reaching the limit of sensitivity range 50 , 52 , since the evaluation of the “X” is not relevant. If it is determined within the framework of the evaluation that one of the stored EAVs that is part of the set of the selected edge acceptance vector set, then the associated edge is considered detected and the associated bit value is determined (cf. functional block 72 and 74 ). Otherwise no edge is detected, and the instantaneous bit is the same as the preceding bit (cf.
  • FIG. 7 shows a simple variant of an example embodiment of the present invention.
  • Sensitivity range 54 for expected rising edges includes not 12 but even 13 sampling values. This makes it possible to detect a rising edge change even at position 2 in front of PEP 2 - 3 , which would no longer be possible with a sensitivity range 50 from FIG. 6 .
  • the expansion of sensitivity range 54 by one sampling value is possible despite overlapping sensitivity ranges 52 , 54 , without endangering the unambiguity of the detection.
  • FIG. 8 An additional exemplary embodiment is described in FIG. 8 .
  • the signal “TxD data signal” ( 812 ) transmitted by a transmitting user ( 14 ) corresponds to signal “RxD data signal” ( 813 ) arriving at receiving user ( 36 ).
  • the asymmetrical delay times are generally shown in the examples; delays in topology run-through are disregarded in the figure since they are not relevant. For that reason, the edges of signal characteristics 812 and 812 are exactly superposed. Potential-edge positions PEP are to be understood according to the explanations regarding FIG. 6 .
  • Received data signal 813 is sampled periodically at sampling points 816 .
  • the description begins with resynchronization 802 of sampling counter 801 .
  • a suitable subset of the rising edge-acceptance vectors 803 has already been selected.
  • the edge-acceptance vectors in this exemplary embodiment have a different characteristic than those from FIGS. 3 a , 4 a , and 5 a .
  • the edge-acceptance vectors utilized here are shown in FIGS. 3 b , 4 b , and 5 b .
  • the rule is basically satisfied that vectors for detecting rising edges must have at least one “1”, and vectors for detecting falling edges must have at least one “0”.
  • Sampling counter 801 is incremented until it reaches 16. 16 is followed by 1 again, etc.
  • Each edge-acceptance vector has an identification, such as “VR 01 ” through “VR 15 ” etc.
  • the comparison of each vector of the selected subset to the content of input register RegA ( 804 ) has the result that vector “VR 08 ” corresponds to the content of RegA ( 804 ). This means that a rising edge was detected and that the value of the decoded data bit 1 is therefore a “1”.
  • Eight sampling periods later, the other result register RegB ( 807 ) is full, and the decision algorithm is implemented for evaluation point BEW 2 ( 806 ).
  • evaluation point BEW 3 ( 808 ) leads to the same sequence; the result for data bit 3 is “1” in this case as well.
  • evaluation point BEW 4 ( 809 ) a falling edge is detected since the content of input register RegB ( 807 ) corresponds to falling edge-acceptance vector VF 04 .
  • the decision algorithm For the decoding of eight successive data bits, as provided in FlexRay protocol version v2.1, the decision algorithm must be executed eight times. This is carried out in evaluation points BEW 1 ( 805 ) through BEW 8 ( 810 ).
  • BEW 9 ( 811 ) may be used for plausibility checks.
  • the BSS detection is activated ( 814 ). This may be carried out, for example, by methods published in the FlexRay specification version 2.1 and functioning accordingly.
  • FIG. 11 One advantageous development of the selection of a suitable subset by measuring successive rising and falling edges is described in FIG. 11 .
  • the interval of the falling BSS edge relative to the last preceding rising edge is measured for each synchronization point BSS ( 1102 ).
  • Prior to BSS 1, precisely w data bits are identical to “1”.
  • the subset of the vectors is selected for instance according to FIG. 4 b as a function of m.
  • each rising edge is shifted to “advance” by three sampling periods relative to the falling BSS edge by systematic, asymmetrical delay times.
  • An additional stochastic jitter by one sampling period leads to received signal “RxD data signal” ( 1201 ).
  • the measuring counter is started (that is to say, begins to increment from 1) at the first rising edge after the BSS edge ( 1202 ).
  • the measuring counter is incremented in each sampling period until a falling edge is detected.
  • the state of the measuring counter remains undefined (logically “X”) until the next rising edge occurs.
  • the measurement is started at counter reading “1” at the next rising edge ( 1202 ).
  • FIG. 9 shows a decoding example having a maximum asymmetry to “advance”
  • FIG. 10 shows a maximum asymmetry to “delay”.
  • stochastic asymmetry 902 is additionally acting on each edge.
  • vectors “VRrec” and “VFrec” allow the decoder to resume correct operation following short-duration incorrect decoding. Although this does not allow errors to be avoided or corrected, it is nevertheless ensured that the Hamming distance, which is decisive for error detection, will not be exceeded.
  • the vectors “VRrec” and “VFrec” also may show less significant “1” or “0” than shown in the example.
  • a communications controller advantageously includes two memories, preferably two 16 bit memories, which are written to in alternation.
  • the storing is triggered by the two counters A and B with value range 16 , which are incremented at each sampling cycle (sampling period).
  • a memory is written to by the first sampling bit of the potential edge change sampling if the associated counter A, B is at ‘1’, etc.
  • smaller memories that allow comparisons in short segments including at least one bit are possible as well.
  • the method of example embodiments of the present invention may be simplified and accelerated by the definition of and compliance with marginal conditions.
  • the sum of the sample clocks must not exceed 16 for two successive sensitivity ranges (given eightfold oversampling).
  • the filter effect of the majority voting machine must be taken into account.
  • the time discretization error of the sampling is to be taken into account.
  • the EAV that includes exclusively ‘0’ or ‘1’ in the sensitivity range is used to compensate for the time-discretization error.
  • at least the following asymmetrical overall delays are allowed when exhausting all EAVs:
  • the edge changes may also be detected in some other manner, the position of the detected changes being ascertained with reference to the counter reading of counters A, B.
  • the position allows the evaluation of the instantaneous bit value.
  • the magnitudes of sensitivity ranges 50, 52, 54 are variable. Instead of an eightfold oversampling, some other n-fold oversampling may be selected. Instead of a synchronization to the falling edge, it may also be synchronized to the rising edge. The number of bits to be sampled after the synchronization edge may be varied.
  • evaluation of the sampled values allows the diagnosis of implausible combinations as input bit errors (such as oscillating input bit streams).
  • Evaluation instant BEW need not necessarily occur after 16 monitored sampling values, but following the end of the sensitivity of the evaluation since the evaluation of the sampling values outside the sensitivity range is irrelevant.
  • Majority voting requires a minimum duration of the 1 or 0 phase of two sampling period durations. As an alternative, the majority voting may also be reduced to two consecutive edges (rising and falling) of the sampling period, or a filter effect may be achieved as well by suitable selection of the edge-acceptance vectors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
US12/063,392 2005-08-08 2006-08-07 Method and device for decoding a signal Expired - Fee Related US7864078B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102005037263.5 2005-08-08
DE102005037263 2005-08-08
DE102005037263A DE102005037263A1 (de) 2005-08-08 2005-08-08 Verfahren und Vorrichtung zum Decodieren eines Signals
PCT/EP2006/065111 WO2007017491A1 (de) 2005-08-08 2006-08-07 Verfahren und vorrichtung zum dekodieren eines signals

Publications (2)

Publication Number Publication Date
US20100219992A1 US20100219992A1 (en) 2010-09-02
US7864078B2 true US7864078B2 (en) 2011-01-04

Family

ID=37156012

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/063,392 Expired - Fee Related US7864078B2 (en) 2005-08-08 2006-08-07 Method and device for decoding a signal

Country Status (7)

Country Link
US (1) US7864078B2 (ja)
EP (1) EP1915833B1 (ja)
JP (1) JP4873663B2 (ja)
KR (1) KR101023930B1 (ja)
CN (1) CN101243638B (ja)
DE (1) DE102005037263A1 (ja)
WO (1) WO2007017491A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100008456A1 (en) * 2006-03-08 2010-01-14 Andreas-Juergen Rohatschek Method And System For Compensating Asymmetrical Delays
US20100046594A1 (en) * 2005-04-27 2010-02-25 Florian Hartwich Method and device for decoding a signal
US20160164701A1 (en) * 2014-12-04 2016-06-09 Stmicroelectronics (Rousset) Sas Transmission and Reception Methods for a Binary Signal on a Serial Link

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005037263A1 (de) 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zum Decodieren eines Signals
DE102009001397A1 (de) * 2009-03-09 2010-09-16 Robert Bosch Gmbh Verfahren sowie Vorrichtung zur Diagnose eines Kommunikationssystems hinsichtlich asymmetrischer Verzögerung
KR101743294B1 (ko) * 2010-11-01 2017-06-15 두산인프라코어 주식회사 건설장비의 모니터링 데이터 샘플링 방법
JP5907499B2 (ja) * 2011-05-11 2016-04-26 矢崎総業株式会社 中継装置およびコネクタ
DE102012103194B4 (de) 2012-04-13 2014-09-11 Pilz Gmbh & Co. Kg Verfahren zum Übertragen von Prozessdaten in einer automatisiert gesteuerten Anlage
CN105959143B (zh) * 2016-05-18 2019-05-24 中国电子科技集团公司第四十一研究所 一种基于数字荧光示波器的FlexRay总线协议分析系统及方法
DE102017214421A1 (de) * 2017-08-18 2019-02-21 Robert Bosch Gmbh Verfahren und Vorrichtung zur Synchronisation von Prozessen auf wenigstens zwei Prozessoren
CN111913829B (zh) * 2019-05-10 2024-05-17 深圳大心电子科技有限公司 数据读取方法、存储控制器与存储装置
CN110208822B (zh) * 2019-05-28 2021-06-11 西安空间无线电技术研究所 一种基于低轨移动通信卫星的通信方法
CN113541852B (zh) * 2020-03-31 2022-06-10 华为技术有限公司 信号解码方法、解码电路及手写笔

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3417358A1 (de) 1984-05-10 1985-11-14 Siemens AG, 1000 Berlin und 8000 München Einrichtung zur software-korrelation
EP0562183A1 (en) 1992-03-27 1993-09-29 ALCATEL BELL Naamloze Vennootschap Synchronization method and device realizing said method
DE4304913A1 (de) 1993-02-18 1994-08-25 Sel Alcatel Ag Verfahren und Vorrichtung zur Synchronisation einer Teilnehmerstation eines Netzwerkes
US5412698A (en) 1993-03-16 1995-05-02 Apple Computer, Inc. Adaptive data separator
US5684838A (en) * 1994-10-12 1997-11-04 Nippondenso Co., Ltd. Receiving device for sampling data bits at a preferred time
EP1335520A1 (en) 2002-02-11 2003-08-13 AMI Semiconductor Belgium BVBA Multiplex bus system with duty cycle correction
US6653968B1 (en) * 1999-08-06 2003-11-25 Robert Bosch Gmbh System for generating a signal to superimpose information
US7106793B2 (en) * 2000-09-27 2006-09-12 Robert Bosch Gmbh Method, device, and interface for transmitting data
US7233618B2 (en) * 2002-04-25 2007-06-19 Infineon Technologies Ag Circuit configuration and method for transmitting digital signals
US7639765B2 (en) * 2005-09-26 2009-12-29 Panasonic Corporation Single-line bidirectional communication apparatus and system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08107408A (ja) * 1994-10-04 1996-04-23 Fuji Electric Co Ltd フレーム同期式伝送データの解読方法
JPH11163951A (ja) * 1997-11-28 1999-06-18 Sony Corp データ受信装置
JP2000031951A (ja) * 1998-07-15 2000-01-28 Fujitsu Ltd バースト同期回路
DE102005037263A1 (de) 2005-08-08 2007-02-15 Robert Bosch Gmbh Verfahren und Vorrichtung zum Decodieren eines Signals

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3417358A1 (de) 1984-05-10 1985-11-14 Siemens AG, 1000 Berlin und 8000 München Einrichtung zur software-korrelation
EP0562183A1 (en) 1992-03-27 1993-09-29 ALCATEL BELL Naamloze Vennootschap Synchronization method and device realizing said method
DE4304913A1 (de) 1993-02-18 1994-08-25 Sel Alcatel Ag Verfahren und Vorrichtung zur Synchronisation einer Teilnehmerstation eines Netzwerkes
US5412698A (en) 1993-03-16 1995-05-02 Apple Computer, Inc. Adaptive data separator
US5684838A (en) * 1994-10-12 1997-11-04 Nippondenso Co., Ltd. Receiving device for sampling data bits at a preferred time
US6653968B1 (en) * 1999-08-06 2003-11-25 Robert Bosch Gmbh System for generating a signal to superimpose information
US7106793B2 (en) * 2000-09-27 2006-09-12 Robert Bosch Gmbh Method, device, and interface for transmitting data
EP1335520A1 (en) 2002-02-11 2003-08-13 AMI Semiconductor Belgium BVBA Multiplex bus system with duty cycle correction
US7233618B2 (en) * 2002-04-25 2007-06-19 Infineon Technologies Ag Circuit configuration and method for transmitting digital signals
US7639765B2 (en) * 2005-09-26 2009-12-29 Panasonic Corporation Single-line bidirectional communication apparatus and system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
International Search Report, PCT International Patent Application No. PCT/EP2006/065111, dated Nov. 14, 2006.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100046594A1 (en) * 2005-04-27 2010-02-25 Florian Hartwich Method and device for decoding a signal
US8320437B2 (en) * 2005-04-27 2012-11-27 Robert Bosch Gmbh Method and device for decoding a signal
US20100008456A1 (en) * 2006-03-08 2010-01-14 Andreas-Juergen Rohatschek Method And System For Compensating Asymmetrical Delays
US8331390B2 (en) * 2006-03-08 2012-12-11 Robert Bosch Gmbh Method and system for compensating asymmetrical delays
US20160164701A1 (en) * 2014-12-04 2016-06-09 Stmicroelectronics (Rousset) Sas Transmission and Reception Methods for a Binary Signal on a Serial Link
US10122552B2 (en) * 2014-12-04 2018-11-06 Stmicroelectronics (Rousset) Sas Transmission and reception methods for a binary signal on a serial link
US10361890B2 (en) * 2014-12-04 2019-07-23 Stmicroelectronics (Rousset) Sas Transmission and reception methods for a binary signal on a serial link
US10616006B2 (en) * 2014-12-04 2020-04-07 Stmicroelectronics (Rousset) Sas Transmission and reception methods for a binary signal on a serial link

Also Published As

Publication number Publication date
JP4873663B2 (ja) 2012-02-08
KR20080041645A (ko) 2008-05-13
WO2007017491A1 (de) 2007-02-15
EP1915833A1 (de) 2008-04-30
KR101023930B1 (ko) 2011-03-28
US20100219992A1 (en) 2010-09-02
JP2009505464A (ja) 2009-02-05
CN101243638A (zh) 2008-08-13
CN101243638B (zh) 2012-07-04
DE102005037263A1 (de) 2007-02-15
EP1915833B1 (de) 2012-05-23

Similar Documents

Publication Publication Date Title
US7864078B2 (en) Method and device for decoding a signal
US8331390B2 (en) Method and system for compensating asymmetrical delays
US8179787B2 (en) Fault tolerant network utilizing bi-directional point-to-point communications links between nodes
US5903613A (en) Data reception device, data reception method and electronic equipment
US6212161B1 (en) Method and apparatus for a fault tolerant software transparent and high data integrity extension to a backplane bus or interconnect
US8897319B2 (en) High speed embedded protocol for distributed control systems
CN106464559B (zh) 用于分布式控制系统的高速嵌入式协议
US8320437B2 (en) Method and device for decoding a signal
EP3371935B1 (en) Confirming data accuracy in a distributed control system
US8180940B2 (en) Method and system for transmission of cyclic and acyclic data over a transmission channel that takes into account real-time capability
US20090327549A1 (en) Monitoring unit for monitoring or controlling user access to a data bus and user having such a monitoring unit
US20100229046A1 (en) Bus Guardian of a User of a Communication System, and a User of a Communication System
Berwanger et al. FlexRay–the communication system for advanced automotive control systems
JPH02247709A (ja) スキユー除去方法
Rufino et al. A Columbus' egg idea for CAN media redundancy
CN110177034B (zh) 总线系统的订户站和提高总线系统的数据传输率的方法
JP3520388B2 (ja) データ受信装置、データ受信方法及び電子機器
JP2001527239A (ja) ディジタルデータを直列伝送するための通信インタフェースおよびデータ伝送方法
WO2019234414A1 (en) A serial communication system
JP3637014B2 (ja) クロック同期はずれ検出回路及びそれを用いた光受信装置
CN113342728A (zh) 可去时钟线高速并行总线同步逻辑设计
Gerke et al. Model checking the flexray physical layer protocol
US5148450A (en) Digital phase-locked loop
US20240053459A1 (en) Modified uart interface and uart data transmission for real-time data transmission of echo data to a higher-level computer system
Cena et al. Protocols and Services in Controller Area Networks

Legal Events

Date Code Title Description
AS Assignment

Owner name: ROBERT BOSCH GMBH, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROHATSCHEK, ANDREAS-JUERGEN;REEL/FRAME:024190/0648

Effective date: 20080331

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20190104