US7830740B2 - Semiconductor memory device having selectable transfer modes - Google Patents

Semiconductor memory device having selectable transfer modes Download PDF

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Publication number
US7830740B2
US7830740B2 US12/014,990 US1499008A US7830740B2 US 7830740 B2 US7830740 B2 US 7830740B2 US 1499008 A US1499008 A US 1499008A US 7830740 B2 US7830740 B2 US 7830740B2
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data
address
transfer mode
pin
input
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US20080186796A1 (en
Inventor
Susumu Takano
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Renesas Electronics Corp
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NEC Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Definitions

  • the present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a terminal combining an input terminal for address and an input/output terminal for data.
  • a semiconductor device is mounted to a cellular phone or the like.
  • data is transferred between a semiconductor memory device (hereinafter referred to as a memory) and other functional circuits such as CPU (Central Processing Unit).
  • CPU Central Processing Unit
  • the data transfer efficiency is desired to improve.
  • One of the methods for the improvement in data transfer efficiency is to increase the number of buses connecting between the memory and CPU etc. This method increases the amount of data that can be transferred in one access by increasing the number of buses.
  • a package of a semiconductor device is desired to be miniaturized.
  • An increase in the number of buses increases the number of pins formed in a memory. The increase in the number of pins is detrimental to the miniaturization of a memory.
  • Japanese Unexamined Patent Application Publication No. 11-328971 discloses to use the same pins for inputting/outputting a data signal and inputting an address signal.
  • Choi discloses to input/output data through a pin for inputting addresses by inputting a particular control signal.
  • the technique only discloses that a memory disclosed by Choi inputs/outputs data through a pin for address. Control of addresses for inputting and input of command to the memory are not taken into consideration for the memory disclosed by Choi.
  • Choi only discloses to switch an input of an address pin for an asynchronous memory.
  • the present inventor has recognized that in the semiconductor memory device disclosed by Choi, if sharing a pin used for data input/output with an address pin, addresses and commands cannot be input through the address pin, thereby reducing the data transfer efficiency.
  • a semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/output with data in a second transfer mode and a switching circuit to switch a connection destination of the address pin according to the transfer mode.
  • This configuration enables a semiconductor memory device which inputs various commands to support mass transfer.
  • the semiconductor memory device improves data transfer efficiency, keeps the number of pins to the minimum and miniaturizes the semiconductor memory device.
  • FIG. 1 is a block diagram showing a memory according to the present invention
  • FIG. 2 shows a detailed pin configuration of a mass transfer mode
  • FIG. 3 shows commands that can be used in the mass transfer mode
  • FIG. 4 is a timing chart showing an access to a memory in the mass transfer mode
  • FIG. 5 shows a detailed pin configuration of a random transfer mode
  • FIG. 6 shows commands that can be used in the random transfer mode
  • FIG. 7 is a timing chart showing an access to a memory in the random transfer mode.
  • FIG. 8 compares the number of pins in a memory of a related art and the present invention.
  • a semiconductor memory device (hereinafter referred to as a memory) of this embodiment has at least two operational modes.
  • One of the operational modes (first transfer mode) supports sequential transfers in which a large amount of continuous data is input/output at once.
  • the other mode (second transfer mode) is a random transfer operational mode in which a small amount of discrete data is input/output at random.
  • the memory of this embodiment uses pins for inputting addresses as data input/output pins in the mode for transferring a large amount of data and operates in ⁇ 32 mode. In the operational mode for transferring data at random, only data input/output pins are used and operates in ⁇ 16 mode.
  • a memory 1 of the SDRAM according to this embodiment includes a switching circuit (Add/IO and CMD/IO switching circuit) 2 , an address buffer 3 , an input/output buffer 4 , a memory array 5 , a control circuit 6 , a mode setting circuit (Mode Register Set: hereinafter referred to as a MRS control circuit) 7 , a data control unit 8 , a clock control unit 9 , a standby control unit 10 , an address latch circuit 11 , a row decoder 12 , a column decoder 13 and a sense amplifier 14 and a latch circuit 15 .
  • the switching circuit 2 is a circuit for switching a connection destination of pins for address input according to an output of the mode setting circuit 7 .
  • the switching circuit switches the case when an address pin is connected with the address buffer 3 and the case when an address pin is connected with a memory cell through the input/output buffer.
  • the address buffer 3 outputs an address signal provided through the switching circuit 2 and the control circuit 6 when an address is input to the address pin.
  • the input/output buffer 4 is a buffer circuit for inputting/outputting data with outside the memory.
  • the memory array 5 has a plurality of memory cells arranged in a matrix to store data.
  • the control circuit 6 controls operation of the memory of this embodiment according to a command input through the switching circuit 2 .
  • the control circuit 6 lets the MRS circuit 7 hold that it is a mass transfer when a command indicating of mass transfer is provided and also lets the MRS circuit 7 hold that it is a random transfer when a command indicating of random transfer is provided.
  • the MRS circuit 7 is a register for holding the operational mode of the memory and outputs a signal which controls operation of the memory according to the operational mode held there.
  • the data control unit 8 is a circuit for selecting whether to output data in 32 bits output of ⁇ 32 mode or 16 bits output of ⁇ 16 mode.
  • the clock control unit 9 outputs a control signal that synchronizes with a clock signal which is input externally to operate the memory.
  • the standby control unit 10 stops operation of the memory when the memory is in standby status to be in a standby mode.
  • the address latch circuit 11 temporarily holds an address signal output by the address buffer 3 .
  • the row decoder 12 decodes a row address from the address signal held in the address latch circuit 11 and selects any row of the memory array.
  • the column decoder 13 decodes the address signal held in the address latch circuit and selects any column of the memory array.
  • the sense amplifier 14 amplifies a value read from a memory cell in the memory array 5 .
  • the latch circuit 15 temporarily holds read-out data or write-in data.
  • the memory 1 of this embodiment includes several kinds of pins.
  • these pins correspond to a plurality of address pins ADQ 1 to ADQ 16 in which address data or a data signal is input/output according to the operational mode of the memory, a plurality of data pins DQ 1 to DQ 16 in which data is input/output, a mode specification pin CMD_E in which a mode specification signal is input and a command pin CMD for inputting various commands to the memory.
  • These pins are connected to the switching circuit 2 in the memory 1 .
  • the memory 1 of this embodiment has the mode for transferring a large amount of data (hereinafter referred to as a mass transfer mode) and the mode to transfer a small amount data at random (hereinafter referred to as a random transfer mode).
  • a mass transfer mode the mode for transferring a large amount of data
  • a random transfer mode the mode to transfer a small amount data at random
  • a command indicating of the mass transfer mode is input externally to the memory 1 through the command pin CMD.
  • the command indicating of the mass transfer mode is input to the control circuit 2 through the switching circuit 2 .
  • the control circuit 6 lets the MRS circuit 7 hold that is the mass transfer mode according to the transfer mode indicated by the provided command.
  • the MRS circuit 7 outputs a signal indicating of the mass transfer mode to the data control unit 8 and the switching circuit 2 if set to the mass transfer mode.
  • the data control unit 8 is set to ⁇ 32 mode and inputs/outputs data which is input/output from/to the memory to/from the latch circuit 15 in ⁇ 32 mode.
  • the switching circuit 2 treats the address pins ADQ 1 to ADQ 16 as data pins when receiving a signal indicating of the mass transfer mode. That is, a signal input and output to the address pins ADQ 1 to ADQ 16 is exchanged through the input/output buffer 4 , the latch circuit 15 and the data control unit 8 , as with the signal input to the data pins DQ 1 to DQ 16 .
  • a command indicating of the random transfer mode is input externally to the memory 1 through the command pin CMD.
  • the signal indicating of the random transfer mode is input to the control circuit 6 through the switching circuit 2 .
  • the control circuit 6 lets the MRS circuit 7 hold that it is the random transfer mode according to the signal provided.
  • the MRS circuit 7 outputs a signal indicating of the random transfer mode to the data control unit 8 and the switching circuit 2 if set to the random transfer mode.
  • the data control unit 8 is set to ⁇ 16 mode and inputs/outputs data which is input/output from/to the memory to/from the latch circuit 15 in ⁇ 16 mode.
  • the switching circuit 2 When receiving the signal indicating of the random transfer mode, the switching circuit 2 inputs the signal provided to the address pins ADQ 1 to ADQ 16 into the address buffer 3 as data indicating an address of the memory. In the random transfer mode, the memory 1 accesses a memory cell according to an address through the address buffer 3 and the address latch circuit 11 .
  • the pin configuration at the time of the mass data transfer mode is shown in FIG. 2 .
  • the abovementioned pins operating as address pins and data pins are indicated as ADQ[ 00 ] to ADQ[ 23 ] and the data pins are indicated as DQ[ 24 ] to DQ[ 30 ].
  • the mode specification pin CMD_E which supports the transfer mode is equivalent to a command enable CMD_E.
  • FIG. 2 The example shown in FIG.
  • FIG. 2 illustrates a data mask pin B which inputs a signal for masking input/output data in accordance with the actual operation of the memory 1 , a data strobe pin DQS which inputs a signal for adjusting an input/output timing of data, a clock signal input pin CLK and #CLK, a pin CDQ operating for command input and data input/output of a SDRAM and a chip enable pin CE.
  • the number of necessary pins is; 22 address pins, 32 data pins, 1 clock pin and 9 command pins.
  • the memory device of a related art requires at least 32 data pins to output in ⁇ 32 mode.
  • the 512M ⁇ 32 bit memory device requires at least 64 pins.
  • the switching circuit 2 switches input/output of the address pin to data input/output. Therefore, with 32 pins combining the address pins and data pins, it is possible to output in ⁇ 32 mode.
  • a specified level for example L level
  • FIG. 3 The command that can be input to the memory in this case are shown in FIG. 3 .
  • FIG. 4 The timing chart of an access to the memory is shown in FIG. 4 .
  • the number of commands that can be input to the memory 1 is smaller than the SDRAM with 512M ⁇ 32 bit configuration.
  • a first address to be read out may be input once before inputting/outputting data as shown in FIG. 4 , and then after that, it is possible to transfer data at high speed in ⁇ 32 mode.
  • FIG. 5 shows the pin configuration of the random transfer mode.
  • the control circuit 6 lets the MRS circuit hold the value when the command indicating of the random transfer mode is input and the switching circuit 2 switches an input to each pin as shown in FIG. 5 .
  • the commands that can be used in this random transfer mode are shown in FIG. 6 . If set to the random transfer mode as shown in FIG. 6 , it becomes possible to access to a memory cell by bank. Therefore, as shown in FIG. 7 , a command and an address are input to access the memory according to the input address and then data is input/output.
  • the present invention is not limited to the above embodiment but various modifications can be made.
  • the pin configurations shown in FIGS. 2 to 7 can be changed as appropriate according to the specification and the capacity of the target memory device.
  • a mode is set by a command for specifying the mode and the address pins in the switching circuit are switched to the data pins by the mode specification pin.
  • the switching circuit may change the address pins to pins for inputting/outputting data by an output of the MRS circuit and the mode specification pin is not necessarily required.
  • a predetermined value is held in the MRS circuit by the mode specification pin, and the mode is not necessarily specified by a command input.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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US12/014,990 2007-02-07 2008-01-16 Semiconductor memory device having selectable transfer modes Expired - Fee Related US7830740B2 (en)

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JP2007027983A JP2008192264A (ja) 2007-02-07 2007-02-07 半導体記憶装置

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170212853A1 (en) * 2013-12-25 2017-07-27 Renesas Electronics Corporation Semiconductor device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102605637B1 (ko) * 2018-07-27 2023-11-24 에스케이하이닉스 주식회사 반도체 장치 및 데이터 처리 시스템
US11086803B2 (en) 2018-10-05 2021-08-10 Micron Technology, Inc. Dynamically configuring transmission lines of a bus
US20220188262A1 (en) * 2020-12-11 2022-06-16 Skyworks Solutions, Inc. Auto-enumeration of peripheral devices on a serial communication bus

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US5086407A (en) * 1989-06-05 1992-02-04 Mcgarity Ralph C Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation
US5636174A (en) * 1996-01-11 1997-06-03 Cirrus Logic, Inc. Fast cycle time-low latency dynamic random access memories and systems and methods using the same
JPH11328971A (ja) 1998-04-03 1999-11-30 Hyundai Electronics Ind Co Ltd 半導体メモリ装置
US6993601B2 (en) * 2002-02-22 2006-01-31 Murata Manufacturing Co., Ltd. Interface card including selectable data transmission route modes including first transmission route mode via memory buffer and second transmission route mode not via memory buffer
US7102958B2 (en) * 2001-07-20 2006-09-05 Samsung Electronics Co., Ltd. Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods
US7139847B2 (en) * 1999-07-23 2006-11-21 Samsung Electronics Co., Ltd. Semiconductor memory device having externally controllable data input and output mode
US7310717B2 (en) * 2002-06-21 2007-12-18 Renesas Technology Corp. Data transfer control unit with selectable transfer unit size

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JPS6396797A (ja) * 1986-10-13 1988-04-27 Matsushita Electric Ind Co Ltd 半導体メモリ
JPH0697560B2 (ja) * 1987-11-19 1994-11-30 三菱電機株式会社 半導体記憶装置
JPH06162762A (ja) * 1992-11-16 1994-06-10 Matsushita Electron Corp 半導体記憶装置
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Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086407A (en) * 1989-06-05 1992-02-04 Mcgarity Ralph C Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation
US5636174A (en) * 1996-01-11 1997-06-03 Cirrus Logic, Inc. Fast cycle time-low latency dynamic random access memories and systems and methods using the same
JPH11328971A (ja) 1998-04-03 1999-11-30 Hyundai Electronics Ind Co Ltd 半導体メモリ装置
US7139847B2 (en) * 1999-07-23 2006-11-21 Samsung Electronics Co., Ltd. Semiconductor memory device having externally controllable data input and output mode
US7102958B2 (en) * 2001-07-20 2006-09-05 Samsung Electronics Co., Ltd. Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods
US6993601B2 (en) * 2002-02-22 2006-01-31 Murata Manufacturing Co., Ltd. Interface card including selectable data transmission route modes including first transmission route mode via memory buffer and second transmission route mode not via memory buffer
US7310717B2 (en) * 2002-06-21 2007-12-18 Renesas Technology Corp. Data transfer control unit with selectable transfer unit size

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170212853A1 (en) * 2013-12-25 2017-07-27 Renesas Electronics Corporation Semiconductor device
US9977753B2 (en) * 2013-12-25 2018-05-22 Renesas Electronics Corporation Semiconductor device

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JP2008192264A (ja) 2008-08-21

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