US7541296B2 - Method for forming insulating film, method for forming multilayer structure and method for manufacturing semiconductor device - Google Patents

Method for forming insulating film, method for forming multilayer structure and method for manufacturing semiconductor device Download PDF

Info

Publication number
US7541296B2
US7541296B2 US11/171,318 US17131805A US7541296B2 US 7541296 B2 US7541296 B2 US 7541296B2 US 17131805 A US17131805 A US 17131805A US 7541296 B2 US7541296 B2 US 7541296B2
Authority
US
United States
Prior art keywords
film
coating film
hydrogen plasma
forming
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US11/171,318
Other languages
English (en)
Other versions
US20060178017A1 (en
Inventor
Tamotsu Owada
Hirofumi Watatani
Yoshihiro Nakata
Shirou Ozaki
Shun-ichi Fukuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OZAKI, SHIROU, FUKUYAMA, SHUN-ICHI, NAKATA, YOSHIHIRO, OWADA, TAMOTSU, WATATANI, HIROFUMI
Publication of US20060178017A1 publication Critical patent/US20060178017A1/en
Assigned to FUJITSU MICROELECTRONICS LIMITED reassignment FUJITSU MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU LIMITED
Application granted granted Critical
Publication of US7541296B2 publication Critical patent/US7541296B2/en
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF ADDRESS Assignors: FUJITSU SEMICONDUCTOR LIMITED
Assigned to AIZU FUJITSU SEMICONDUCTOR LIMITED reassignment AIZU FUJITSU SEMICONDUCTOR LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU SEMICONDUCTOR LIMITED
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME AND CHANGE OF ADDRESS Assignors: AIZU FUJITSU SEMICONDUCTOR LIMITED
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Definitions

  • the present invention relates to a method for forming an insulating film, a method for forming a multilayer structure and a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for forming an insulating film using low dielectric constant insulating materials (Low-k materials), a method for forming a multilayer structure using the insulating film, and a method for manufacturing a semiconductor device having the multilayer structure.
  • Low-k materials low dielectric constant insulating materials
  • a propagation speed of signals is determined mainly by a wiring resistance and a parasitic capacitance of an insulating film which is present between wirings.
  • a wiring interval is equal to or more than 1 ⁇ m, a capacitance between adjoining wirings is small and has a small effect on a speed of the whole device.
  • the wiring interval is about equal to or less than 0.5 ⁇ m, the capacitance between adjoining wirings has a larger effect thereon.
  • a circuit may be formed at a wiring interval of equal to or less than 0.2 ⁇ m.
  • the capacitance between adjoining wirings has an extremely large effect on the device speed. Further, a high integration in the semiconductor device proceeds in recent years and therefore, the wiring interval is made narrower. As a result, the capacitance between adjoining wirings increases if the wiring thickness is the same as heretofore. Accordingly, when reducing the wiring thickness to decrease a region of an insulating film between wirings, the capacitance between adjoining wirings can be reduced.
  • the most effective method for attaining reduction in the capacitance between adjoining wirings is to allow a lower dielectric constant of an insulating film used. From that point of view, low-k materials having a dielectric constant of about 2.0 to 2.5 are taken notice of.
  • a so-called spin-on process is used for one method for forming the insulating film (Low-k insulating film) using the Low-k materials.
  • the spin-on process is a process as described below.
  • a precursor solution formed by dispersing Low-k materials in a solvent is coated on a predetermined substrate by a spin coating method to form a coating film.
  • the coating film is heated at a temperature near a boiling point of the solvent to remove the solvent (a baking process). Then, the coating film is further heated at a higher temperature for a given length of time. As a result, the coating film is sintered to form a network structure where molecules within the Low-k materials are cross-linked (a curing process).
  • a Low-k insulating film is formed.
  • the method comprises, for example, the steps of: forming a lower copper (Cu) wiring as a conductive material by a damascene method, forming thereon a diffusion barrier film for preventing copper diffusion by a CVD (Chemical Vapor Deposition) method, forming a Low-k insulating film as an interlayer insulating film by the spin-on process, forming an etching stopper film (a middle stopper film) or a cap film using the CVD method again, and forming within the Low-k insulating film a via which communicates with the lower copper wiring, or an upper copper wiring.
  • CVD Chemical Vapor Deposition
  • the diffusion barrier film as well as the interlayer insulating film is required to have a lower dielectric constant. Therefore, the diffusion barrier film is now formed using silicon nitride (SiN) or silicon carbide (SiC), particularly, SiC having a small oxygen content.
  • minute wirings are generally used for the lower layer in many cases.
  • the above-described problem of the capacitance between adjoining wirings becomes more significant and therefore, it is strongly desired that the Low-k materials are used particularly for such a portion.
  • the capacitance between adjoining wirings in the upper and lower layers also becomes important due to expansion of an electric field. Accordingly, the necessity of providing the Low-k insulating film not only between lateral wirings but also between vertical wirings increases at present.
  • the following method comprises the steps of subjecting a surface of the copper wiring formed by the damascene method to a cleanup treatment with ammonia plasma and depositing thereon SiN while keeping a vacuum condition (see, Japanese Unexamined Patent Publication No. 2001-291720). Further, this proposal discloses that the adhesion between a copper wiring and a silicon oxide film which is present between the copper wirings is improved by thus treating the surface of the copper wiring with ammonia plasma.
  • a heat treatment such as a baking treatment or a curing treatment is required as described above.
  • the curing treatment occupies a considerable amount of the time necessary for the heat treatment.
  • the curing treatment is usually performed at a temperature of about 400° C. in an inactive atmosphere.
  • the following disadvantages are normally found.
  • a mechanical physical property of the Low-k insulating film is affected, or adhesion between the Low-k insulating film and the underlying film where the Low-k insulating film is formed or the etching stopper film formed on the insulating film is reduced.
  • the curing treatment is performed using a method of treating wafers in a single-wafer type using a hot plate or a method of collectively treating a plurality of wafers (e.g., 25 sheets) using a furnace.
  • the method of treating wafers in a single-wafer type using a hot plate is disadvantageous in that a long period of time is required for treatment of a plurality of wafers.
  • the method of collectively treating wafers using a furnace is more advantageous.
  • the heat treatment at about 400° C. for about 60 minutes is required.
  • it becomes necessary to carry wafers in the furnace to carry wafers from the furnace to the outside, to displace atmosphere within the furnace and to lower or raise the temperature within the furnace.
  • the curing treatment requires about from 90 to 120 minutes in total or may require much more time in some cases.
  • the method of collectively treating wafers using a furnace has a problem that a temperature distribution within the furnace is normally nonuniform. Therefore, heat is nonuniformly applied between wafers or within a wafer surface particularly when the wafers increase in number or in size. As a result, it becomes difficult to form the Low-k insulating film uniformly.
  • the process cost can be largely reduced. Further, the time required for the whole process including the subsequent step of forming the etching stopper film to form the multilayer wiring structure can be of course shortened, so that the cost of the whole process can also be reduced. Further, when the uniform Low-k insulating film can be formed irrespective of the number or size of wafers, the multilayer wiring structure having high quality and high performance, and the semiconductor device having the multilayer wiring structure can be effectively formed at low cost.
  • This method for forming an insulating film comprises the steps of: coating a solution containing an insulating material to form a coating film containing the insulating material; heating the coating film to remove a solvent therefrom; and irradiating hydrogen plasma onto the coating film after removal of the solvent.
  • This method for forming a multilayer structure comprises the steps of: coating a solution containing an insulating material to form a coating film containing the insulating material; heating the coating film to remove a solvent therefrom; and irradiating hydrogen plasma onto the coating film after removal of the solvent to form the insulating film.
  • a method for manufacturing a semiconductor device having the multilayer structure using the insulating film comprises the steps of: coating a solution containing an insulating material to form a coating film containing the insulating material; heating the coating film to remove a solvent therefrom; and irradiating hydrogen plasma onto the coating film after removal of the solvent to form the insulating film.
  • FIG. 1 shows one example of a flow chart for forming a Low-k insulating film using a spin-on process.
  • FIG. 2 shows an effect of a hydrogen plasma treatment on a film thickness of a Low-k insulating film.
  • FIG. 3 shows an effect of a hydrogen plasma treatment on a dielectric constant of a Low-k insulating film.
  • FIG. 4 is a schematic sectional view showing an essential part of a multilayer wiring structure according to a first application example.
  • FIG. 5 is a schematic sectional view showing an essential part of a multilayer wiring structure according to a second application example.
  • FIG. 6 is a schematic sectional view showing an essential part of a multilayer wiring structure according to a third application example.
  • FIG. 1 shows one example of a flow chart for forming a Low-k insulating film using a spin-on process.
  • Low-k materials are dispersed in a solvent to form a precursor solution (step S 1 ).
  • the Low-k materials which can be used include an organic polyarylene or polyallyl ether, an inorganic hydrogen sillsquioxane (HSQ), an organic and inorganic hybrid methylsillsquioxane (MSQ), or a mixed material of HSQ and MSQ.
  • the precursor solution is coated by a spin coating method on an underlying substrate or underlying layer on which the Low-k insulating film is formed (step S 2 ).
  • a thickness of the Low-k insulating film formed can be controlled by a viscosity or amount of the precursor solution which drops on the underlying layer, or by a rotational velocity of the underlying layer.
  • a coating film formed by the spin coating method is subjected to a baking treatment (step S 3 ).
  • the coating film is heated for about several minutes at a temperature near a boiling point of the solvent in the precursor solution and thereby removing the solvent from the coating film.
  • a suitable film such as SiC, silicon oxide (SiO 2 ), SiN, silicon-oxy-carbide (SiOC) or tetraethoxysilane is formed to an appropriate film thickness by a CVD method to thereby form a barrier film (step S 4 ).
  • the SiC film can be formed by the CVD method using only tetramethylsilane gas, or using tetramethylsilane gas and an oxidizing agent gas such as carbon dioxide as raw materials.
  • the SiC film can also be formed by the CVD method using only dimethylphenylsilane, or using dimethylphenylsilane and an oxidizing agent gas as raw materials.
  • the SiOC film can be formed by the CVD method using tetramethyl-cyclo-tetrasiloxane and an oxidizing agent gas.
  • the coating film after the baking treatment is irradiated with hydrogen plasma through the barrier film using the same CVD apparatus as used in forming the barrier film without taking out the film from the device (step S 5 ).
  • a treating object after the formation of the barrier film is heated as it is to about 400° C. within the same CVD apparatus as used in forming the barrier film, or is carried to a treatment region heated to 400° C. Then, the treating object is irradiated with a predetermined amount of hydrogen plasma from the barrier film side only for a predetermined time.
  • a dose of the hydrogen plasma in the step S 5 may be set, for example, to the total amount of the hydrogen plasma necessary for the curing treatment of the coating film after the baking treatment.
  • the hydrogen plasma treatment is performed as described above. That is, the barrier film is formed after the baking treatment and then, the hydrogen plasma treatment is performed through the barrier film.
  • FIG. 2 shows an effect of the hydrogen plasma treatment on a film thickness of the Low-k insulating film.
  • the horizontal axis shows a measuring point of the film thickness of the Low-k insulating film
  • the vertical axis shows the film thickness (nm) of the Low-k insulating film.
  • FIG. 2 shows measurement results of the film thickness of the Low-k insulating film in each measuring point.
  • the following samples are used: a sample after the baking treatment and before the formation of the barrier film, a sample formed by directly performing the hydrogen plasma treatment after the baking treatment, and a sample formed by forming a barrier film after the baking treatment and then performing the hydrogen plasma treatment through the barrier film.
  • the measuring points are set to corresponding positions among the respective samples.
  • the sample formed by directly performing the hydrogen plasma treatment after the baking treatment is remarkably reduced in the film thickness in any measuring point, as compared with the sample formed by performing the hydrogen plasma treatment through the barrier film.
  • the film thickness in each of the measuring points is scarcely reduced from the initial state after the baking treatment and before the formation of the barrier film, even after the hydrogen plasma treatment.
  • FIG. 3 shows an effect of the hydrogen plasma treatment on a dielectric constant of the Low-k insulating film.
  • FIG. 3 shows measurement results of the dielectric constant of each sample described in the FIG. 2 .
  • the sample formed by directly performing the hydrogen plasma treatment after the baking treatment is increased in the dielectric constant, as compared with the initial state after the baking treatment and before the formation of the barrier film as well as the sample formed by performing the hydrogen plasma treatment through the barrier film.
  • increase in the dielectric constant is suppressed even after the hydrogen plasma treatment.
  • the hydrogen plasma treatment is performed for a short period of time after the baking treatment of the spin-coated Low-k material, so that the curing treatment equal to or more than the conventional curing treatment using a furnace can be performed.
  • the barrier film is formed on a surface of the coating film after the baking treatment and then the hydrogen plasma treatment is performed through the barrier film, so that the Low-k insulating film having a desired film thickness and a dielectric constant can be formed.
  • the formation of the barrier film and the hydrogen plasma treatment can be performed using the same CVD apparatus. Therefore, the curing treatment time is largely shortened so that the Low-k insulating film can be effectively formed.
  • the barrier film for use in the hydrogen plasma treatment can be used as an etching stopper film (a middle stopper film) or a cap film within the multilayer wiring structure.
  • the formation process of the Low-k insulating film is allowed to serve as a so-called multitasking process capable of simultaneously performing the curing treatment and the formation of a laminated film such as an etching stopper film laminated on the insulating film. Accordingly, in this case, a material or film thickness of the barrier film may be set according to the function or intended use of the laminated film.
  • the curing treatment can be incorporated into the downstream CVD process. Therefore, the time required for the curing treatment which may be repeatedly performed in the formation process of the multilayer wiring structure is largely shortened so that the multilayer wiring structure can be more effectively formed. As a result, the process cost or the product cost can be reduced. Further, existing facilities can be used for a spin coater or the CVD apparatus. Therefore, a new plant investment is not required, and even when a wafer having a large diameter is used, introduction of a large-sized furnace corresponding to a size of the wafer is not required.
  • a method is described in which one layer barrier film is formed after the baking treatment of the coating film containing the Low-k material and then a total amount of the hydrogen plasma necessary for the curing treatment is irradiated collectively (steps S 3 to S 5 ).
  • the irradiation of hydrogen plasma may be performed in numbers.
  • the following method may also be used. The formation of a thin barrier film and the irradiation of hydrogen plasma are alternately repeated after the baking treatment to finally form the barrier film having a desired film thickness as well as to complete the curing treatment and thereby forming the Low-k insulating film.
  • the film thickness of each of the barrier films to be formed at one time and the dose of hydrogen plasma may be each set according to the number of repetitions thereof. Also by using the method, the same effects as those shown in the FIGS. 2 and 3 can be obtained.
  • a hydrogen plasma irradiation head within the CVD apparatus that performs formation of the barrier film, an atmosphere causing no contamination of impurities in vacuum can be kept, so that a desired barrier film can be obtained.
  • the Low-k insulating film is formed to have a porous structure containing voids and thereby further reducing the dielectric constant.
  • a template material for example, a desorbing agent having a boiling point slightly higher than that of a solvent is incorporated into the solution.
  • the resulting solution is coated on the underlying layer to form the coating film and then the film is subjected to the baking treatment.
  • the coating film is heated at a temperature near the boiling point of the template material, and thereby removing the template material from the coating film.
  • the formation of the barrier film and the hydrogen plasma treatment may be performed according to the steps S 4 and S 5 .
  • the Low-k material previously having a molecular cluster structure may be used.
  • a coating film having voids is formed after the baking treatment.
  • the formation of the barrier film and the hydrogen plasma treatment may be performed according to the steps S 4 and S 5 .
  • the formation of the barrier film and the hydrogen plasma treatment may be of course performed alternately as described above.
  • FIG. 4 is a schematic sectional view showing an essential part of a multilayer wiring structure according to the first application example.
  • a PSG (Phospho-Silicate Glass) film 2 is formed to a film thickness of about 1.5 ⁇ m (substrate temperature: about 600° C.) by the CVD method and is planarized by a CMP (Chemical Mechanical Polishing) method.
  • a via groove is formed in the film by a conventional method using as a mask a resist pattern for extracting an electrode. Then, tungsten is buried in the via and unnecessary tungsten is removed by the CMP method. Thus, a tungsten plug 3 connected to the element 1 is formed.
  • a SiC film (ESL 3 : trade name, produced by Novellus Systems, Inc.) is formed by the CVD method to form a SiC etching stopper film 4 having a film thickness of about 30 nm.
  • the SiC etching stopper film 4 is formed under the following conditions. That is, the flow rate of tetramethylsilane gas as a raw material is about 500 sccm, the pressure within a chamber is about 1.8 Torr, the high frequency radio frequency electric power is about 600 W, and the low frequency radio frequency electric power is about 300 W.
  • NCS trade name, produced by Catalysts & Chemicals Industries Co., Ltd.
  • a hybrid porous silica film 5 as the Low-k insulating film is formed to a film thickness of about 130 nm by the spin-on process.
  • NCS is spin-coated on the SiC etching stopper film 4 to form the film 5 .
  • the film 5 is just heated for about 3 minutes at a temperature of about 350° C. for the sake of the baking treatment for removing the solvent.
  • the SiC film (ESL 2 : trade name, produced by Novellus Systems, Inc.) is formed by the CVD method to form a SiC cap film 6 .
  • the curing treatment of the porous silica film 5 by hydrogen plasma irradiation is performed within the same CVD apparatus. More specifically, the following operation is performed. First, a first SiC film having a film thickness of about 5 nm is formed and then a first hydrogen plasma treatment is performed. Further, a second SiC film having a film thickness of about 5 nm is formed and then a second hydrogen plasma treatment is performed. This operation is repeatedly performed to finally form the SiC cap film 6 having a film thickness of about 30 nm.
  • each SiC film is formed under the following conditions. That is, the flow rate of tetramethylsilane gas as the raw material is about 1000 sccm, the pressure within a chamber is about 2.3 Torr, the high frequency radio frequency electric power is about 600 W and the low frequency radio frequency electric power is about 300 W.
  • Each SiC film is allowed to function as a barrier film which prevents the porous silica film 5 from being directly irradiated with the hydrogen plasma.
  • the hydrogen plasma treatment is performed by irradiating hydrogen plasma five times for about 90 seconds in total under the following conditions. That is, the flow rate of hydrogen gas is about 4000 sccm, the pressure within a chamber is about 2.3 Torr and the high frequency radio frequency electric power is about 250 W (single frequency).
  • an antireflection film (not shown) is provided.
  • the SiC cap film 6 , the porous silica film 5 and the SiC etching stopper film 4 are partially removed by the conventional method to form a wiring groove.
  • a tantalum nitride (TaN) film 7 and a Cu film 8 are each formed in the wiring groove to a film thickness of about 30 nm, and copper is buried therein by a plating method. Further, unnecessary copper is removed by the CMP method to form a copper wiring 9 .
  • an UDC-SiC (undoped carbide SiC) film having a small oxygen content is formed to a film thickness of about 50 nm by the CVD method and thereby forming an UDC-SiC diffusion barrier film 10 .
  • the UDC-SiC diffusion barrier film 10 is formed under the following conditions. That is, the flow rate of tetramethylsilane gas as a raw material is about 650 sccm, the pressure within a chamber is about 4.5 Torr, the high frequency radio frequency electric power is about 500 W, and the low frequency radio frequency electric power is about 150 W.
  • a hybrid porous silica film 11 is formed to a film thickness of about 250 nm by the spin-on process using NCS in the same manner as in the first wiring layer. Also in this case, NCS is spin-coated on the UDC-SiC diffusion barrier film 10 to form the film 11 . Then, the film 11 is just heated for about 3 minutes at a temperature of about 350° C. for the sake of the baking treatment.
  • the SiC film (ESL 2 : trade name) is formed by the CVD method to form a SiC middle stopper film 12 .
  • the curing treatment of the porous silica film 11 by hydrogen plasma irradiation is performed within the same CVD apparatus.
  • each SiC film is formed by about 5 nm and the hydrogen plasma treatment is performed five times during each film formation.
  • the SiC middle stopper film 12 having a film thickness of about 30 nm is finally formed.
  • the film formation conditions of the SiC middle stopper film 12 and the hydrogen plasma irradiation conditions of the hydrogen plasma treatment are set to the same conditions as those in the formation of the SiC cap film 6 previously formed.
  • a hybrid porous silica film 13 is formed to a film thickness of about 170 nm by the spin-on process using NCS in the same manner as in the first wiring layer. Also in this case, NCS is spin-coated on the SiC middle stopper film 12 to form the film 13 . Then, the film 13 is just heated for about 3 minutes at a temperature of about 350° C. for the sake of the baking treatment.
  • the SiC film (ESL 2 : trade name) is formed by the CVD method to form a SiC cap film 14 .
  • the curing treatment of the porous silica film 13 by hydrogen plasma irradiation is performed within the same CVD apparatus.
  • each SiC film is formed by about 5 nm and the hydrogen plasma treatment is performed five times during each film formation.
  • the SiC cap film 14 having a film thickness of about 30 nm is finally formed.
  • the film formation conditions of the SiC cap film 14 and the hydrogen plasma irradiation conditions of the hydrogen plasma treatment are set to the same conditions as those in the formation of the SiC cap film 6 previously formed.
  • an antireflection film (not shown) is provided.
  • a via groove that communicates with the copper wiring 9 is first formed by the conventional method.
  • a wiring groove is formed similarly by the conventional method in which a hole is opened until the SiC middle stopper film 12 is exposed.
  • a TaN film 15 and a Cu film 16 are each formed in the via groove and the wiring groove to a film thickness of about 30 nm, and copper is buried therein by the plating method. Further, unnecessary copper is removed by the CMP method to form a via 17 a and a copper wiring 17 b .
  • an UDC-SiC diffusion barrier film 18 is formed to a film thickness of about 50 nm by the CVD method.
  • the forming conditions thereof are set to the same conditions as those in the formation of the UDC-SiC diffusion barrier film 10 previously formed.
  • a third wiring layer is formed as follows. First, a porous silica film 19 , a SiC middle stopper film 20 , a porous silica film 21 and a SiC cap film 22 are sequentially formed on the film 18 . Next, a wiring groove is formed and then, a TaN film 23 and a Cu film 24 are formed in the groove. Next, copper is buried therein to form a copper wiring 25 . On the surface, a SiC etching stopper film 26 and a SiO 2 interlayer insulating film 27 are formed. Next, a via that communicates with the copper wiring 25 is formed and then, a tungsten plug 28 is formed in the via. Next, an aluminum pad 29 is formed on the plug 28 . Finally, a protective film 30 is formed on an area other than a part of the aluminum pad 29 surface.
  • the following effects can be found.
  • a reliability acceleration test using a heat cycle occurrence of deterioration is prevented and a preferred result is obtained, as compared with the multilayer wiring structure formed by a method where the film formation is performed using NCS and the conventional curing treatment is performed using a furnace.
  • FIG. 5 is a schematic sectional view showing an essential part of the multilayer wiring structure according to the second application example.
  • the second and third wiring layers are sequentially formed according to the following steps.
  • the same elements as those described in the first application example are indicated by the same reference numerals as in the first application example and the description is omitted.
  • a plasma treatment is first performed within the same CVD apparatus while introducing carbon dioxide, whereby a surface of the UDC-SiC diffusion barrier film 10 is oxidized.
  • carbon dioxide plasma irradiation is performed under the following conditions. That is, the flow rate of carbon dioxide is about 500 sccm, the pressure within a chamber is about 3.5 Torr, the high frequency radio frequency electric power is about 100 W and the treating time is about 5 seconds.
  • a silicon-oxy-carbide film 40 is formed to a film thickness of about 170 nm while introducing tetramethyl-cyclo-tetrasiloxane and carbon dioxide into the chamber.
  • the silicon-oxy-carbide film 40 is formed under the following conditions. That is, the flow rate of tetramethyl-cyclo-tetrasiloxane is about 1 sccm, the flow rate of carbon dioxide is about 5000 sccm, the pressure within the chamber is about 3.5 Torr, the high frequency radio frequency electric power is about 300 W and the low frequency radio frequency electric power is about 200 W.
  • a hybrid porous silica film 41 as the Low-k insulating film is formed to a film thickness of about 150 nm by the spin-on process using NCS in the same manner as in the first wiring layer. Also in this case, NCS is spin-coated on the silicon-oxy-carbide film 40 to form the film 41 . Then, the film is just heated for about 3 minutes at a temperature of about 350° C. for the sake of the baking treatment.
  • the SiC film (ESL 2 : trade name) is formed by the CVD method to form a SiC cap film 42 .
  • the curing treatment of the porous silica film 41 by hydrogen plasma irradiation is performed within the same CVD apparatus.
  • each SiC film is formed by about 5 nm and the hydrogen plasma treatment is performed five times during each film formation.
  • the SiC cap film 42 having a film thickness of about 30 nm is finally formed.
  • the film formation conditions of the SiC cap film 42 and the hydrogen plasma irradiation conditions of the hydrogen plasma treatment are set to the same conditions as those in the formation of the SiC cap film 6 previously formed.
  • an antireflection film (not shown) is provided.
  • a via groove that communicates with the copper wiring 9 is first formed by the conventional method.
  • a wiring groove that reaches the silicon-oxy-carbide film 40 is formed similarly by the conventional method.
  • a TaN film 43 and a Cu film 44 are each formed to a film thickness of about 30 nm, and copper is buried in the via groove and the wiring groove by the plating method. Further, unnecessary copper is removed by the CMP method to form a via 45 a and a copper wiring 45 b .
  • an UDC-SiC diffusion barrier film 46 is formed to a film thickness of about 50 nm by the CVD method.
  • the forming conditions are set to the same conditions as those in the formation of the UDC-SiC diffusion barrier film 10 previously formed.
  • a subsequent third wiring layer is formed as follow.
  • the porous silica film 19 , the SiC middle stopper film 20 , the porous silica film 21 and the SiC cap film 22 are sequentially formed on the film 46 .
  • a wiring groove is formed and then, the TaN film 23 and the Cu film 24 are formed in the groove.
  • copper is buried therein to form the copper wiring 25 .
  • the SiC etching stopper film 26 and the SiO 2 interlayer insulating film 27 are formed.
  • a via that communicates with the Cu wiring 25 is formed and then, the tungsten plug 28 is formed in the via.
  • the aluminum pad 29 is formed on the tungsten plug 28 .
  • the protective film 30 is formed on an area other than a part of the aluminum pad 29 surface.
  • the following effects can be found.
  • a reliability acceleration test using a heat cycle occurrence of deterioration is prevented and a preferred result is obtained, as compared with the multilayer wiring structure formed by a method where the film formation is performed using NCS and the conventional curing treatment is performed using a furnace.
  • FIG. 6 is a schematic sectional view showing an essential part of the multilayer wiring structure according to the third application example.
  • the PSG (Phospho-Silicate Glass) film 2 is formed to a film thickness of about 1.5 ⁇ m (substrate temperature: about 600° C.) and is planarized by the CMP method.
  • a via groove is formed in the film and then, tungsten is buried in the via.
  • the SiC film (ESL 3 : trade name, produced by Novellus Systems, Inc.) is formed to form the SiC etching stopper film 4 having a film thickness of about 30 nm.
  • an organic insulating film 50 as the Low-k insulating film is formed to a film thickness of about 250 nm by the spin-on process.
  • Silk is spin-coated on the SiC etching stopper film 4 to form the organic insulating film 50 .
  • the film 50 is just heated for about 5 minutes at a temperature of about 350° C. for the sake of the baking treatment for removing the solvent.
  • a SiO film is formed by the CVD method to form a SiO cap film 51 .
  • the curing treatment of the organic insulating film 50 by hydrogen plasma irradiation is performed within the same CVD apparatus. More specifically, the following operation is performed. After completion of heating at about 400° C. for about one minute, a first SiO film having a film thickness of about 16 nm is formed and then a first hydrogen plasma treatment is performed. Further, after completion of heating at about 400° C. for about one minute, a second SiO film having a film thickness of about 5 nm is formed and then a second hydrogen plasma treatment is performed. This operation is repeatedly performed to finally form the SiO cap film 51 having a film thickness of about 100 nm.
  • the heating treatment for about 6 minutes and five hydrogen plasma treatments are intermittently performed.
  • the hydrogen plasma treatment is performed by irradiating hydrogen plasma five times for about 90 seconds in total under the following conditions. That is, the flow rate of hydrogen gas is about 4000 sccm, the pressure within a chamber is about 2.3 Torr and the high frequency radio frequency electric power is about 250 W (single frequency).
  • the SiO cap film 51 , the organic insulating film 50 and the SiC etching stopper film 4 are partially removed by the conventional method to form a wiring groove.
  • a TaN film 52 and a Cu film 53 are each formed in the wiring groove to a film thickness of about 30 nm, and copper is buried therein by the plating method. Further, unnecessary copper is removed by the CMP method to form a copper wiring 54 .
  • the SiC film (ESL 3 : trade name) is formed to a film thickness of about 50 nm by the CVD method to form a SiC diffusion barrier film 55 .
  • an organic insulating film 56 is formed to a film thickness of about 450 nm by the spin-on process using SiLK (trade name) in the same manner as in the first wiring layer.
  • a SiO cap film 57 is formed to a film thickness of about 100 nm by the CVD method.
  • Silk is spin-coated on the SiC diffusion barrier film 55 to form the organic insulating film 56 .
  • the film 56 is just heated for about 5 minutes at a temperature of about 350° C. for the sake of the baking treatment.
  • each SiO film is formed by about 16 nm and the hydrogen plasma treatment is performed five times during each film formation.
  • the SiO cap film 57 having a film thickness of about 100 nm is finally formed.
  • the hydrogen plasma irradiation conditions of the hydrogen plasma treatment are set to the same conditions as those in the formation of the SiO cap film 51 previously formed.
  • a SiN film is formed to a film thickness of about 50 nm by the CVD method to form a SiN hard mask 58 . Further, wiring pattern formation and via pattern formation on the SiN hard mask 58 are performed to form a via groove and a wiring groove. Subsequently, the following operation is performed in the same manner as in the formation of the copper wiring 54 in the first wiring layer.
  • a TaN film 59 and a Cu film 60 are each formed to a film thickness of about 30 nm, and copper is buried in the via groove and the wiring groove by the plating method. Further, a via 61 a and a copper wiring 61 b are formed by the CMP method. Then, the SiC film (ESL 3 : trade name) is formed to a film thickness of about 50 nm by the CVD method to form a SiC diffusion barrier film 62 .
  • a subsequent third wiring layer is formed as follows. First, an organic insulating film 63 , a SiO cap film 64 and a SiN hard mask 65 are sequentially formed on the film 62 . Next, a wiring groove is formed and then, a TaN film 66 and a Cu film 67 are formed in the groove. Next, copper is buried therein to form a copper wiring 68 . On the surface, a SiC diffusion barrier film 69 and the SiO 2 interlayer insulating film 27 are formed. Next, a via that communicates with the copper wiring 68 is formed and then, the tungsten plug 28 is formed in the via. Next, the aluminum pad 29 is formed on the plug 28 . Finally, the protective film 30 is formed on an area other than a part of the aluminum pad 29 surface.
  • a capacitance of the second wiring layer is about 180 fF/mm.
  • a heat treatment at a temperature of about 400° C. for about 30 minutes film peeling is not observed at all.
  • a reliability acceleration test using a heat cycle occurrence of deterioration is prevented and a preferred result is obtained, as compared with the multilayer wiring structure formed by a method where the film formation is performed using SiLK (trade name) and the conventional curing treatment is performed using a furnace.
  • the curing treatment of the Low-k material in the spin-on process is performed as follows. After the baking treatment of the Low-k material, the barrier film is formed. Then, hydrogen plasma is irradiated through the film using the CVD apparatus. As a result, a high-quality Low-k insulating film having a desired film thickness and dielectric constant can be effectively formed.
  • existing facilities can be used. Therefore, introduction of new facilities, for example, introduction of a large-sized curing treatment apparatus such as an electric furnace is not required. Further, the curing treatment is performed using hydrogen plasma. Therefore, even when forming the Low-k material on the low dielectric constant film such as SiC, the adhesion between films can be secured.
  • the barrier film formed on the Low-k material is an etching stopper film (a middle stopper film) or cap film having the multilayer wiring structure
  • the curing treatment can be incorporated into the CVD film formation step in forming such a film. Therefore, more effective formation of the Low-k insulating film can be realized.
  • the Low-k insulating film having a desired film thickness and dielectric constant can be formed. Therefore, the via depth or wiring thickness formed on the film can be suitably controlled. As a result, the semiconductor device having a highly reliable multilayer wiring structure capable of high-speed operation can be realized at low cost.
  • the insulating film is formed by the following method.
  • a solution containing an insulating material is coated to form a coating film.
  • the coating film is heated to remove a solvent therefrom.
  • hydrogen plasma is irradiated onto the coating film after removal of the solvent.
  • the multilayer structure having high quality and high performance, and the semiconductor device having the multilayer structure can be effectively formed at low cost.
US11/171,318 2005-02-09 2005-07-01 Method for forming insulating film, method for forming multilayer structure and method for manufacturing semiconductor device Active 2027-03-05 US7541296B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005032446A JP4223012B2 (ja) 2005-02-09 2005-02-09 絶縁膜の形成方法、多層構造の形成方法および半導体装置の製造方法
JP2005-032446 2005-02-09

Publications (2)

Publication Number Publication Date
US20060178017A1 US20060178017A1 (en) 2006-08-10
US7541296B2 true US7541296B2 (en) 2009-06-02

Family

ID=36780513

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/171,318 Active 2027-03-05 US7541296B2 (en) 2005-02-09 2005-07-01 Method for forming insulating film, method for forming multilayer structure and method for manufacturing semiconductor device

Country Status (2)

Country Link
US (1) US7541296B2 (ja)
JP (1) JP4223012B2 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100459064C (zh) * 2005-12-12 2009-02-04 中芯国际集成电路制造(上海)有限公司 改进低介电常数层的粘附强度的方法
JP5183588B2 (ja) * 2009-07-15 2013-04-17 三菱電機株式会社 光起電力装置の製造方法
US20110318502A1 (en) * 2009-12-24 2011-12-29 Spp Process Technology Systems Uk Limited Methods of depositing sio2 films
JP6918386B1 (ja) * 2020-12-09 2021-08-11 株式会社アビット・テクノロジーズ 絶縁膜の製造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999019904A1 (en) 1997-10-16 1999-04-22 Advanced Micro Devices, Inc. Borderless vias with hsq gap filled patterned metal layers
WO2003015150A1 (en) 2001-07-16 2003-02-20 Axcelis Technologies, Inc. Plasma curing of msq-based porous low-k film materials
US20030118845A1 (en) * 2001-12-11 2003-06-26 Knut Beekmann Diffusion barrier
US20030232495A1 (en) * 2002-05-08 2003-12-18 Farhad Moghadam Methods and apparatus for E-beam treatment used to fabricate integrated circuit devices
US6670285B2 (en) * 2001-03-14 2003-12-30 International Business Machines Corporation Nitrogen-containing polymers as porogens in the preparation of highly porous, low dielectric constant materials
US7129164B2 (en) * 2004-10-18 2006-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a multi-layer low-K dual damascene

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999019904A1 (en) 1997-10-16 1999-04-22 Advanced Micro Devices, Inc. Borderless vias with hsq gap filled patterned metal layers
JP2001520459A (ja) 1997-10-16 2001-10-30 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Ｈｓｑで間隙充填されたパターニングされた金属層を備えるボーダレスバイア
US6670285B2 (en) * 2001-03-14 2003-12-30 International Business Machines Corporation Nitrogen-containing polymers as porogens in the preparation of highly porous, low dielectric constant materials
WO2003015150A1 (en) 2001-07-16 2003-02-20 Axcelis Technologies, Inc. Plasma curing of msq-based porous low-k film materials
JP2004538637A (ja) 2001-07-16 2004-12-24 アクセリス テクノロジーズ， インコーポレイテッド Ｍｓｑ系多孔質低ｋ膜材料のプラズマ硬化
US20030118845A1 (en) * 2001-12-11 2003-06-26 Knut Beekmann Diffusion barrier
US20030232495A1 (en) * 2002-05-08 2003-12-18 Farhad Moghadam Methods and apparatus for E-beam treatment used to fabricate integrated circuit devices
US7129164B2 (en) * 2004-10-18 2006-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a multi-layer low-K dual damascene

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Partial Translation of Japanese Office Action dated Jun. 10, 2008, issued in corresponding Japanese Application No. 2005-032446.
Patent Abstracts of Japan, Publication No. 2001-291720, published on Oct. 19, 2001.
Patent Abstracts of Japan, Publication No. 2004-088047, published on Mar. 18, 2004.

Also Published As

Publication number Publication date
US20060178017A1 (en) 2006-08-10
JP2006222171A (ja) 2006-08-24
JP4223012B2 (ja) 2009-02-12

Similar Documents

Publication Publication Date Title
US8017522B2 (en) Mechanically robust metal/low-κ interconnects
US5607773A (en) Method of forming a multilevel dielectric
US7842518B2 (en) Method for fabricating semiconductor device
US6737747B2 (en) Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof
US7326651B2 (en) Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material
US7407879B2 (en) Chemical planarization performance for copper/low-k interconnect structures
US7304386B2 (en) Semiconductor device having a multilayer wiring structure
US8889544B2 (en) Dielectric protection layer as a chemical-mechanical polishing stop layer
US8384219B2 (en) Semiconductor having interconnects with improved mechanical properties by insertion of nanoparticles
KR20010076349A (ko) 반도체 장치 및 그 제조 방법
KR100489456B1 (ko) 반도체장치및그제조방법
US20050191847A1 (en) Method for manufacturing semiconductor device
JP4675258B2 (ja) 半導体装置の製造方法および半導体装置
US20060211240A1 (en) Method of enhancing adhesion between dielectric layers
JP3173426B2 (ja) シリカ絶縁膜の製造方法及び半導体装置の製造方法
US20070249164A1 (en) Method of fabricating an interconnect structure
US7541296B2 (en) Method for forming insulating film, method for forming multilayer structure and method for manufacturing semiconductor device
US20100301495A1 (en) Semiconductor device and method for manufacturing same
US6998325B2 (en) Method for manufacturing semiconductor device
US20160190002A1 (en) High Boiling Temperature Solvent Additives for Semiconductor Processing
KR940005723B1 (ko) 반도체 장치
JP2003031566A (ja) 低誘電率絶縁膜形成用組成物、これを用いる絶縁膜形成方法、及びそれにより得られた絶縁膜を有する電子部品
JPH09241518A (ja) 樹脂組成物および多層配線形成方法
US7897505B2 (en) Method for enhancing adhesion between layers in BEOL fabrication
JP5408116B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OWADA, TAMOTSU;WATATANI, HIROFUMI;NAKATA, YOSHIHIRO;AND OTHERS;REEL/FRAME:016750/0266;SIGNING DATES FROM 20050509 TO 20050510

AS Assignment

Owner name: FUJITSU MICROELECTRONICS LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089

Effective date: 20081104

Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089

Effective date: 20081104

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:025046/0478

Effective date: 20100401

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPAN

Free format text: CHANGE OF ADDRESS;ASSIGNOR:FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:041188/0401

Effective date: 20160909

AS Assignment

Owner name: AIZU FUJITSU SEMICONDUCTOR LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:053209/0468

Effective date: 20200331

AS Assignment

Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPAN

Free format text: CHANGE OF NAME AND CHANGE OF ADDRESS;ASSIGNOR:AIZU FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:053481/0962

Effective date: 20200410

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12