US7145543B2 - Image display unit - Google Patents
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- US7145543B2 US7145543B2 US10/450,148 US45014803A US7145543B2 US 7145543 B2 US7145543 B2 US 7145543B2 US 45014803 A US45014803 A US 45014803A US 7145543 B2 US7145543 B2 US 7145543B2
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Definitions
- the present invention relates to an image display and, more particularly, to an image display that requires refreshing of a data signal.
- a liquid crystal display for displaying a still picture and a moving picture has conventionally been employed in a personal computer, a television receiver, a portable telephone, a portable information terminal and the like.
- FIG. 17 is a circuit diagram showing a main part of such a liquid crystal display.
- this liquid crystal display includes a liquid crystal cell 70 , a scan line 71 , a common potential line 72 , a data signal line 73 and a liquid crystal drive circuit 74 , wherein liquid crystal drive circuit 74 includes an N-type TFT (Thin Film Transistor) 75 and a capacitor 76 .
- N-type TFT Thin Film Transistor
- N-type TFT 75 is connected between data signal line 73 and a data holding node N 75 and having the gate connected to scan line 71 .
- Capacitor 76 is connected between data holding node N 75 and common potential line 72 .
- One electrode of liquid crystal cell 70 is connected to data holding node N 75 and the other electrode thereof receives a reference potential VR.
- Common potential line 72 is applied with a common potential VC.
- Scan line 71 is driven by a vertical scan circuit (not shown) and data signal line 73 is driven by a horizontal scan circuit (not shown).
- N-type TFT 75 When scan line 71 is set to “H” level, N-type TFT 75 is made conductive to charge data holding node N 75 to a level on data signal line 73 through N-type TFT 75 .
- a light transmittance of liquid crystal cell 70 increases to the maximum when data holding node N 75 is at “H” level, for example, while the light transmittance decreases to the minimum when data holding node N 75 is at “L” level.
- Liquid crystal cells 70 are arranged in a plurality of rows and a plurality of columns to form one liquid crystal panel, on which one picture is displayed.
- An image display includes: a pixel display circuit displaying a pixel density corresponding to a potential of a data holding node; a data write circuit applying one of first and second potentials to the data holding node in accordance with an image signal; and a refresh circuit performing refresh of a potential at the data holding node in response to a refresh signal when the potential at the data holding node exceeds a predetermined third potential between the first and second potentials while performing no refresh of the potential at the data holding node in response to the refresh signal when the potential at the data holding node does not exceed the third potential. Therefore, since a potential at the data holding node is refreshed by the refresh circuit when a refresh signal is supplied thereto, refresh of a data signal can be performed with ease.
- the refresh circuit includes a capacitor having one electrode receiving a potential at the data holding node, having the other electrode receiving the refresh signal, and a capacitance value of which varies according to a potential difference between the one electrode and the other electrode.
- a change in capacitance value of the capacitor according to a potential at the data holding node is used to make it possible to select whether or not refresh of the potential at the data holding node is performed.
- the capacitor includes an N-channel field effect transistor, having a gate electrode serving as the one electrode, and having at least one of first and second electrodes serving as the other electrode.
- a capacitance value of the capacitor increases when a positive voltage is applied between the one electrode and the other electrode of the capacitor.
- the capacitor includes a P-channel field effect transistor having a gate electrode serving as the other electrode, and having at least one of first and second electrodes serving as the one electrode.
- a capacitance value of the capacitor increases when a negative voltage is applied between the other electrode and the one electrode of the capacitor.
- the refresh circuit further includes: a first field effect transistor, connected between one electrode of the capacitor and the data holding node, and having a gate electrode receiving a first drive potential; and a second field effect transistor having a first electrode receiving a second drive potential, having a second electrode connected to the data holding node, and having a gate electrode connected to one electrode of the capacitor.
- the second field effect transistor is made conductive to refresh a potential at the data holding node when a potential at the one electrode of the capacitor exceeds a prescribed potential in response to a refresh signal, while the second field effect transistor does not made conductive to refresh no potential at the data holding node when a potential at the one electrode of the capacitor does not exceed a prescribed voltage in response to a refresh signal.
- the first drive potential is equal to a potential of the sum of the first potential and a threshold voltage of the first field effect transistor
- the second drive potential is equal to the first potential.
- An activation level of the refresh signal is equal to the first potential and a deactivation level thereof is equal to the second potential. In this case, a potential at the data holding node is refreshed to the first potential in response to transition of the second field effect transistor to a conductive state.
- the refresh circuit further includes a third field effect transistor, interposed between a node at the second drive potential and the first electrode of the second field effect transistor, having a gate electrode receiving the refresh signal.
- reduction is enabled in a leakage current from the node at the second drive potential to the data holding node.
- the first drive potential is equal to a potential of the sum of the first potential and the threshold voltage of the first field effect transistor
- the second drive potential is equal to the first potential.
- the activation level of the refresh signal is equal to a potential of the sum of the first potential and the threshold voltage of the third field effect transistor, and the deactivation thereof is equal to the second potential.
- a potential at the data holding node is refreshed to the first potential in response to transition of the second and third field effect transistors to a conductive state. Voltage drop in the third field effect transistor can be prevented from occurring.
- the second drive potential is applied only during a prescribed period including a period in which the refresh signal is set at the activation level. In this case, more reduction is enabled in leakage current from the node at the second drive potential to the data holding node.
- the refresh circuit further includes: a third field effect transistor, interposed between the node at the second drive potential and the first electrode of the second field effect transistor, having a gate electrode receiving a control signal in synchronism with the refresh signal.
- a third field effect transistor interposed between the node at the second drive potential and the first electrode of the second field effect transistor, having a gate electrode receiving a control signal in synchronism with the refresh signal.
- reduction is enabled in a leakage current from the node at the second drive potential to the data holding node.
- the first drive potential is equal to a potential of the sum of the first potential and the threshold voltage of the first field effect transistor
- the second drive potential is equal to the first potential.
- the activation level of the refresh signal is equal to the first potential and the deactivation level thereof is equal to a potential obtained by level shifting the second potential to the first potential side by a predetermined first voltage.
- the activation level of the control signal is equal to a potential of the sum of the first potential and a threshold voltage of the third field effect transistor, and the deactivation level thereof is equal to a potential obtained by level shifting the second potential to the side opposed to the first potential side by a predetermined second voltage.
- a potential at the data holding node is refreshed to the first potential in response to transition of the second and third field effect transistors to a conductive state.
- a change in potential at the data holding node can be suppressed to be small in the case where a potential at the data holding node is not refreshed.
- the second drive potential is applied only during a prescribed period including a period in which the refresh signal and the control signal are set at the activation levels. In this case, more reduction is enabled in leakage current from the node at the second drive potential to the data holding node.
- a capacitor connected between the data holding node and a node at a reference potential.
- a potential at the data holding node is maintained by the capacitor, a change becomes smaller in potential at the data holding node.
- the pixel display circuit includes a liquid crystal cell having one electrode connected to the data holding node, having the other electrode receiving a drive potential, and a light transmittance of which varies according to a potential at the data holding node.
- a pixel density varies according to a light transmittance of the liquid crystal cell.
- the pixel display circuit includes: a field effect transistor having a gate electrode connected to the data holding node, and having a first electrode receiving the reference potential; and a liquid crystal cell having one electrode connected to a second electrode of the field effect transistor, having the other electrode receiving a drive potential, and a light transmittance of which varies according to a conductive state/non-conductive state of the field effect transistor.
- the field effect transistor is brought into the conductive or non-conductive state according to whether or not a potential at the data holding node exceeds a threshold voltage of the field effect transistor to thereby cause a light transmittance of the liquid crystal cell to be the maximum or minimum.
- the pixel display circuit includes: a field effect transistor having a gate electrode connected to the data holding node, and having a first electrode receiving a first drive voltage; a switch circuit applying a second drive potential to a prescribed node in response to a reset signal, and connecting a second electrode of the field effect transistor to the prescribed node in response to a set signal; and a liquid crystal cell having one electrode connected to the prescribed node, having the other electrode receiving a reference potential, and a light transmittance of which varies according to a potential at the prescribed node.
- a reset signal and a set signal are alternately inputted to thereby enable the prescribed node to take the first or second drive potential, which makes it possible to adjust a light transmittance of the liquid cell to the maximum or the minimum.
- the pixel display circuit includes: a field effect transistor having a gate electrode connected to the data holding node; and a light emitting element, connected in series with the field effect transistor between a node at a drive potential and a node at a reference potential, and a light intensity of which varies according to a current flowing in the field effect transistor.
- a pixel density varies according to a light intensity of the light emitting element.
- a plurality of pixel display circuits arranged in a plurality of rows and a plurality of columns
- the data write circuit includes: a plurality of scan lines provided correspondingly to the plurality of rows, respectively; a plurality of data signal lines provided correspondingly to the plurality of columns, respectively; field effect transistors, provided correspondingly to the respective pixel display circuits, each connected between the data holding node of a corresponding pixel display circuit and a corresponding data signal line, and each having a gate electrode connected to a corresponding scan line; a vertical scan circuit sequentially selecting the plurality of scan lines to drive a selected scan line to a select level and to cause a field effect transistor corresponding to the selected scan line to be made conductive; and a horizontal scan circuit sequentially selecting the plurality of data signal lines while one scan line is selected by the vertical scan circuit to apply one of the first and second potentials onto a data line selected according to the image signal.
- an image in two dimensions can be displayed.
- FIG. 1 is a circuit block diagram showing an overall configuration of a color liquid crystal display according to Embodiment 1 of the present invention.
- FIG. 2 is a circuit diagram showing a configuration of a liquid crystal drive circuit provided correspondingly to each liquid crystal cell shown in FIG. 1 .
- FIG. 3 is a sectional view showing a construction of a capacitor 25 shown in FIG. 2 .
- FIG. 4 is a timing chart for describing an operation of the liquid crystal drive circuit shown in FIG. 2 .
- FIG. 5 is another timing chart for describing an operation of the liquid crystal drive circuit shown in FIG. 2 .
- FIG. 6 is a circuit diagram showing a modification example of Embodiment 1.
- FIG. 7 is a sectional diagram showing a configuration of a capacitor 37 shown in FIG. 6 .
- FIG. 8 is a circuit diagram showing a main part of a color liquid crystal display according to Embodiment 2 of the present invention.
- FIG. 9 is a timing chart for describing an operation of the liquid crystal drive circuit shown in FIG. 8 .
- FIG. 10 is a circuit diagram showing a modification example of Embodiment 2.
- FIG. 11 is a timing chart for describing an operation of a liquid crystal drive circuit shown in FIG. 10 .
- FIG. 12 is a circuit diagram showing another modification example of Embodiment 2.
- FIG. 13 is a timing chart for describing an operation of a liquid crystal drive circuit shown in FIG. 12 .
- FIG. 14 is a circuit diagram showing a main part of a color liquid crystal display according to Embodiment 3 of the present invention.
- FIG. 15 is a circuit diagram showing a main part of a color liquid crystal display according to Embodiment 4 of the present invention.
- FIG. 16 is a circuit diagram showing a main part of an image display according to Embodiment 5 of the present invention.
- FIG. 17 is a circuit diagram showing a main part of a conventional liquid crystal display.
- FIG. 18 is a timing chart for describing a problem in the conventional liquid crystal display.
- FIG. 1 is a circuit block diagram showing an overall configuration of a color liquid crystal display according to Embodiment 1 of the present invention.
- color liquid crystal display 1 includes a liquid crystal panel 2 , a vertical scan circuit 8 and a horizontal scan circuit 11 , and is driven by a power supply potential VDD and a ground voltage VSS applied externally.
- Liquid crystal panel 2 includes: a plurality of liquid crystal cells 3 arranged in a plurality of rows and a plurality of columns; scan lines 5 and common potential lines 6 provided correspondingly to respective rows; and data signal lines 7 provided correspondingly to respective columns.
- Liquid crystal cells 3 are grouped into sets of three cells in each row in advance.
- the three liquid crystal cells 2 of each set are provided with color filters for R, G and B, respectively.
- the three liquid crystal cells 3 of each set constitute one pixel 4 .
- a common potential VC is externally applied onto common potential lines 6 .
- a refresh signal REF and drive potentials V 1 , V 2 and V 3 are externally applied to liquid crystal panel 2 .
- Vertical scan circuit 8 includes a shift register circuit 9 and a buffer circuit 10 .
- Shift register circuit 9 generates a signal for sequentially selecting a plurality of scan lines 5 of liquid crystal panel 2 in synchronism with a horizontal and vertical synchronous signal SN 1 supplied externally.
- Buffer circuit 10 buffers an output signal of shift register circuit 9 to supply the resulting signal to selected scan line 5 . Therefore, the plurality of scan lines 5 of liquid crystal panel 2 are sequentially driven to “H” level at select level for a prescribed time on each scan line 5 . When scan line 5 is driven to “H” level at select level, pixels 4 corresponding to scan line 5 are activated.
- Horizontal scan circuit 11 includes a shift register circuit 12 , a buffer circuit 14 and a plurality of switches 14 .
- the plurality of switches 14 are provided correspondingly to a plurality of data signal lines 7 , respectively, and are grouped into sets of three switches corresponding to respective sets of liquid crystal cells 2 in advance.
- One electrodes of three switches of each set receive data signals DR, DG and DB for R, G and B, respectively, and the other electrodes thereof are connected to corresponding three data signal lines 7 , respectively.
- Shift register circuit 12 generates a signal sequentially selecting a plurality of switch sets in synchronism with horizontal synchronous signal SN 2 supplied externally for a prescribed time to each switch set.
- Buffer circuit 10 buffers an output signal of shift register circuit 12 to supply the resulting signal to the control terminals of switches 14 of a selected set and to cause switches 14 to be made conductive. Therefore, data signals DR, DG and DB are sequentially supplied to the plurality of pixels 4 in a selected row.
- liquid crystal panel 2 When all pixels 4 of liquid crystal panel 2 are scanned by vertical scan circuit 8 and horizontal scan circuit 11 , one image is displayed on liquid crystal panel 2 .
- FIG. 2 is a circuit diagram showing a configuration of a liquid crystal drive circuit 20 provided correspondingly to each liquid crystal cell 3 .
- liquid crystal drive circuit 20 includes enhanced N-type TFTs 21 to 24 and capacitors 25 and 26 , and not only is connected to corresponding liquid crystal cell 3 , scan line 5 , common potential line 6 and signal line 7 , but also receives refresh signal REF and drive potentials V 1 and V 2 .
- FIG. 2 there is shown liquid crystal drive circuit 20 corresponding to R of R, G and B.
- N-type TFT 21 is connected between corresponding data signal line 7 and data holding node N 21 , and the gate thereof is connected to corresponding scan line 5 .
- Capacitor 26 is connected between data holding node N 21 and common potential line 6 .
- N-type TFT 24 is connected between one electrode of corresponding liquid crystal cell 3 and common potential line 6 , and the gate thereof is connected to data holding node N 21 .
- the other electrode of liquid crystal cell 3 receives a drive voltage V3.
- N-type TFT 21 When scan line 5 is driven to “H” level at select level, N-type TFT 21 is made conductive, and data holding node N 21 is charged at a potential on data signal line 7 . When scan line 5 is driven to “L” level at non-select level, N-type TFT 21 is made non-conductive, and a potential at data holding node N 21 is held by capacitor 26 .
- N-type TFT 24 When data holding node N 21 is at “H” level, N-type TFT 24 is made conductive, a drive voltage V 3 ⁇ VC is applied between electrodes of liquid crystal cell 3 , and a light transmittance of liquid crystal cell 3 is maximized, for example.
- N-type TFT 24 When data holding node N 21 is at “L” level, N-type TFT 24 is made non-conductive, no drive voltage is applied between electrodes of liquid crystal cell 3 , and a light transmittance of liquid crystal cell 3 is minimized, for example.
- N-type TFTs 22 and 23 and capacitor 25 constitute a refresh circuit.
- N-type TFT 22 is connected between a node N 22 and data holding node N 21 , and the gate thereof receives drive potential V 2 .
- Drive potential V 2 is set to a potential VH+VTN obtained by adding a threshold voltage VTN of N-type TFT to “H” level VH of data signal DR. Therefore, no voltage drop occurs due to threshold voltage VTN of N-type TFT 22 to cause potentials at nodes N 21 and N 22 to be equal to each other.
- N-type TFT 23 receives drive potential V 1 , the source thereof is connected to data holding node N 21 , and the gate thereof is connected to node N 22 .
- N-type TFT 23 is non-conductive.
- Capacitor 25 is a capacitor of an N-type TFT (of an enhancement type) structure, the gate thereof is connected to node N 22 , and the source thereof receives refresh signal REF.
- a gate to source voltage of capacitor 25 is higher than threshold voltage VTN of N-type TFT, capacitor 25 has a prescribed capacitance value.
- capacitor 25 has a considerably small capacitance value only corresponding to a parasitic capacitance.
- FIG. 3 is a sectional view showing a configuration of capacitor 25 .
- an intrinsic polysilicon film 31 is formed in a prescribed region on a surface of a glass substrate 30 .
- a gate insulating film 32 is formed so as to cover part of intrinsic polysilicon film 31 and, further, a gate electrode 33 is laminated on gate insulating film 32 .
- N-type impurity is injected into portion which is not covered by gate insulating film 32 and gate electrode 32 on intrinsic polysilicon film 31 to form a source region 31 s.
- an interlayer insulating film 34 is formed so as to cover all the region, a contact hole CH 1 is opened from a surface of interlayer insulating film 34 to a surface of gate electrode 33 , and a contact hole CH 2 is opened from the surface of interlayer insulating film 34 to a surface of source region 31 s.
- aluminum electrodes 35 and 36 are formed so as to fill and cover contact holes CH 1 and CH 2 .
- Aluminum electrode 35 (gate) is connected to node N 22
- aluminum electrode (source) 36 receives refresh signal REF.
- N-type TFT When a voltage higher than threshold voltage VTN of N-type TFT is applied between the gate and source, an N-type channel layer is formed on a surface of intrinsic polysilicon film 31 below gate electrode 33 to generate prescribed capacitance value between the gate and source.
- a configuration may be adopted in which not only is a gate electrode formed in the central portion on the surface of the intrinsic polysilicon film with a gate insulating film interposed therebetween in a similar way to the case of an ordinary TFT, but impurity is also injected at both sides of the gate electrode to form a source region and a drain region and, in addition, not only is the gate electrode connected to one aluminum electrode, but the source region and the drain region are connected commonly to the other aluminum electrode to form a capacitor.
- FIG. 4 is a timing chart for describing an operation of liquid crystal drive circuit 20 in the case where data signal DR is at “H” level VH.
- potential V 5 on scan line 5 is set to “L” level
- data signal DR is set to “L” level VL
- nodes N 21 and N 22 are reset to “L” level VL
- refresh signal REF is set to “L” level.
- N-type TFT 21 is made conductive to raise nodes N 21 and N 22 from “L” level VL to “H” level VH.
- potential V 5 on scan line 5 is lowered to “L” level and, then, data signal DR is also lowered to “L” level.
- potential V 5 on scan line 5 is raised to “L” level
- N-type TFT 21 is made non-conductive to cause potentials at nodes N 21 and N 22 to be held by capacitor 26 .
- N-type TFT 24 is made conductive to apply drive voltage V 3 ⁇ VC between electrodes of liquid crystal cell 3 and to, for example, maximize a light transmittance of liquid crystal cell 3 .
- N-type TFT When liquid crystal cell is left in this state, potentials at nodes N 21 and N 22 are gradually lowered by leakage current.
- a potential at node N 21 is lowered to a value lower than threshold potential VTN of N-type TFT 24 , N-type TFT is made non-conductive to vary a light transmittance of liquid crystal cell 3 from the maximum to the minimum. Therefore, refresh of a data signal is performed at prescribed time t 2 before potentials at nodes N 21 and N 22 are lowered to a value lower than threshold potential VTN of N-type TFT 24 .
- FIG. 5 is a timing chart for showing an operation of liquid crystal drive circuit 20 in the case where data signal DR is at “L” level VL.
- data signal DR is fixed at “L” level VL. Therefore, at time t 1 , potential V5 on scan line 5 is raised to “H” level and kept there for a prescribed time and even if N-type TFT 21 is in a conductive state only for a prescribed time, nodes N 21 and N 22 are maintained as is at “L” level VL.
- Embodiment 1 since no necessity arises for driving scan line 5 and data signal line 7 at the time of refreshing a data signal, a refresh control can be implemented with ease. Furthermore, since no necessity arises for operating vertical scan circuit 8 and horizontal scan circuit 11 at the time of refreshing a data signal, power consumption can be reduced.
- capacitor 25 having an N-type TFT structure is replaced with a capacitor 37 having a P-type TFT (of a enhancement type) structure.
- Capacitor 37 is, as shown in FIG. 7 , of a structure in which N-type source region 31 s of capacitor 25 is replaced with a P-type source region 31 s'.
- the gate of capacitor 37 receives refresh signal REF and the source thereof is connected to node N 22 .
- FIG. 8 is a circuit diagram showing a configuration of a liquid crystal drive circuit 40 of a color liquid crystal display according to Embodiment 2 of the present invention, and the figure is to be compared with FIG. 2 .
- liquid crystal drive circuit 40 is different from liquid crystal drive circuit 20 of FIG. 2 in that N-type TFT 41 is added and that a refresh signal REF′ is supplied instead of refresh signal REF.
- the drain of N-type TFT 41 receives drive potential V 1 , the source thereof is connected to the drain (a node N 23 ) of N-type TFT 23 , and the gate thereof receives refresh signal REF′.
- Refresh signal REF′ is different from refresh signal REF in that “H” level of refresh signal REF′, as shown in FIG. 9 , is not VH, but a prescribed potential VH′ equal to or higher than VH+VTN.
- refresh signal REF′ When refresh signal REF′ is set to “H” level VH′, N-type TFT 41 is made conductive. At this time, since “H” level VH′ of refresh signal REF′ is set to VH+VTN or higher, no voltage drop occurs due to threshold voltage VTN of N-type TFT 41 .
- capacitor 25 of an N-type TFT structure is replaced with capacitor 37 of a P-type TFT structure shown in FIGS. 6 and 7 .
- refresh signal REF′ When refresh signal REF′ is raised from “L” level to “H” level in the case where data holding node N 21 is at “L” level, potentials at nodes N 21 and N 22 are somewhat raised due to a considerably small capacitance value of capacitor 25 . In order to cause a rise, at this time, in potentials at nodes N 21 and N 22 to be smaller, a necessity arises for minimize a capacitance value of capacitor 25 under conditions where an N-type channel layer is hard to be generated in intrinsic polysilicon film 31 of capacitor 25 . Therefore, a configuration may be adopted in which “L” level of refresh signal REF′ is set not to VL (0 V) but to a positive potential VL′ (for example 1 V) to thereby maintain a gate to source voltage of capacitor 25 at a negative voltage.
- refresh signal REF 1 is supplied to the drain of N-type TFT 41 of liquid crystal drive circuit 40 instead of drive potential V 1 .
- refresh signal REF 1 is kept at “H” level VH only during a period (from time t 2 to time t 3 ) when refresh signal REF′ is at “H” level VH and prescribed periods before and after the period (from time t 2 to time t 3 ) while being kept at “L” level VL during the other periods. Therefore, a leakage current flowing in N-type TFTs 23 and 41 can be smaller.
- capacitor 25 of an N-type TFT structure may be replaced with capacitor 37 of a P-type TFT structure shown in FIGS. 6 and 7 .
- the gate of N-type TFT 41 and the source of capacitor 25 of liquid crystal drive circuit 40 are disconnected, refresh signal REF′′ is supplied to the source of capacitor 25 , refresh signal REF 2 is supplied to the gate of N-type TFT 41 , and refresh signal REF 1 is supplied to the drain of N-type TFT 41 .
- ⁇ V 1 is 1 V. Under such a condition, a capacitance value of capacitor 25 in the case where nodes N 21 and N 22 are at “L” level can be smaller.
- ⁇ V 2 is 1 V.
- FIG. 14 is a circuit diagram showing a main part of a color liquid crystal display according to Embodiment 3 of the present invention, and the figure is to be compared with FIG. 2 .
- the color liquid crystal display is different from color liquid crystal display 1 of Embodiment 1 in that liquid crystal drive circuit 20 is replaced with a liquid crystal drive circuit 50 , that a set line 54 and a reset line 55 are added, and that a drive potential VC′ and a reference potential VLC are newly introduced.
- Set line 54 and reset line 55 are driven, for example, by a vertical scan circuit.
- Liquid crystal drive circuit 50 is constituted of liquid crystal drive circuit added with N-type TFTs 51 and 52 and a capacitor 53 .
- Capacitor 26 is connected between node N 21 and node N 24 .
- a potential at data holding node N 21 is maintained by capacitor 26 .
- N-type TFTs 24 and 51 are in series connected between node N 24 and a node 51 .
- the gate of N-type TFT 24 is connected to data holding node N 21 .
- the gate of N-type TFT 51 receives a set signal ST through set line 54 .
- N-type TFT 51 When set signal ST is at “L” level at non-select level, N-type TFT 51 is made non-conductive. When set signal ST is set to “H” level at select level, N-type TFT 51 is made conductive. When data holding node N 21 is at “L” level, N-type TFT 24 is made non-conductive and node 51 does not vary as is at drive potential V 3 . When data holding node N 21 is at “H” level, N-type TFT 24 is made conductive to set node N 51 to drive potential VC′.
- Capacitor 53 is connected between node N 51 and common potential line 6 .
- N-type TFT 52 When reset signal RST is at “L” level at non-select level, N-type TFT 52 is made non-conductive and a potential at node N 51 is maintained as it is. When reset signal RST is set to “H” level at select level, N-type TFT 52 is made conductive and node N 51 is reset to drive potential V 3 .
- a light transmittance of liquid crystal cell 3 takes, for example, the maximum value
- a light transmittance of liquid crystal cell 3 takes, for example, the minimum value.
- scan line 5 is set to “H” level at select level to cause N-type TFT 21 to be made conductive and to write a potential on data signal line 7 to data holding node N 21 .
- scan line 5 is set to “L” level at non-select level, N-type TFT 21 is made non-conductive to thereby, cause a potential at data holding node N 21 to be maintained by capacitor 26 .
- reset signal RST and set signal ST are sequentially set to “H” level for a prescribed time T 2 at intervals of a prescribed time T 1 (T 2 ⁇ T 1 ).
- T 2 ⁇ T 1 a prescribed time T 1
- node 51 is set to drive potential VC′ while when data holding node N 21 is at “L” level, node N 51 is reset to drive potential V 3 .
- Embodiment 3 as well, there can be obtained the same effect as in Embodiment 1.
- FIG. 15 is a circuit diagram showing a liquid crystal drive circuit 60 of a color liquid crystal display according to Embodiment 4 of the present invention, and the figure is to be compared with FIG. 2 .
- liquid crystal drive circuit 60 is different from liquid crystal drive circuit 20 of FIG. 2 in that N-type TFT 24 is deleted.
- One electrode of liquid crystal cell 3 is connected directly to data holding node N 21 .
- Embodiment 4 as well, there can be obtained the same effect as in Embodiment 1.
- FIG. 16 is a circuit diagram showing a main part of an image display according to Embodiment 5 of the present invention, and the figure is to be compared with FIG. 2 .
- the image display is different from color liquid crystal display 1 of Embodiment 1 in that liquid crystal 3 is replaced with an organic EL (electroluminescence) element 61 .
- Organic EL element 61 is connected between a node at power supply potential VDD and the drain of N-type TFT 24 of drive circuit 20 .
- N-type TFT 24 When data holding node N 21 is at “H” level, N-type TFT 24 is made conductive to cause a current to flow in organic EL element 61 and to cause organic EL element 61 to emit light. When data holding node N 21 is at “L” level, N-type TFT 24 is made non-conductive to cause no current to flow in organic EL element 61 and to cause organic EL element 61 to emit no light. A potential at data holding node N 21 is refreshed using N-type TFTs 22 and 23 , and capacitor 25 .
- Embodiment 5 as well, there can be obtained the same effect as in Embodiment 1.
- a display element of another kind may be used instead of organic EL element 61 .
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PCT/JP2002/000991 WO2003067316A1 (fr) | 2002-02-06 | 2002-02-06 | Unite d'affichage d'image |
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US20040066360A1 US20040066360A1 (en) | 2004-04-08 |
US7145543B2 true US7145543B2 (en) | 2006-12-05 |
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US10/450,148 Expired - Lifetime US7145543B2 (en) | 2002-02-06 | 2002-02-06 | Image display unit |
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US (1) | US7145543B2 (ja) |
JP (1) | JP4334353B2 (ja) |
KR (1) | KR100572746B1 (ja) |
CN (1) | CN1325966C (ja) |
TW (1) | TW546606B (ja) |
WO (1) | WO2003067316A1 (ja) |
Cited By (2)
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US20040246214A1 (en) * | 2003-05-19 | 2004-12-09 | Au Optronics Corp. | Liquid crystal display and sampling circuit therefor |
US20080136983A1 (en) * | 2006-12-12 | 2008-06-12 | Industrial Technology Research Institute | Pixel structure of display device and method for driving the same |
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KR100778514B1 (ko) * | 2006-08-09 | 2007-11-22 | 삼성에스디아이 주식회사 | 유기 발광 표시 장치 |
JP4821029B2 (ja) * | 2009-01-09 | 2011-11-24 | 奇美電子股▲ふん▼有限公司 | アクティブマトリクス型ディスプレイ装置及びこれを備える電子機器 |
WO2011027598A1 (ja) * | 2009-09-07 | 2011-03-10 | シャープ株式会社 | 画素回路及び表示装置 |
US8717273B2 (en) | 2009-09-16 | 2014-05-06 | Sharp Kabushiki Kaisha | Liquid crystal display device and drive method for liquid crystal display device |
EP2479607A4 (en) * | 2009-09-16 | 2013-03-20 | Sharp Kk | MEMORY DEVICE, DISPLAY DEVICE WITH THE MEMORY DEVICE, DRIVE PROCEDURE FOR THE MEMORY DEVICE AND DRIVE SYSTEM FOR THE DISPLAY DEVICE |
JP5351975B2 (ja) * | 2009-11-06 | 2013-11-27 | シャープ株式会社 | 画素回路及び表示装置 |
JP5452616B2 (ja) * | 2009-12-10 | 2014-03-26 | シャープ株式会社 | 画素回路及び表示装置 |
CN102376239B (zh) * | 2010-08-25 | 2013-12-18 | 立景光电股份有限公司 | 显示装置的像素电路 |
US20130021320A1 (en) * | 2011-07-18 | 2013-01-24 | Chimei Innolux Corporation | Pixel element, display panel thereof, and control method thereof |
CN103927981B (zh) * | 2014-03-24 | 2016-05-18 | 京东方科技集团股份有限公司 | 像素电路及其驱动方法、显示装置 |
CN109410885A (zh) * | 2018-12-27 | 2019-03-01 | 信利半导体有限公司 | 扫描驱动电路、像素阵列基板及显示面板 |
CN111261122A (zh) * | 2020-02-27 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | 蓝相液晶像素电路、其驱动方法及显示装置 |
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- 2002-02-06 US US10/450,148 patent/US7145543B2/en not_active Expired - Lifetime
- 2002-02-06 JP JP2003566609A patent/JP4334353B2/ja not_active Expired - Fee Related
- 2002-02-06 KR KR1020037012998A patent/KR100572746B1/ko active IP Right Grant
- 2002-02-06 CN CNB028033612A patent/CN1325966C/zh not_active Expired - Fee Related
- 2002-03-05 TW TW091103998A patent/TW546606B/zh not_active IP Right Cessation
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US20080136983A1 (en) * | 2006-12-12 | 2008-06-12 | Industrial Technology Research Institute | Pixel structure of display device and method for driving the same |
Also Published As
Publication number | Publication date |
---|---|
CN1325966C (zh) | 2007-07-11 |
JPWO2003067316A1 (ja) | 2005-06-02 |
KR20040000419A (ko) | 2004-01-03 |
KR100572746B1 (ko) | 2006-04-24 |
TW546606B (en) | 2003-08-11 |
JP4334353B2 (ja) | 2009-09-30 |
US20040066360A1 (en) | 2004-04-08 |
WO2003067316A1 (fr) | 2003-08-14 |
CN1479883A (zh) | 2004-03-03 |
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