US7017158B2 - Multi-processor system, data processing system, data processing method, and computer program - Google Patents

Multi-processor system, data processing system, data processing method, and computer program Download PDF

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US7017158B2
US7017158B2 US09/964,247 US96424701A US7017158B2 US 7017158 B2 US7017158 B2 US 7017158B2 US 96424701 A US96424701 A US 96424701A US 7017158 B2 US7017158 B2 US 7017158B2
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data
data processing
ones
processors
processing means
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Nobuo Sasaki
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Sony Interactive Entertainment Inc
Sony Network Entertainment Platform Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Definitions

  • the present invention relates to a data processing system that performs data processing by a plurality of data processing means, for example, a multi-processor system and a data processing method.
  • the data processing ability of multi-processor is determined, depending on the number of processors to be used and the processing method; and dependence on the high performance of individual processors is low. For this reason, this is one of useful means to improve the processing ability of data processing apparatus.
  • the data processing method using the multi-processor can be explained as follows if it is divided based on the range of data necessary when one processor performs data processing.
  • Such control is suitable for a cell automaton, image filter, calculation of cloth-wave like movement, calculation of polygon generation from a curved surface and the like.
  • the processor that performs data processing uses data processed by all processors.
  • Such control is suitable for an associative storage, optimization of four-color problem, traveling salesman problem and so on, radiosity, clustering, multiplexing link simulation, learning, etc.
  • the processor that performs data processing uses only data processed by some of a plurality of processors.
  • control is suitable for self-assembly calculation, group algorithm based on judgment using sense of vision, many-to-many collision determination, database search, calculation for generating/deforming continuous curved surface, born animation, inverse kinematics, etc.
  • It is an object of the present invention is to provide various kinds of multi-processor systems, a data processing system, a data processing method, a computer program, and a semiconductor device.
  • the present invention provides various kinds of multi-processor systems described below, a data processing system, a data processing method, a computer program, and a semiconductor device.
  • a first multi-processor system comprises a plurality of processors for performing data processing; and a controller for broadcasting broadcast data including data used in data processing to the plurality of processors, wherein each of the plurality of processors sorts out data necessary for data processing to be performed by each processor from the broadcast data broadcasted by the controller to perform data processing.
  • each of the plurality of processors sorts out only data that is necessary for each cell from broadcasted data and performs data processing, it is possible to implement high-speed processing without occurrence of a data conflict.
  • the controller obtains a result of processing from each of the plurality processors, and broadcasts the obtained result of processing to all processors as broadcast data.
  • each of the plurality of processors is assigned identification data for identifying the corresponding processor
  • the controller generates broadcast data where identification data of the processor as a result obtaining source is added to the result of processing and broadcasts the data. Accordingly, each processor can easily sort out the result of processing necessary for data processing that each processor should perform at next timing based on the identification data. Moreover, each processor can easily recognize from which processor the broadcasted processing result has been sent.
  • the multi-processor system further comprising a sort mechanism obtains the identification data from the processor that has finished data processing among the plurality of processors to send obtained identification data to the controller in a given sequence. Then, the controller is configured to obtain the result of processing based on identification data received from the sort mechanism. In this case, there is further provided means for generating priority data that fixes a reading sequence of the result of processing to be performed by the controller.
  • the processor that has finished data processing is configured to send the sort mechanism identification data of the processor and the priority data about the processing, the sort mechanism is configured to determine a sequence of sending the identification data based on the priority data,
  • the provision of sort mechanism allows the controller to obtain the processing result in the necessary sequence and efficiently execute the complicated processing as an entirety of system.
  • the sort mechanism includes the same number of registers as the processors, means for recording the identification data and identification data sent from the respective processors in the register relating to the corresponding processor, a comparator for performing a comparison between the priority data to determine sequence of identification data recorded in the respective registers.
  • the sort mechanism is configured to determine the sequence of sending the identification data based on the determination result of the comparator.
  • the controller in the multi-processor system includes, for example, memory for storing data, storage control means for obtaining the result of processing from the processor specified by the identification data received from the sort mechanism to store the obtained result in the memory, and data generating means for reading the result of processing stored in the memory to generate the broadcast data that includes the result of processing and the received indemnification data, whereby allowing the implement of the multi-processor system.
  • each of the plurality of processors more specifically includes a data processing mechanism for determining whether or not data necessary for data processing that is performed by each processor is included in the broadcast data to sort out only the data when the necessary data is included therein and perform data processing, means for sending the controller the result of data processing performed by the data processing mechanism and identification of each processor according to a request from the controller, and means for sending the sort mechanism process end notifying data including identification data of each processor when ending data processing, whereby allowing the implement of the multi-processor system.
  • a second multi-processor system comprising a plurality of processors for each holding template data to be compared with data to be input, a controller for broadcasting the input data to the plurality of processors, and a comparison mechanism for comparing the respective outputs of the plurality of processors.
  • Template data held by the plurality of processors is different from template data held by other processors, respectively.
  • Each of the plurality of processors calculates a differential value between the feature of the input data broadcasted by the controller and the feature of the template that is held by each processor and sends the comparison mechanism a pair of data including the calculated differential value and identification data for identifying each processor.
  • the comparison mechanism selects any one of differential values based on the differential values received from the respective processors and sends the controller identification data paired with the selected differential value.
  • the controller specifies one processor from the plurality of processors based on the identification data received from the comparison mechanism.
  • the above-configured multi-processor system can perform judgment of similarity of data at high-speed.
  • a third multi-processor system comprises a plurality of processors for performing data processing, a controller for broadcasting data used in data processing to the plurality of processors, and a sum circuit for calculating the sum of results of data processing performed by the plurality of processors.
  • Each of the plurality of processors sorts out only data necessary for processing from the data broadcasted by the controller to perform data processing and sends the result of processing to the sum circuit.
  • the sum circuit calculates the sum of the results of processing sent from the respective processors and sends the calculation result to the controller.
  • the controller broadcasts the sum of the results of processing received from the sum circuit to the plurality of processors.
  • the sum of the data processing results is often needed to normalize the calculation in connection with an optimization calculation used in such as a neurocomputer.
  • the calculated sum may be broadcasted to each processor.
  • the above-configured multi-processor system can perform these processing at high-speed.
  • At least some of the plurality of processors are connected to each other in a ring format via common memory, and are configured such that transmission/reception of data between the processors connected in a ring format is performed via the common memory.
  • the data processing method provided by the present invention is the method, which is executed by an apparatus or a system having a plurality of data processing means each which performs data processing, and control means for controlling an operation of each of the plurality of data processing means, the method comprising the steps of obtaining a result of data processing in a given order in which data processing was performed by each of the plurality of processors to generate broadcast data including the obtained result of processing and identification data for identifying data processing means as a processing result obtaining source and broadcast the broadcast data to the plurality of data processing means, wherein the step is performed by the control means; and selecting only some of the processing results specified based on the identification data from broadcast data received by the control means to perform data processing and send the control means the result of processing and identification data indicating each data processing means, wherein the step is performed by at least one of the plurality of data processing means.
  • the first data processing system comprises a plurality of data processing means for performing data processing, and control means for broadcasting broadcast data including results of data processing received from some or all of the plurality of data processing means and data used in data processing performed by at least one of the data processing means, wherein each of the plurality of data processing means sorts out only data necessary for data processing to be performed by each data processing means from the broadcast data broadcasted by the control means to perform data processing and sends the processing result to the control means.
  • the second data processing system is one that performs two-way communication between a plurality of data processing means that performs data processing, the data processing system comprising means for specifying at least one the data processing means to generate broadcast data including identification information of the specified data processing means and data processing data directed to the data processing means, means for obtaining a result of data processing performed by the corresponding data processing means from some or all of the plurality of data processing means, and means for including the processing result received in the broadcast data to broadcast the broadcast data to each of the plurality of data processing means.
  • the computer program provided by the present invention is one for causing an apparatus having a computer that performs two-way communication between a plurality of data processing means that performs data processing to form the following functions (1) to (3) and the semiconductor device provided by the present invention is one that is incorporated into an apparatus having a computer that performs two-way communication between a plurality of data processing means that performs data processing, whereby causing the computer to form the following functions (1) to (3).
  • FIG. 1 is a view illustrating the configuration example of multi-processor system to which the present invention is applied;
  • FIG. 2 is a view illustrating the configuration example of a BCMC according to the present invention.
  • FIG. 3 is a view illustrating the configuration example of a cell processor according to the present invention.
  • FIG. 4 is a view illustrating the configuration example of a WTA/sum circuit according to the present invention.
  • FIG. 5 is a flowchart illustrating the flow of processing that is executed by the multi-processor system according to the present embodiment
  • FIG. 6 is a conceptual view using the result of data processing of an adjacent processor according to the present invention.
  • FIG. 7 is a conceptual view using the result of data processing of some processors according to the present invention.
  • FIG. 8 is a view illustrating a case in which lattice point data is grouped according to the present invention.
  • FIG. 9 is a view illustrating a case in which objects are divided into clusters according to the present invention.
  • FIG. 10 is a flowchart illustrating the flow of processing of a collision determination algorithm according to the present invention.
  • FIG. 1 is a view illustrating the configuration example of multi-processor system.
  • This multi-processor system 1 includes a broadcast memory controller 10 (hereinafter referred to as BCMC), which is control means for data processing and data recording and reading, a plurality of cell processors 20 as one example of each data processing means, a plurality of WTA (Winner Take All)/sum circuits 30 for forming various kinds of functions required for data processing.
  • BCMC broadcast memory controller 10
  • WTA Winner Take All
  • BCMC and all processors 20 are connected via a broadcast channel (communication channel that can disseminate information to several recipients simultaneously).
  • a broadcast channel communication channel that can disseminate information to several recipients simultaneously.
  • This multi-processor system 1 manages a status variable value, which is the result of data processing obtained by each cell processor 20 , using BCMC 10 , and sends the status variable values of all cell processors 20 from BCMC 10 through the broadcast as one example of reference numeric values. This makes it possible for each cell processor 20 to refer to the status variable values generated by other cell processors 20 at high speed.
  • the broadcast channel is a transmission path formed between BCMC 10 and the plurality of cell processors 20 , and includes an address bus that is used to transfer addresses and a data bus that is used to transfer data such as status variable values.
  • the address includes a cell address for specifying each cell processor 20 and a broadcast address for all cell processors 20 .
  • the cell address corresponds to an address (physical address or logical address) on memory, and the status variable value sent from the cell processor 20 is designed to be placed into memory at an address corresponding to a cell address indicative of each cell processor 20 .
  • Each processor 20 is provided with ID (identification) as identification information for identifying each cell processor.
  • ID identification
  • the cell address also corresponds to ID. The use of cell address makes it possible to specify from which cell processor 20 the status variable value is output.
  • the WTA/sum circuits 30 are connected as illustrated in FIG. 1 . Namely, the WTA/sum circuits 30 are connected in a pyramidal shape where the side of the cell processors 20 is set as a first stage. Two cell processors 20 are connected to the input terminals of the respective WTA/sum circuits 30 of the first stage, and their output terminals are connected to the input terminals of the WTA/sum circuits 30 of the second stage.
  • the outputs of two WTA/sum circuits 30 of the lower stage are connected to the respective input terminals, and the input terminal of the WTA/sum circuits 30 of the upper stage is connected to the output terminal of the lower stage.
  • the outputs of two WTA/sum circuits 30 of the lower stage are connected to the input terminals of the WTA/sum circuit 30 of the uppermost stage, and the output terminal of the WTA/sum circuit 30 of the uppermost stage is connected to BCMC 10 .
  • the prevent invention can be carried out by cascading the WTA/sum circuits 30 .
  • two cell processors 20 are connected to the input of the WAT/sum circuit 30 of the first stage, and its output terminal is connected to the input terminal of the upper stage.
  • the output terminals of the WTA/sum circuits 30 of the lower stage and the cell processors are connected to the input terminals of the WTA/sum circuits 30 of the second stage and afterward.
  • the output terminals of the WTA/sum circuits 30 of the second stage and afterward are connected to the input terminal of the upper stage.
  • the input terminal of the WTA/sum circuit 30 of the uppermost stage is connected to the output terminal of the WTA circuit 30 of the lower stage and the cell processor 20 , and the output terminal of the WTA/sum circuit 30 of the uppermost stage is connected to the BCMC 10 .
  • BCMC 10 broadcasts data to all cell processors 20 through the broadcast channel, and fetches the status variable values from the respective cell processors 20 and holds them.
  • a configuration example of BCMC 10 is illustrated in FIG. 2 .
  • the BCMC 10 includes a CPU core 101 that controls the entire operation of the multi-processor system 1 , main memory 102 that can rewrite SRAM (Static Random Access Memory), and a DMAC (Direct Memory Access Controller) 103 and they are connected to one another by a bus B 1 .
  • the CPU core 101 is a semiconductor device including a computer having a function for performing the characteristic data processing of the present invention by reading a given computer program in cooperation with main memory 102 to execute the program.
  • the main memory 102 is used as memory common to the entire system.
  • the output terminal of the WTA/sum circuit 30 of the, uppermost stage and outer memory such as hard disk, transportable media, and like are also connected to the bus B 1 .
  • the CPU core 101 reads a startup program from the external memory at an initiating time, and executes the startup program to operate an operating system. It also reads various kinds of data necessary for data processing from the external memory and expands it to the main memory 102 . Data such as a status variable value of each cell processors 20 is designed to be stored in the main memory 102 . The status variable value is placed into the main memory at the address corresponding to the cell address of the cell processor 20 that has calculated the corresponding status variable value.
  • the CPU core 101 generates broadcast data to be broadcasted to each cell processor 20 based on data read from the main memory 102 .
  • the broadcast data is a pair of data having a status variable value and a cell address indicating the cell processor 20 that has calculated the corresponding status variable value. In this case, one or a plurality of pairs of data is generated.
  • the DMAC 103 is a semiconductor device that performs direct memory access transfer control between the main memory 102 and each cell processor 20 .
  • the TDMAC 103 broadcasts broadcast data to each cell processor 20 via the broadcast channel. It also obtains the results of data processing of the respective cell processors 20 individually and writes them to the main memory 102 .
  • Each cell processor 20 sorts out necessary data from broadcast data and performs data processing, and reports the result to the WTA/sum circuit 30 at the time of ending data processing.
  • Each cell processor 20 sends the status variable value, which is the result of data processing, to the BCMC 10 in accordance with an instruction from the BCMC 10 .
  • the respective cell processors 20 are connected to each other in a ring format via the common memory (not shown).
  • Each cell processor 20 may perform data processing on a synchronous clock. Also, each cell processor 20 may perform data processing on a different clock.
  • FIG. 3 shows the configuration example of the cell processor 20 .
  • the cell processor 20 is composed of a cell CPU 201 , an input buffer 202 , an output buffer 203 , a WTA buffer 204 , a program controller 205 , instruction memory 206 , and data memory 207 .
  • the cell CPU 201 is a processor that has a programmable floating-point calculator and controls the operation of each cell processor to perform data processing.
  • the cell CPU 201 obtains broadcast data subjected to broadcasting from the BCMC 10 via the input buffer 202 . Then, the cell CPU 201 determines whether or not obtained broadcast data is data necessary for processing that the cell CPU 201 should perform using the cell address of pair data.
  • the cell CPU 201 writes the status variable value to the corresponding address of data memory 207 , if necessary.
  • the cell CPU 201 reads the status variable value from the data memory 207 and performs data processing. Then, the cell CPU 201 writes the result of data processing to the output buffer 203 , and sends data, which indicated the end of data processing, to the WTA/sum circuit 30 .
  • the input buffer 202 is one that holds broadcast data subjected to broadcasting from the BCMC 10 . Broadcast data held is sent to the cell CPU 201 in response to a request sent from the cell CPU 201 .
  • the output buffer 203 is one that holds the status variable value of the cell CPU 201 .
  • the status variable value held is sent to the BCMC 10 in response to a request from the BCMC 10 .
  • the input buffer 202 and output buffer 203 may perform transmission and reception of data for control.
  • the WTA buffer 204 receives data, which indicates the end of data processing, from the cell CPU 201 at the time of ending data processing performed by the cell CPU 201 . Then, the WTA buffer 204 transmits the received data to the WTA/sum circuit 30 to report the end of data processing thereto.
  • Data, indicative of end of data processing includes, for example, ID of its cell processor 20 , and priority data that determines priority, which is necessary when the status variable value stored in the output buffer 203 is read to the BCMC 10 .
  • the program controller 205 is one that fetches a program for defining the operation of the cell processor 20 from the BCMC 10 .
  • the program for defining the operation of the cell processor 20 includes a program for data processing executed by the cell processor 20 , a data selective program for determining data necessary for processing executed by each cell processor 20 .
  • the program also includes a priority deciding program for deciding priority, which is necessary when the result of processing is read to the BCMC 10 .
  • the instruction memory 206 stores the program fetched by the program controller 205 .
  • the stored program is read to the cell CPU 201 as required.
  • the data memory 207 is one that stores data processed by the cell processor 20 .
  • the broadcast data determined as being necessary by the cell CPU 201 is written therein.
  • the broadcast data is stored into the data memory 207 at the address corresponding to the cell address.
  • a part of the data memory 207 is connected to the cell processors 20 adjacent to each other via the common memory to make it possible to transmit/receive data to/from the adjacent cell processors for each cycle.
  • the plurality of WTA/sum circuits 30 determines the order in which the BCMC 10 captures the status variable value from the cell processor 20 based on data, indicative of the end of data processing sent from each cell processor 20 , and reports it to the BCMC 10 .
  • FIG. 4 illustrates the configuration example of the WTA/sum circuit 30 .
  • Each WTA/sum circuit 30 is composed of two input registers A and B (hereinafter referred to first input register 301 and second input register 302 ), a selector switch 303 , a comparator 304 , an adder 305 , and an output register 306 .
  • Each of the first input register 301 and the second input register 302 has an integer register and a floating-point register.
  • ID data is written into the integer register
  • priority data is written into the floating-point register.
  • the selector switch 303 energizes either the comparator 304 or the adder 305 . More specifically, the selector switch 303 makes it possible to use only one of them in accordance with an operation mode.
  • the operation mode is determined by an instruction from, e.g., the BCMC 10 . The operation mode will be described later.
  • the comparator 304 perform's the comparison of the floating-point values, which are held by the floating-point registers of the first input register 301 and second input register 302 .
  • the comparator 304 writes a larger (or smaller) value and an integer attendant thereon to the output register 306 .
  • the adder 305 calculates the sum of the floating-point values, which are held by the floating-point registers of the first input register 301 and second input register 302 , and writes the result of calculation to the output register 306 .
  • the output register 306 is configured in substantially the same way as the fist input register 301 and the second input register 302 . Namely, the output register 306 comprises the integer register and the floating-point register. ID data is written to the integer register and priority data is written to the floating-point register.
  • the WTA/sum circuit 30 has three operation modes set forth below.
  • the comparator 304 is energized by the selector switch 303 .
  • the comparator 304 performs the comparison of the floating-point values A and B, which are held by the floating-point registers of the first input register 301 and second input register 302 .
  • the comparator 304 writes a larger (or smaller) value and an integer attendant thereon to the output register 306 .
  • the first input register 301 and the second input register 302 are cleared.
  • the content of the output register 306 is written to the input register of the WTA/sum circuit 30 of the upper stage. At this time, if the input register as a writing destination is not cleared, the writing is stalled and no writing is performed at this cycle. For this reason, the content of the output register 306 is designed to be written at a next cycle.
  • the adder 305 is energized by the selector switch 303 .
  • the adder 305 calculates the sum of the floating-point values A and B, which are held by the floating-point registers of the first input register 301 and second input register 302 .
  • the adder 305 writes the calculation result to the output register 306 .
  • the content of the output register 306 is written to the input register of the WTA/sum circuit 30 of the upper stage.
  • the comparator 304 is energized by the selector switch 303 .
  • the comparator 304 performs the comparison of the floating-point values A and B, which are held by the floating-point registers of the first input register 301 and second input register 302 .
  • the comparator 304 writes a larger (or smaller) value and an integer attendant thereon to the output register 306 .
  • first input registers 301 , second input registers 302 , and output registers 306 of all WTA/sum circuits 30 are cleared before entering each mode.
  • the change in each mode implements the function as a mechanism for sorting (sorting mechanism) and/or sum circuit in connection with the entirety of the plurality of WTA/sum circuits.
  • sorting mechanism mechanism for sorting
  • sum circuit in connection with the entirety of the plurality of WTA/sum circuits.
  • the WTA/sum circuit 30 that operates in each of the maximum value mode and the approximate sort mode may be realized as follows:
  • WTA/sum circuit 30 is composed of the same number of input registers as that of the cell processors 20 , a selector switch, comparator 304 , adder 305 , and output register.
  • the number of input registers as that of the cell processors 20 is prepared, and each includes an integer register and a floating-point register similar to the first register 301 and second register 302 .
  • the comparator performs the comparison of the floating-point values, which are held by the floating-point registers of all input registers.
  • the adder calculates the sum of the floating-point values, which are held by all floating-point registers.
  • the output register is the same as the output register of the WTA/sum 30 of FIG. 4 .
  • the comparator compares priority data that is held by the floating-point registers of the respective input registers and writes appurtenant IDs to the output register in decreasing order of priority, sequentially. This makes it possible to send IDs to the BCMC 10 in decreasing order of priority.
  • the adder adds data that is held by the floating-point registers to obtain the total sum.
  • Such one WTA/sum circuit functions as the sorting mechanism and sum circuit of the present invention instead of adopting the connection form as illustrated in FIG. 1 .
  • FIG. 5 is a flowchart illustrating the flow of processing that is executed by this multi-processor system 1 .
  • initial values of status variable values of all cell processors 20 are stored in advance.
  • BCMC 10 produces broadcast data using a pair of data including the status variable value of each cell processor 20 and the cell address of each cell processor 20 (step S 101 ). Then, BCMC 10 broadcasts produced broadcast data to all cell processors 20 (step S 102 ).
  • Each cell processor 20 fetches broadcast data to the input buffer 202 .
  • the cell CPU 201 checks the cell address of broadcast data held by the input buffer 202 according to a data selection program stored in the instruction memory 206 , and confirms whether or not there is a status variable value that is needed when each cell processor 20 performs data processing (step S 103 ). In the case where there is no status variable value that is needed when each cell processor 20 performs data processing, the cell processor 20 ends the processing operation (step S 103 : NO).
  • step S 104 the cell processor 20 performs the overwriting of the corresponding status variable value at the address on the data memory 207 corresponding to the cell address paired with this status variable value (step S 104 ).
  • each cell processor 20 When the broadcasting is ended, each cell processor 20 provides data processing to the status variable value recorded on the data memory 207 to produce a new status variable value according to the program of data processing stored in the instruction memory 206 .
  • the new status variable value is written to the data memory 207 , and is written to the output buffer 203 , too (step S 105 ). Then, each cell processor 20 performs the overwriting of the new status variable value at the address on the data memory 207 corresponding to its cell address.
  • the cell CPU 201 transmits end data including ID and priority data to the input register of the WTA/sum circuit 30 of the first stage via the WTA buffer 204 , and reports the end of data processing (step S 106 ).
  • Priority data is generated according to a given priority deciding program before or after data processing.
  • the WTA/sum circuit 30 of the first stage holds ID by use of the integer registers of input register and priority data by use of the floating-point registers, respectively.
  • the WTA/sum circuit 30 operates in the approximate sort mode. For this reason, the selector switch 303 energizes the comparator 304 .
  • the integer registers of the first input register 301 and second input register 302 of WTA/sum circuit 30 hold IDs sent from the different processors. Each of the floating-point registers holds priority data attendant on ID.
  • the comparator 304 reads priority data from the floating-point registers of the first input register 301 and the second input register 302 , and compares them. As a result of comparison, the comparator 304 writes higher priority data and IDs attendant thereon to the floating-point register of the output register 306 and the integer register. Regarding the input registers whose contents are written to the output register 306 , the contents are cleared. Regarding IDs and priority data written to the output register 306 , they are written to the input registers of the WTA/sum circuit 30 of the upper stage.
  • the aforementioned processing is performed at the WTA/sum circuits of the respective stages.
  • the TWA/sum circuit 30 of the uppermost stage sends ID written to the inter register of the output register 306 to BCMC 10 .
  • the WTA/sum circuits 30 as a whole send IDs to the BCMC 10 in order of decreasing the priority by the aforementioned processing (step S 107 ).
  • the BCMC 10 obtains a status variable value subjected to data processing from the output buffer 203 of the cell processor 20 corresponding to ID sent from the WTA/sum circuit 30 .
  • the overwriting of the obtained status variable value is performed at the address corresponding to the cell address indicating the cell processor 20 that has performed processing (step S 108 ).
  • the BCMC 10 obtains the result of data processing from each cell processor 20 , thus generating broadcast data.
  • Each cell processor 20 sorts out only data necessary for each cell processor 20 from broadcast data to perform data processing. Data processing using such broadcast data makes it possible to perform processing using data processed by all other cell processors 20 . Moreover, the BCMC 10 generates broadcast data using the pair of data having the result of data processing sent from each cell processor 20 and the cell address indicative of the cell processor 20 that has generated the result of data processing. This makes it possible to perform processing using only the result of data processing sent from the specific cell processor 20 . Moreover, since the adjacent cell processor 20 are connected to each other via the common memory, it is possible to perform processing between the adjacent cell processors 20 , similar to the prior art.
  • Each cell processor 20 sorts out necessary data from broadcast data without fetching data necessary for each cell processor 20 to the main memory 102 directly, and performs processing as holding data therein, allowing high-speed processing without occurrence of a data conflict.
  • This embodiment explains an example using only data processed by a certain cell processor 20 and other cell processors 20 adjacent thereto with reference to FIG. 6 .
  • ⁇ represents cell processors and a shaded “ ⁇ ” indicates a cell processor that performs data processing, and “ ⁇ ” denotes cell processors that hold necessary data.
  • BCMC 10 broadcasts lattice point data, which is grouped in a row or column as broadcast data, to n cell processors 20 .
  • FIG. 8 is a view illustrating lattice data, which is grouped.
  • Lattice point data indicated by “ ⁇ ” is illustrated in groups of five.
  • Lattice point data in one group is processed by one cell processor 20 .
  • the cell processor 20 stores necessary lattice point data grouped from broadcast data in the data memory 207 . Then, it reads lattice point data from the data memory 207 sequentially and performs data processing. Data transfer between the cell processors 20 connected via the common memory is performed using the common memory. If data writing operation to the common memory is one cycle, transfer of grouped data between the cell processors 20 can be carried out in 2 n cycles.
  • the respective cell processors 20 are synchronously operated to execute the writing to the common memory and the calculation simultaneously as in pipeline processing, making it possible to perform communication between the cell processors and the calculation at the same time.
  • the BCMC 10 broadcasts next broadcast data each time when data processing of grouped lattice data is ended.
  • the cell processor 20 judges whether or not data processing should be carried out based on data I and j to be broadcasted.
  • Broadcast data is grouped to make it possible to process data in a row or column direction, and data transfer is performed via common data, allowing data processing in a row or column direction.
  • This embodiment explains an example using only data processed by some of all cell processors 20 with reference to FIG. 7 .
  • “ ⁇ ” represents cell processors and a shaded “ ⁇ ” indicates a cell processor that performs data processing, and “ ⁇ ” denotes cell processors that hold necessary data.
  • Such a multi-processor system is useful to realize hop field associative storage.
  • each cell processor 20 holds a status variable value, which is the result of data processing, and a weighting factor indicative of significance of the status variable data. Moreover, a number is added to each of the cell processors 20 , and the BCMC 10 fetches the status variable values from all cell processors 20 in order of the number.
  • the BCMC 10 broadcasts the status variable values fetched from all cell processors 20 as broadcast data.
  • Each cell processor 20 selects only necessary status variable value from broadcast data and performs product-sum operation with respect to the weighting factor and updates the status variable value. In the case where necessary status variable value indicates all status variable values included in broadcast data, this corresponds to processing using data processed by all processors.
  • processing for specifying the cell processor 20 that holds data which is similar to the feature of input data most, is performed. This processing is carried out as follows:
  • Each cell processor 20 holds template data to be compared beforehand.
  • the BCMC 10 broadcasts input data to all cell processors 20 .
  • Each processor 20 calculates a differential value between the feature of template data held by each cell processor 20 and the feature of input data.
  • the differential value is sent to the WTA/sum circuit 30 with ID.
  • the WTA/sum circuit 30 operates in the maximum value mode.
  • the integer register of input register holds ID
  • the floating-point register holds the differential value.
  • the comparator 304 compares the differential values calculated by the respective cell processors 20 , and sends a smaller differential value and ID attendant thereon to the output register 306 . This processing is carried out through the entire WTA/sum circuits 30 to obtain the smallest differential value and ID attendant thereon. The obtained ID and differential value are sent to the BCMC 10 .
  • the BCMC 10 specifies the cell processor 20 based on ID. This make it possible to detect template data which is similar to the feature of the input data most, and to detect the differential value between the template data and the input data.
  • collision determination algorithm is one that determines whether or not n objects existing in a certain space collide with other objects and how much degree of strength is generated when collision occurs.
  • n objects there are some variations in the spatial distribution of n objects, and the objects are divided into m clusters. Here, for example, it is assumed that determination of whether one object collides with any one of other (n-1) objects most strongly is performed.
  • FIG. 9 is a view illustrating the objects in such a space, and objects expressed by “ ⁇ ” are enclosed with a rectangle to form one cluster.
  • the objects are divided into five clusters.
  • Data indicative of objects is broadcasted from the BCMC 10 , and fetched to the cell processor 20 on a cluster-by-cluster basis.
  • the cell processor 20 performs processing about the position and movement in the space in connection with the fetched objects included in one cluster.
  • cell processors A to E perform processing of objects divided into five clusters.
  • the BCMC 10 generates broadcast data including object data having data of object position and velocity and cluster data indicative of a cluster to which the corresponding object belongs, and broadcasts them to all cell processors 20 (step S 201 ).
  • Each cell processor 20 sorts out object data from broadcast data based on cluster data and fetches it.
  • the cell processor 20 that has fetched object data calculates new positional data from current positional data of the object and velocity data after a unit of time.
  • the cell processor 20 obtains a value of a new bounding box from new positional data (step S 202 ).
  • the bounding box means a rectangle that encloses the objects as in, for example, FIG. 9 .
  • the value of bounding box is coordinates of the vertex of the bounding box.
  • the BCMC 10 fetches new positional data of objects from each cell processor 20 and updates positional data (step S 203 ).
  • the BCMC 10 broadcasts object data including obtained new positional data and so on to all cell processors 20 one by one (step S 204 ). Namely, the BCMC 10 sends positional data, which indicates the position of one object as a target to be subjected to collision determination (hereinafter referred to as “determining objects”), to all cell processors 20 .
  • Each cell processor 20 first determines whether or not there is a possibility that collision of determination object will occur using the bounding box calculated by step S 202 (step S 205 ). More specifically, the cell processor 20 determines whether or not the position of the determining object is present in the bounding box.
  • the cell processor 20 calculates the distance between the respective objects in the bounding box to be processed sequentially (step S 206 ) to determine the occurrence of collision (step S 207 ). In the case where the determining object collides with any one of objects in the bounding box (step S 207 . YES), the cell processor 20 generates collision data including data (collision strength data), which quantitatively indicates the strength of impact caused by collision, and data, which indicates influence upon the determining object caused by collision (step S 208 ). Moreover, the cell processor 20 sends collision strength data among generated collision data to the WTA/sum circuit 30 together with its ID (step S 209 ).
  • each cell processor 20 sends, for example, “ ⁇ 1, 0” as collision strength data to the WTA/sum circuit 30 (step S 210 ).
  • the WTA/sum circuit 30 operates in the maximum value mode.
  • the WTA/sum circuit 30 performs comparison between collision strength data sent from the cell processors 20 , and detects collision strength data, which indicates the highest strength of impact of impact caused by collision (step S 211 ). Then, the WTA/sum circuit 30 specifies the cell processor 20 that has generated collision strength data detected. After that, the WTA/sum circuit 30 sends ID, which indicates the specified cell processor 20 , to the BCMC 10 .
  • the BCMC 10 obtains collision data from the cell processor 20 , which is shown by ID sent from the uppermost stage of WTA/sum circuit 30 (step S 212 ). By providing processing after step 204 to all objects, determination of collision among all objects in the space is performed.
  • Each cell processor 20 inputs the result of data processing to the WTA/sum circuit 30 .
  • the adder 305 adds the result of data processing and resultantly obtains the sum of the results of data processing in connection with all cell processors 20 . In this way, the sum of the results of data processing can be obtained at high speed by the WTA/sum circuit 30 .
  • the sum of the results of data processing is sent to the BCMC 10 by which the sum can be transmitted to all cell processors 20 at high speed.
  • the sum of the results of data processing is used to normalize calculation in connection with an optimization calculation used in such as a neurocomputer.
  • WTA/sum circuit 30 may be incorporated into BCMC 10 to configure a controller as one block.
  • the following configuration may be possible.
  • two or more data processing terminals are connected in the form that two-way communication is possible via a wide-area network.
  • one or a plurality of data processing terminals is operated as control means and the others are operated as data processing means.
  • Control means is provided with a function of broadcasting broadcast data including the result of data processing received from some or all of the plurality of data processing means and data used for data processing executed by at least one data processing.
  • Each of the plurality of data processing means is provided with a function of sorting out only data necessary for data processing executed by each processing means from broadcast data broadcasted by control means to perform data processing and transmit the result of processing to control means.
  • a plurality of general-purpose data processing terminals which is capable of specifying predetermined identification information (for example, the aforementioned identification data), is used as a plurality of data processing means.
  • a data processing system may be configured by only a server, which is capable of performing two-way communication with these general-purpose data processing terminals, or an apparatus provided with a semiconductor device including a CPU and memory therein.
  • the CPU provided in its interior reads a given computer program and executes it.
  • This provides the following functions to the server main body or apparatus. Namely, the function is to specify at least one data processing terminal as data processing means to generate broadcast data including identification information of the specified data processing terminal and data processing data directed to the data processing terminal. Another function is to obtain the result of data processing executed by the corresponding data processing terminal from some or all of the plurality of data processing terminals. Still another function is to include the received result of processing in broadcast data and broadcast the corresponding broadcast data to each of the plurality of data processing terminals.
  • the above-mentioned present invention makes it possible to efficiently perform data processing among data processing means in the case of using the plurality of data processing means.

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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050027793A1 (en) * 2002-10-08 2005-02-03 Hass David T. Advanced processor with mechanism for packet distribution at high line rate
US20080216074A1 (en) * 2002-10-08 2008-09-04 Hass David T Advanced processor translation lookaside buffer management in a multithreaded system
US20100042785A1 (en) * 2002-10-08 2010-02-18 Hass David T Advanced processor with fast messaging network technology
US7870365B1 (en) 2008-07-07 2011-01-11 Ovics Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel
US7958341B1 (en) 2008-07-07 2011-06-07 Ovics Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory
US20110161978A1 (en) * 2009-12-28 2011-06-30 Samsung Electronics Co., Ltd. Job allocation method and apparatus for a multi-core system
US8131975B1 (en) 2008-07-07 2012-03-06 Ovics Matrix processor initialization systems and methods
US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
US8176298B2 (en) 2002-10-08 2012-05-08 Netlogic Microsystems, Inc. Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline
US8327114B1 (en) 2008-07-07 2012-12-04 Ovics Matrix processor proxy systems and methods
US20130081028A1 (en) * 2011-09-23 2013-03-28 Royce A. Levien Receiving discrete interface device subtask result data and acquiring task result data
US8478811B2 (en) 2002-10-08 2013-07-02 Netlogic Microsystems, Inc. Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip
US8788732B2 (en) 2002-10-08 2014-07-22 Netlogic Microsystems, Inc. Messaging network for processing data using multiple processor cores
US9088474B2 (en) 2002-10-08 2015-07-21 Broadcom Corporation Advanced processor with interfacing messaging network to a CPU
US9269063B2 (en) 2011-09-23 2016-02-23 Elwha Llc Acquiring and transmitting event related tasks and subtasks to interface devices
US9596324B2 (en) 2008-02-08 2017-03-14 Broadcom Corporation System and method for parsing and allocating a plurality of packets to processor core threads

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US6989843B2 (en) * 2000-06-29 2006-01-24 Sun Microsystems, Inc. Graphics system with an improved filtering adder tree
US20050120185A1 (en) * 2003-12-01 2005-06-02 Sony Computer Entertainment Inc. Methods and apparatus for efficient multi-tasking
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US7444525B2 (en) * 2005-05-25 2008-10-28 Sony Computer Entertainment Inc. Methods and apparatus for reducing leakage current in a disabled SOI circuit
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61283976A (ja) 1985-06-11 1986-12-13 Sanyo Electric Co Ltd パタ−ン認識装置
US4739476A (en) * 1985-08-01 1988-04-19 General Electric Company Local interconnection scheme for parallel processing architectures
JPH0247757A (ja) 1988-08-09 1990-02-16 Sanyo Electric Co Ltd 情報処理装置
JPH0281258A (ja) 1988-09-19 1990-03-22 Fujitsu Ltd 並列計算機
EP0360527A2 (en) 1988-09-19 1990-03-28 Fujitsu Limited Parallel computer system using a SIMD method
EP0411497A2 (en) 1989-07-31 1991-02-06 Hitachi, Ltd. Data processing system and data transmission and processing method
JPH0362255A (ja) 1989-07-31 1991-03-18 Hitachi Ltd データ伝送方式
JPH0784966A (ja) 1993-08-06 1995-03-31 Toshiba Corp データ処理装置
US5511212A (en) * 1993-06-10 1996-04-23 Rockoff; Todd E. Multi-clock SIMD computer and instruction-cache-enhancement thereof
US5805915A (en) * 1992-05-22 1998-09-08 International Business Machines Corporation SIMIMD array processing system
US6516403B1 (en) * 1999-04-28 2003-02-04 Nec Corporation System for synchronizing use of critical sections by multiple processors using the corresponding flag bits in the communication registers and access control register

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61283976A (ja) 1985-06-11 1986-12-13 Sanyo Electric Co Ltd パタ−ン認識装置
US4739476A (en) * 1985-08-01 1988-04-19 General Electric Company Local interconnection scheme for parallel processing architectures
JPH0247757A (ja) 1988-08-09 1990-02-16 Sanyo Electric Co Ltd 情報処理装置
JPH0281258A (ja) 1988-09-19 1990-03-22 Fujitsu Ltd 並列計算機
EP0360527A2 (en) 1988-09-19 1990-03-28 Fujitsu Limited Parallel computer system using a SIMD method
US5230057A (en) 1988-09-19 1993-07-20 Fujitsu Limited Simd system having logic units arranged in stages of tree structure and operation of stages controlled through respective control registers
JPH0362255A (ja) 1989-07-31 1991-03-18 Hitachi Ltd データ伝送方式
EP0411497A2 (en) 1989-07-31 1991-02-06 Hitachi, Ltd. Data processing system and data transmission and processing method
US5655079A (en) 1989-07-31 1997-08-05 Hitachi, Ltd. Data processing system and data transmission and processing method
US5805915A (en) * 1992-05-22 1998-09-08 International Business Machines Corporation SIMIMD array processing system
US5511212A (en) * 1993-06-10 1996-04-23 Rockoff; Todd E. Multi-clock SIMD computer and instruction-cache-enhancement thereof
JPH0784966A (ja) 1993-08-06 1995-03-31 Toshiba Corp データ処理装置
US6516403B1 (en) * 1999-04-28 2003-02-04 Nec Corporation System for synchronizing use of critical sections by multiple processors using the corresponding flag bits in the communication registers and access control register

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8788732B2 (en) 2002-10-08 2014-07-22 Netlogic Microsystems, Inc. Messaging network for processing data using multiple processor cores
US9088474B2 (en) 2002-10-08 2015-07-21 Broadcom Corporation Advanced processor with interfacing messaging network to a CPU
US8176298B2 (en) 2002-10-08 2012-05-08 Netlogic Microsystems, Inc. Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline
US9154443B2 (en) 2002-10-08 2015-10-06 Broadcom Corporation Advanced processor with fast messaging network technology
US9092360B2 (en) 2002-10-08 2015-07-28 Broadcom Corporation Advanced processor translation lookaside buffer management in a multithreaded system
US20080216074A1 (en) * 2002-10-08 2008-09-04 Hass David T Advanced processor translation lookaside buffer management in a multithreaded system
US7991977B2 (en) 2002-10-08 2011-08-02 Netlogic Microsystems, Inc. Advanced processor translation lookaside buffer management in a multithreaded system
US8015567B2 (en) * 2002-10-08 2011-09-06 Netlogic Microsystems, Inc. Advanced processor with mechanism for packet distribution at high line rate
US20050027793A1 (en) * 2002-10-08 2005-02-03 Hass David T. Advanced processor with mechanism for packet distribution at high line rate
US8499302B2 (en) 2002-10-08 2013-07-30 Netlogic Microsystems, Inc. Advanced processor with mechanism for packet distribution at high line rate
US20100042785A1 (en) * 2002-10-08 2010-02-18 Hass David T Advanced processor with fast messaging network technology
US8478811B2 (en) 2002-10-08 2013-07-02 Netlogic Microsystems, Inc. Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip
US9596324B2 (en) 2008-02-08 2017-03-14 Broadcom Corporation System and method for parsing and allocating a plurality of packets to processor core threads
US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
US8131975B1 (en) 2008-07-07 2012-03-06 Ovics Matrix processor initialization systems and methods
US7958341B1 (en) 2008-07-07 2011-06-07 Ovics Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory
US7870365B1 (en) 2008-07-07 2011-01-11 Ovics Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel
US9280513B1 (en) 2008-07-07 2016-03-08 Ovics Matrix processor proxy systems and methods
US8327114B1 (en) 2008-07-07 2012-12-04 Ovics Matrix processor proxy systems and methods
US20110161978A1 (en) * 2009-12-28 2011-06-30 Samsung Electronics Co., Ltd. Job allocation method and apparatus for a multi-core system
US9710768B2 (en) 2011-09-23 2017-07-18 Elwha Llc Acquiring and transmitting event related tasks and subtasks to interface devices
US20130081028A1 (en) * 2011-09-23 2013-03-28 Royce A. Levien Receiving discrete interface device subtask result data and acquiring task result data
US9269063B2 (en) 2011-09-23 2016-02-23 Elwha Llc Acquiring and transmitting event related tasks and subtasks to interface devices

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