US6836022B2 - High voltage flip-chip component package and method for forming the same - Google Patents
High voltage flip-chip component package and method for forming the same Download PDFInfo
- Publication number
- US6836022B2 US6836022B2 US10/365,765 US36576503A US6836022B2 US 6836022 B2 US6836022 B2 US 6836022B2 US 36576503 A US36576503 A US 36576503A US 6836022 B2 US6836022 B2 US 6836022B2
- Authority
- US
- United States
- Prior art keywords
- flip
- component
- chip package
- shield plane
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime, expires
Links
- 238000000034 method Methods 0.000 title description 11
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 230000005684 electric field Effects 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 230000010287 polarization Effects 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 description 14
- 229910000679 solder Inorganic materials 0.000 description 14
- 238000012858 packaging process Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052755 nonmetal Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Definitions
- the present invention generally relates to die packaging, and more particularly relates to a high-voltage flip-chip component package and a high-voltage flip-chip packaging process.
- Flip-chip technology is a semiconductor fabrication technology that allows the overall package size to be made very compact.
- the flip-chip package configuration differs from the conventional ones particularly in that it mounts the die in an upside-down manner over the chip carrier, or substrate, and electrically couples the die to the substrate by means of solder bumps provided on the active surface of the die. Since minimal or no bonding wires are required, which would otherwise occupy much layout space, the overall size of the flip-chip package can be made very compact as compared to conventional types of electronic packages.
- High voltage die refers to an electronic component or device that is operable with a potential greater than about 50 volts across any two electrical terminals or contacts of the component. Such high voltage components may be further operable at DC voltages greater than about 100 volts, and even further may be operable at DC voltages greater than about 500 volts, 1000 volts and even greater, perhaps as great as 1600 or more volts.
- High voltage die may include devices such as Field Effect Transistors (FETs), Metal Oxide Semiconductor (MOS) FETs (MOSFETs), Insulated Gate FETs (IGFETs), thyristors, bipolar transistors, diodes, MOS-controlled thyristors, resistors, capacitors, etc.
- FETs Field Effect Transistors
- MOS Metal Oxide Semiconductor
- IGFETs Insulated Gate FETs
- thyristors bipolar transistors
- diodes MOS-controlled thyristors
- resistors capacitors, etc.
- the underfill used in the flip-chip package may become polarized and/or ions in the underfill may be attracted to the high voltage die. Such phenomena may cause detrimental electrical performance changes, such as, for example, leakage current that can cause a device in the off-state to switch to the on-state.
- circuit traces formed within the substrate upon which the high-voltage die is mounted create electric fields. If the circuit traces are not routed deep enough within the substrate, the electric fields may be sufficiently close to the die and of sufficient strength to negatively influence the performance of the die.
- a flip-chip package comprising a substrate having at least one layer and a component flip-chip mounted to the substrate, the component having a field termination ring.
- the flip-chip package further comprises a shield plane interposed between the at least one layer of substrate and the field termination ring.
- a flip-chip packaging process comprises the steps of providing a substrate having at least one layer and providing a component having a field termination ring.
- the process further includes the steps of flip-chip mounting the component to the substrate and interposing a shield plane between the at least one layer of the substrate and the field termination ring.
- FIG. 1 is a cross-sectional view of a flip-chip package in accordance with an exemplary embodiment of the present invention
- FIG. 2 is a top view of shield plane formed on a substrate with phantom termination rings superimposed thereon;
- FIG. 3 is a flow chart of a flip-chip packaging process in accordance with an exemplary embodiment of the present invention.
- FIG. 1 illustrates an exemplary embodiment of the flip-chip component package 10 of the present invention, which is particularly beneficial in high voltage discrete die packages and other high voltage component packages, where “high voltage component” or “high voltage discrete die” is defined herein as a device that is operable with a potential greater than fifty (50) volts, preferably greater than one hundred (100) volts, more preferably greater than five hundred (500) volts, and even more preferably greater than one thousand (1000) or sixteen hundred (1600) volts.
- high voltage component or “high voltage discrete die” is defined herein as a device that is operable with a potential greater than fifty (50) volts, preferably greater than one hundred (100) volts, more preferably greater than five hundred (500) volts, and even more preferably greater than one thousand (1000) or sixteen hundred (1600) volts.
- high voltage component or “high voltage discrete die” is defined herein as a device that is operable with a potential greater than fifty (50) volt
- the component package or high voltage component package in accordance with the present invention may include any number of devices such as Field Effect Transistors (FETs), Metal Oxide Semiconductor (MOS) FETs (MOSFETs), Insulated Gate FETs (IGFETs), thyristors, bipolar transistors, diodes, MOS-controlled thyristors, resistors, capacitors, etc.
- FETs Field Effect Transistors
- MOS FETs Metal Oxide Semiconductor
- IGFETs Insulated Gate FETs
- thyristors bipolar transistors
- diodes diodes
- MOS-controlled thyristors resistors, capacitors, etc.
- Flip-chip component package 10 comprises a non-metal substrate 12 and a component, or die, 14 .
- Component 14 has a first surface 16 at which has been formed at least one field termination ring 18 .
- Field termination ring 18 may be formed on first surface 16 of component 14 using any method as is known in the semiconductor industry including but not limited to, diffusion, implantation, and the formation of moats.
- component 14 comprises a plurality of concentric field termination rings. Field termination rings are well known in the semiconductor industry and, accordingly, will not be described in detail here.
- Flip-chip component package 10 further comprises a shield plane 20 interposed between substrate 12 and component 14 .
- shield plane 20 is formed overlying substrate 12 .
- Shield plane 20 is formed of a conductive material, such as, for example, a metal.
- shield plane 20 is formed of copper. It will be appreciated that flip-chip component package 10 may comprise further active components or connections, such as conductive layer 24 overlying substrate 12 .
- Component 14 is “flip-chip mounted” onto substrate 12 . As illustrated in FIG. 1, component 14 is formed with a plurality of solder bumps 22 connected to active electrical terminal connections at first surface 16 . Each solder bump 22 is connected to a solder bonding pad 32 formed on substrate 12 .
- flip-chip component package 10 also may comprise a solder mask layer 26 , which may overlie shield plane 20 and may be patterned to define solderable areas, such as, for example, solder bonding pads 32 to which solder bumps 22 are connected.
- Flip-chip component package 10 further comprises an underfill material 28 .
- the underfill material 28 may comprise epoxy resin or any other material well known in the semiconductor industry.
- underfill material 28 may begin to approach its glass-transition temperature. Underfill material 28 may lose hardness, and the molecules may be free to move or rotate within the material. This may allow the underfill molecules to become polarized in the presence of a strong electric field. The mobility of free ionic contaminants in underfill material 28 also may be increased as the material softens as the temperature is increased. When component 14 is in the “off-state” and a voltage is applied across main electrical terminals, an electric field may develop across field termination ring 18 on the surface 16 of component 14 . An electric fringing field may extend from the surface of component 14 into underfill material 28 .
- underfill 28 may orient themselves as dictated by the direction and polarity of the electric fringing field. Any free ions may move through underfill material 28 as dictated by the polarity of their charge and the direction of the electric fringing field. The ions may then accumulate at the surface of component 14 if the electric fringing field is applied continuously at an elevated temperature.
- the additional electric field set up by polarization of underfill 28 or accumulation of ionic charge may have a negative effect on the performance of component 14 .
- the additional electric fields may terminate on charge carriers in component 14 and create an inversion layer at the surface of component 14 that may form a leakage path across field termination ring 18 . This may cause component 14 to gradually switch from the “off-state” to the “on-state.”
- Shield plane 20 is configured so that there is a dominant electric field between component 14 and shield plane 20 , rather than across field termination ring 18 .
- the field between component 14 and shield plane 20 may create polarization of underfill material 28 towards shield plane 20 . It also may attract ions towards shield plane 20 and away from the surface of component 14 , and generate a vertical electric field that promotes a light accumulation layer to form at the surface of component 14 . In this manner, the formation of the inversion layer at the surface of the substrate may be reduced or eliminated, and leakage current stability may be achieved.
- shield plane 20 is configured to receive a biasing voltage to produce the electric field between component 14 and shield plane 20 .
- the biasing voltage preferably has a magnitude at least as great as the magnitude of the biasing voltage applied to component 14 , the voltages having the same polarity.
- a positive biasing voltage is applied to shield plane 20 , the positive biasing voltage preferably having a magnitude at least as great as the magnitude of the most positive biasing voltage applied to component 14 .
- a negative biasing voltage is applied to shield plane 20 , the negative biasing voltage preferably having a magnitude at least as great as the magnitude of the most negative biasing voltage applied to component 14 .
- Shield plane 20 may be connected directly to a terminal of component 14 if the component has unidirectional blocking characteristics, such as MOSFETs and diodes. However, if component 14 has bidirectional blocking, such as a thyristor, the voltage on shield plane 20 should be switched. In either case, shield plane 20 should be biased with a polarity that promotes accumulation of majority carriers at the surface of the lightly doped surface region at the field termination ring 18 .
- shield plane 20 should be sufficiently close to field termination ring 18 so that the electric field between component 14 and shield plane 20 dominates.
- the height of the solder bumps 22 may be configured to provide the preferable maximum distance between field termination ring 18 and shield plane 20 .
- a 1000V MOSFET intended to operate at 80% rated voltage at 125° C. should have shield plane 20 within 50 to 200 ⁇ m from the field termination ring 18 .
- the minimum distance between shield plane 20 and component 14 is determined by the dielectric strength of the insulating layers between shield plane 20 and component 14 , such as, for example, underfill material 28 and solder mask layer 26 .
- shield plane 20 has a surface area that is at least the size of the surface area of field termination ring 18 .
- shield plane 20 may have a surface area of the total annular ring comprising the concentric termination rings.
- the surface area of shield plane 20 is coextensive with the surface area of field termination ring 18 .
- the surface area of shield plane 20 is coextensive with and extends beyond the surface area of field termination ring 18 to compensation for any misalignment of component 14 when it is mounted on substrate 12 . Referring to FIG.
- a plurality of concentric field termination rings 40 , 42 , 44 forming a total annular ring 50 are illustrated in phantom overlying substrate 12 .
- Shield plane 20 overlies substrate 12 .
- the surface area 46 of shield plane 20 (shown with diagonal lines) is at least the size of the surface area 48 of total annular ring 50 comprising termination rings 40 , 42 , 44 .
- surface area 46 of shield plane 20 is coextensive with the surface area 48 of the total annular ring of the field termination rings and also extends beyond surface area 48 .
- coextensive means that the boundaries or edges of the surface area of the field termination ring, or the total annular ring, align with the boundaries of the surface area of the shield plane or that the boundaries of the surface area of the shield plane extend beyond the boundaries of the field termination ring (or total annular ring, as the case may be).
- flip-chip component package 10 may further comprise a circuit trace 30 formed within substrate 12 .
- shield plane 20 if trace 30 has a strong potential and is in close proximity to surface 16 of component 14 , an inversion layer may form in component 14 due to the creation of a parasitic transistor between component 14 and substrate 12 .
- Shield plane 20 serves to terminate or reduce the effect of the electric fields created at circuit trace 30 so that it cannot detrimentally influence the performance of component 14 . Accordingly, it will be appreciated by those skilled in the art that shield plane 20 may be formed overlying substrate 12 or, alternatively, may be formed within substrate 12 as long as it is interposed between circuit trace 30 and component 14 .
- FIG. 3 illustrates a flip-chip package process in accordance with another exemplary embodiment of the invention.
- a non-metal substrate is provided at step 60 .
- the substrate may comprise one layer or a plurality of various layers, one or more of which may be a circuit trace.
- a plurality of solder bonding pads is formed on a surface of the substrate.
- the solder bonding pads can be either SMD (Solder Mask Defined) type or NSMD (Non-SMD) type, or mixed SMD-NSMD type. These types of bond pads are all well-known in the semiconductor industry, so description thereof will not be further detailed.
- a component having a field termination ring is provided at step 62 .
- a plurality of solder bumps is formed on a surface of the component.
- the component then is flip-chip mounted onto the substrate, as provided at step 64 .
- the component is mounted in an upside-down (flip chip) manner onto the substrate, with the solder bumps thereof being aligned respectively to the substrate-side bonding pads.
- a solder-reflow process is then performed to reflow the solder bumps over the substrate-side bonding pads.
- an underfill material then may be provided, which flows by capillary action into the gap between the component and the substrate.
- the flip-chip packaging process of the present invention further comprises interposing a shield plane between the at least one layer of the substrate and the field termination ring of the component, as provided at step 66 .
- the shield plane may overlie the substrate.
- the shield plane is disposed on the surface of the substrate before the component is flip-chip mounted onto the substrate.
- the shield plane may be formed within the substrate as the substrate is formed and may be interposed between the field termination ring and a circuit trace formed as a layer of the substrate. In this embodiment, the shield plane is interposed between the field termination ring and the circuit trace before the component is flip-chip mounted onto the substrate.
- a flip-chip package and a flip-chip packaging process that fully meets the needs set forth above.
- the package is compact and provides stable electrical characteristics, even at high temperatures.
- various embodiments of the invention have been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to such illustrative embodiments.
- the invention has been described for use with high voltage components, it will be appreciated that the invention may be used with any suitable electronic component.
- the field termination ring is described has having the shape of a “ring”, it will be appreciated that the field termination ring and any corresponding “total annular ring,” as used herein, may assume any shape that surrounds an internal active region.
Landscapes
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/365,765 US6836022B2 (en) | 2003-02-13 | 2003-02-13 | High voltage flip-chip component package and method for forming the same |
PCT/US2004/004040 WO2004075294A2 (fr) | 2003-02-13 | 2004-02-12 | Procede de conditionnement de composant retourne et composant retourne |
CA002516058A CA2516058A1 (fr) | 2003-02-13 | 2004-02-12 | Procede de conditionnement de composant retourne et composant retourne |
JP2006503506A JP4684220B2 (ja) | 2003-02-13 | 2004-02-12 | フリップチップパッケージング方法及びフリップチップパッケージ体 |
EP04710614.1A EP1599902B1 (fr) | 2003-02-13 | 2004-02-12 | Procede de conditionnement de composant retourne |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/365,765 US6836022B2 (en) | 2003-02-13 | 2003-02-13 | High voltage flip-chip component package and method for forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20040159956A1 US20040159956A1 (en) | 2004-08-19 |
US6836022B2 true US6836022B2 (en) | 2004-12-28 |
Family
ID=32849645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/365,765 Expired - Lifetime US6836022B2 (en) | 2003-02-13 | 2003-02-13 | High voltage flip-chip component package and method for forming the same |
Country Status (5)
Country | Link |
---|---|
US (1) | US6836022B2 (fr) |
EP (1) | EP1599902B1 (fr) |
JP (1) | JP4684220B2 (fr) |
CA (1) | CA2516058A1 (fr) |
WO (1) | WO2004075294A2 (fr) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040262033A1 (en) * | 2003-06-30 | 2004-12-30 | Siliconware Precision Industries Co., Ltd. | Printed circuit board and method for fabricating the same |
US20050082075A1 (en) * | 2003-10-15 | 2005-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling |
US20060131732A1 (en) * | 2004-12-16 | 2006-06-22 | Nah Chih K | Discrete electronic component arrangement including anchoring, thermally conductive pad |
US20080093115A1 (en) * | 2006-10-20 | 2008-04-24 | Industrial Technology Research Institute | Interposer, electrical package, and contact structure and fabricating method thereof |
US20100328021A1 (en) * | 2007-06-29 | 2010-12-30 | Koa Corporation | Resistor device |
WO2013048620A1 (fr) | 2011-09-30 | 2013-04-04 | Medtronic, Inc. | Conditionnement de plaquette reconstituée à puce active discrète à haute tension et plaque de champ intégrée pour la stabilité du courant de fuite à haute température |
US8664756B2 (en) | 2012-07-24 | 2014-03-04 | Medtronic, Inc. | Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8766426B2 (en) * | 2010-09-24 | 2014-07-01 | Stats Chippac Ltd. | Integrated circuit packaging system with warpage control and method of manufacture thereof |
US10224255B2 (en) * | 2016-06-14 | 2019-03-05 | Nxp Usa, Inc. | Shielded and packaged electronic devices, electronic assemblies, and methods |
US10497587B1 (en) * | 2018-06-13 | 2019-12-03 | Infineon Technologies Ag | Ion manipulation methods and related apparatuses and systems for semiconductor encapsulation materials |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05259217A (ja) | 1991-03-11 | 1993-10-08 | Nippon Mektron Ltd | 回路部品搭載用中間基板及びその製造法 |
WO1994018707A1 (fr) | 1993-02-04 | 1994-08-18 | Motorola, Inc. | Module de circuit integre thermoconducteur a blindage radioelectrique |
US5808878A (en) | 1995-03-16 | 1998-09-15 | Kabushiki Kaisha Toshiba | Circuit substrate shielding device |
US6103551A (en) | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
JP2001053092A (ja) | 1999-08-13 | 2001-02-23 | Japan Radio Co Ltd | パッケージ、デバイス及びその製造方法 |
WO2001015225A1 (fr) | 1999-08-25 | 2001-03-01 | Telefonaktiebolaget Lm Ericsson (Publ) | Drain thermique et ecran electromagnetique combines |
US6489669B2 (en) * | 2000-09-11 | 2002-12-03 | Rohm Co., Ltd. | Integrated circuit device |
US6521978B2 (en) * | 2000-01-24 | 2003-02-18 | Infineon Technologies Ag | Shielding device and electrical structural part having a shielding device |
US6720662B1 (en) * | 1999-11-04 | 2004-04-13 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure with a radiation noise shield |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3763550A (en) * | 1970-12-03 | 1973-10-09 | Gen Motors Corp | Geometry for a pnp silicon transistor with overlay contacts |
SE466078B (sv) * | 1990-04-20 | 1991-12-09 | Ericsson Telefon Ab L M | Anordning vid en skaerm hos en integrerad krets och foerfarande foer framstaellning av anordningen |
EP0460251B1 (fr) * | 1990-06-05 | 1998-11-18 | Siemens Aktiengesellschaft | Méthode de fabrication d'un MISFET de puissance |
DE19517975B4 (de) * | 1994-07-12 | 2007-02-08 | International Rectifier Corp., El Segundo | CMOS-Schaltungsplättchen mit Polysilizium-Feldringstruktur |
JP2940478B2 (ja) * | 1996-06-21 | 1999-08-25 | 日本電気株式会社 | シールド付き表面実装部品 |
JPH1027767A (ja) * | 1996-07-11 | 1998-01-27 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2001319934A (ja) * | 2000-05-10 | 2001-11-16 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP2002026178A (ja) * | 2000-07-04 | 2002-01-25 | Hitachi Ltd | 半導体装置及びその製造方法並びに電子装置 |
US6420208B1 (en) * | 2000-09-14 | 2002-07-16 | Motorola, Inc. | Method of forming an alternative ground contact for a semiconductor die |
JP2002171036A (ja) * | 2000-12-04 | 2002-06-14 | Olympus Optical Co Ltd | 多層基板 |
DE10060828B4 (de) * | 2000-12-07 | 2006-11-30 | Infineon Technologies Ag | Halbleiterbauelement in Drain-up-Konfiguration |
US6486534B1 (en) * | 2001-02-16 | 2002-11-26 | Ashvattha Semiconductor, Inc. | Integrated circuit die having an interference shield |
-
2003
- 2003-02-13 US US10/365,765 patent/US6836022B2/en not_active Expired - Lifetime
-
2004
- 2004-02-12 WO PCT/US2004/004040 patent/WO2004075294A2/fr active Application Filing
- 2004-02-12 EP EP04710614.1A patent/EP1599902B1/fr not_active Expired - Lifetime
- 2004-02-12 JP JP2006503506A patent/JP4684220B2/ja not_active Expired - Fee Related
- 2004-02-12 CA CA002516058A patent/CA2516058A1/fr not_active Abandoned
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05259217A (ja) | 1991-03-11 | 1993-10-08 | Nippon Mektron Ltd | 回路部品搭載用中間基板及びその製造法 |
WO1994018707A1 (fr) | 1993-02-04 | 1994-08-18 | Motorola, Inc. | Module de circuit integre thermoconducteur a blindage radioelectrique |
US5371404A (en) | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
US5808878A (en) | 1995-03-16 | 1998-09-15 | Kabushiki Kaisha Toshiba | Circuit substrate shielding device |
US6103551A (en) | 1996-03-06 | 2000-08-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor unit and method for manufacturing the same |
JP2001053092A (ja) | 1999-08-13 | 2001-02-23 | Japan Radio Co Ltd | パッケージ、デバイス及びその製造方法 |
WO2001015225A1 (fr) | 1999-08-25 | 2001-03-01 | Telefonaktiebolaget Lm Ericsson (Publ) | Drain thermique et ecran electromagnetique combines |
US6720662B1 (en) * | 1999-11-04 | 2004-04-13 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure with a radiation noise shield |
US6521978B2 (en) * | 2000-01-24 | 2003-02-18 | Infineon Technologies Ag | Shielding device and electrical structural part having a shielding device |
US6489669B2 (en) * | 2000-09-11 | 2002-12-03 | Rohm Co., Ltd. | Integrated circuit device |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040262033A1 (en) * | 2003-06-30 | 2004-12-30 | Siliconware Precision Industries Co., Ltd. | Printed circuit board and method for fabricating the same |
US7205485B2 (en) * | 2003-06-30 | 2007-04-17 | Siliconware Precision Industries Co., Ltd. | Printed circuit board and method for fabricating the same |
US20050082075A1 (en) * | 2003-10-15 | 2005-04-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling |
US6888063B1 (en) * | 2003-10-15 | 2005-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling |
US20060131732A1 (en) * | 2004-12-16 | 2006-06-22 | Nah Chih K | Discrete electronic component arrangement including anchoring, thermally conductive pad |
US7148554B2 (en) * | 2004-12-16 | 2006-12-12 | Delphi Technologies, Inc. | Discrete electronic component arrangement including anchoring, thermally conductive pad |
US20080093115A1 (en) * | 2006-10-20 | 2008-04-24 | Industrial Technology Research Institute | Interposer, electrical package, and contact structure and fabricating method thereof |
US7968799B2 (en) * | 2006-10-20 | 2011-06-28 | Industrial Technology Research Institute | Interposer, electrical package, and contact structure and fabricating method thereof |
US20100328021A1 (en) * | 2007-06-29 | 2010-12-30 | Koa Corporation | Resistor device |
US8149082B2 (en) * | 2007-06-29 | 2012-04-03 | Koa Corporation | Resistor device |
WO2013048620A1 (fr) | 2011-09-30 | 2013-04-04 | Medtronic, Inc. | Conditionnement de plaquette reconstituée à puce active discrète à haute tension et plaque de champ intégrée pour la stabilité du courant de fuite à haute température |
US8664756B2 (en) | 2012-07-24 | 2014-03-04 | Medtronic, Inc. | Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability |
Also Published As
Publication number | Publication date |
---|---|
WO2004075294A3 (fr) | 2005-02-10 |
JP2007524988A (ja) | 2007-08-30 |
WO2004075294A2 (fr) | 2004-09-02 |
EP1599902A2 (fr) | 2005-11-30 |
US20040159956A1 (en) | 2004-08-19 |
JP4684220B2 (ja) | 2011-05-18 |
EP1599902B1 (fr) | 2014-07-23 |
CA2516058A1 (fr) | 2004-09-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100616129B1 (ko) | 고 전력 mcm 패키지 | |
US7301235B2 (en) | Semiconductor device module with flip chip devices on a common lead frame | |
US8466561B2 (en) | Semiconductor module with a power semiconductor chip and a passive component and method for producing the same | |
US6991961B2 (en) | Method of forming a high-voltage/high-power die package | |
US9806029B2 (en) | Transistor arrangement with semiconductor chips between two substrates | |
US9177957B1 (en) | Embedded packaging device | |
CN111971793B (zh) | 半导体模块 | |
US6858922B2 (en) | Back-to-back connected power semiconductor device package | |
US6841865B2 (en) | Semiconductor device having clips for connecting to external elements | |
US6836022B2 (en) | High voltage flip-chip component package and method for forming the same | |
CN101388388A (zh) | 半导体装置 | |
CN111987053A (zh) | 封装结构 | |
CN113574668A (zh) | 半导体装置 | |
US9655265B2 (en) | Electronic module | |
US10848074B2 (en) | High voltage bridge rectifier | |
EP3297022B1 (fr) | Refroidissement côté supérieur pour dispositif gan de puissance | |
JP2011199039A (ja) | 半導体装置 | |
US20050275020A1 (en) | Method of forming active device on substrate and the substrate | |
KR102362565B1 (ko) | 고전압 브리지 정류기 | |
US20220399246A1 (en) | Electronic package and manufacturing method thereof | |
US20160379919A1 (en) | Electronic device and method of manufacturing the same | |
US20170005025A1 (en) | Electronic device and method of manufacturing the same | |
US12080692B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
US20240312936A1 (en) | Power semiconductor package including a passive electronic component and method for fabricating the same | |
US20150221588A1 (en) | Surface Mountable Power Components |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MEDTRONIC, INC., MINNESOTA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOONE, MARK R.;FENNER, ANDREAS A.;MILLA, JUAN G.;AND OTHERS;REEL/FRAME:014023/0961 Effective date: 20030414 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |