WO2004075294A3 - Procede de conditionnement de composant retourne et composant retourne - Google Patents

Procede de conditionnement de composant retourne et composant retourne Download PDF

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Publication number
WO2004075294A3
WO2004075294A3 PCT/US2004/004040 US2004004040W WO2004075294A3 WO 2004075294 A3 WO2004075294 A3 WO 2004075294A3 US 2004004040 W US2004004040 W US 2004004040W WO 2004075294 A3 WO2004075294 A3 WO 2004075294A3
Authority
WO
WIPO (PCT)
Prior art keywords
flip
chip component
packaging process
substrate
chip
Prior art date
Application number
PCT/US2004/004040
Other languages
English (en)
Other versions
WO2004075294A2 (fr
Inventor
Mark R Boone
Andreas A Fenner
Juan G Milla
Lary R Larson
Original Assignee
Medtronic Inc
Mark R Boone
Andreas A Fenner
Juan G Milla
Lary R Larson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Medtronic Inc, Mark R Boone, Andreas A Fenner, Juan G Milla, Lary R Larson filed Critical Medtronic Inc
Priority to JP2006503506A priority Critical patent/JP4684220B2/ja
Priority to EP04710614.1A priority patent/EP1599902B1/fr
Priority to CA002516058A priority patent/CA2516058A1/fr
Publication of WO2004075294A2 publication Critical patent/WO2004075294A2/fr
Publication of WO2004075294A3 publication Critical patent/WO2004075294A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Electromagnetism (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

L'invention concerne un conditionnement de composant retourné qui comprend un substrat présentant au moins une couche et un composant monté retourné sur le substrat, ce composant présentant un anneau de terminaison de champ. Ce conditionnement de composant retourné comprend en outre une surface de blindage interposée entre la ou les couches du substrat et ledit anneau de terminaison de champ.
PCT/US2004/004040 2003-02-13 2004-02-12 Procede de conditionnement de composant retourne et composant retourne WO2004075294A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2006503506A JP4684220B2 (ja) 2003-02-13 2004-02-12 フリップチップパッケージング方法及びフリップチップパッケージ体
EP04710614.1A EP1599902B1 (fr) 2003-02-13 2004-02-12 Procede de conditionnement de composant retourne
CA002516058A CA2516058A1 (fr) 2003-02-13 2004-02-12 Procede de conditionnement de composant retourne et composant retourne

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/365,765 2003-02-13
US10/365,765 US6836022B2 (en) 2003-02-13 2003-02-13 High voltage flip-chip component package and method for forming the same

Publications (2)

Publication Number Publication Date
WO2004075294A2 WO2004075294A2 (fr) 2004-09-02
WO2004075294A3 true WO2004075294A3 (fr) 2005-02-10

Family

ID=32849645

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/004040 WO2004075294A2 (fr) 2003-02-13 2004-02-12 Procede de conditionnement de composant retourne et composant retourne

Country Status (5)

Country Link
US (1) US6836022B2 (fr)
EP (1) EP1599902B1 (fr)
JP (1) JP4684220B2 (fr)
CA (1) CA2516058A1 (fr)
WO (1) WO2004075294A2 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI245597B (en) * 2003-06-30 2005-12-11 Siliconware Precision Industries Co Ltd Printed circuit boards and method for fabricating the same
US6888063B1 (en) * 2003-10-15 2005-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling
US7148554B2 (en) * 2004-12-16 2006-12-12 Delphi Technologies, Inc. Discrete electronic component arrangement including anchoring, thermally conductive pad
TWI322494B (en) * 2006-10-20 2010-03-21 Ind Tech Res Inst Electrical package, and contact structure and fabricating method thereof
JP5320612B2 (ja) * 2007-06-29 2013-10-23 コーア株式会社 抵抗器
US8766426B2 (en) * 2010-09-24 2014-07-01 Stats Chippac Ltd. Integrated circuit packaging system with warpage control and method of manufacture thereof
US8664756B2 (en) 2012-07-24 2014-03-04 Medtronic, Inc. Reconstituted wafer package with high voltage discrete active dice and integrated field plate for high temperature leakage current stability
EP2761653B1 (fr) 2011-09-30 2016-05-04 Medtronic Inc. Boîtier de plaquette reconstituée avec puce discrète à haute tension et plaque de champ intégrée pour la stabilité du courant de fuite à haute température
US10224255B2 (en) * 2016-06-14 2019-03-05 Nxp Usa, Inc. Shielded and packaged electronic devices, electronic assemblies, and methods
US10497587B1 (en) * 2018-06-13 2019-12-03 Infineon Technologies Ag Ion manipulation methods and related apparatuses and systems for semiconductor encapsulation materials

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3763550A (en) * 1970-12-03 1973-10-09 Gen Motors Corp Geometry for a pnp silicon transistor with overlay contacts
EP0453424A1 (fr) * 1990-04-20 1991-10-23 Telefonaktiebolaget L M Ericsson Circuit integré avec un dispositif blindage et procédé pour sa fabrication
US5087577A (en) * 1990-06-05 1992-02-11 Siemens Aktiengesellschaft Manufacturing method for a power misfet
US5686754A (en) * 1994-07-12 1997-11-11 International Rectifier Corporation Polysilicon field ring structure for power IC
DE10060828A1 (de) * 2000-12-07 2002-06-27 Infineon Technologies Ag Halbleiterbauelement in Drain-up-Konfiguration
US6420208B1 (en) * 2000-09-14 2002-07-16 Motorola, Inc. Method of forming an alternative ground contact for a semiconductor die

Family Cites Families (15)

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Publication number Priority date Publication date Assignee Title
JP2869587B2 (ja) 1991-03-11 1999-03-10 日本メクトロン株式会社 回路部品搭載用中間基板及びその製造法
US5371404A (en) 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
EP0732107A3 (fr) 1995-03-16 1997-05-07 Toshiba Kk Dispositif écran pour substrat de circuit
JP3409957B2 (ja) 1996-03-06 2003-05-26 松下電器産業株式会社 半導体ユニット及びその形成方法
JP2940478B2 (ja) * 1996-06-21 1999-08-25 日本電気株式会社 シールド付き表面実装部品
JPH1027767A (ja) * 1996-07-11 1998-01-27 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2001053092A (ja) 1999-08-13 2001-02-23 Japan Radio Co Ltd パッケージ、デバイス及びその製造方法
SE9902998L (sv) 1999-08-25 2001-02-26 Ericsson Telefon Ab L M Kylare
US6720662B1 (en) * 1999-11-04 2004-04-13 Rohm Co., Ltd. Semiconductor device of chip-on-chip structure with a radiation noise shield
DE10002852A1 (de) * 2000-01-24 2001-08-02 Infineon Technologies Ag Abschirmeinrichtung und elektrisches Bauteil mit einer Abschirmeinrichtung
JP2001319934A (ja) * 2000-05-10 2001-11-16 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2002026178A (ja) * 2000-07-04 2002-01-25 Hitachi Ltd 半導体装置及びその製造方法並びに電子装置
JP4497683B2 (ja) * 2000-09-11 2010-07-07 ローム株式会社 集積回路装置
JP2002171036A (ja) * 2000-12-04 2002-06-14 Olympus Optical Co Ltd 多層基板
US6486534B1 (en) * 2001-02-16 2002-11-26 Ashvattha Semiconductor, Inc. Integrated circuit die having an interference shield

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3763550A (en) * 1970-12-03 1973-10-09 Gen Motors Corp Geometry for a pnp silicon transistor with overlay contacts
EP0453424A1 (fr) * 1990-04-20 1991-10-23 Telefonaktiebolaget L M Ericsson Circuit integré avec un dispositif blindage et procédé pour sa fabrication
US5087577A (en) * 1990-06-05 1992-02-11 Siemens Aktiengesellschaft Manufacturing method for a power misfet
US5686754A (en) * 1994-07-12 1997-11-11 International Rectifier Corporation Polysilicon field ring structure for power IC
US6420208B1 (en) * 2000-09-14 2002-07-16 Motorola, Inc. Method of forming an alternative ground contact for a semiconductor die
DE10060828A1 (de) * 2000-12-07 2002-06-27 Infineon Technologies Ag Halbleiterbauelement in Drain-up-Konfiguration

Also Published As

Publication number Publication date
EP1599902B1 (fr) 2014-07-23
US6836022B2 (en) 2004-12-28
JP2007524988A (ja) 2007-08-30
WO2004075294A2 (fr) 2004-09-02
CA2516058A1 (fr) 2004-09-02
EP1599902A2 (fr) 2005-11-30
US20040159956A1 (en) 2004-08-19
JP4684220B2 (ja) 2011-05-18

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