US6503667B1 - Method for fabricating mask - Google Patents

Method for fabricating mask Download PDF

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US6503667B1
US6503667B1 US09/697,424 US69742400A US6503667B1 US 6503667 B1 US6503667 B1 US 6503667B1 US 69742400 A US69742400 A US 69742400A US 6503667 B1 US6503667 B1 US 6503667B1
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light
resist
pattern
film
region
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Shinji Kobayashi
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/80—Etching

Definitions

  • the present invention relates to a method for fabricating a mask.
  • a mask obtained by forming a chrome film as a light-shielding film in a certain configuration on a quartz substrate has been generally utilized.
  • the patterning of the chrome film is generally performed by a lithography step of applying a resist to the quartz substrate on which the chrome film has been formed and patterning the resist using an electron beam (hereinafter referred to as EB), and an etching step of patterning the chrome film using the patterned resist as a mask.
  • EB electron beam
  • the miniaturization of the mask has not been required very much.
  • a reduction projection aligner hereinafter referred to as a stepper
  • the pattern of the mask has been satisfactory in the order of 5 times or 10 times larger than a pattern to be formed on the wafer. Therefore the mask miniaturization has been less required.
  • wet etching is isotropic in general so that etching shift surely occurs. Further, if a film to be etched includes step difference or variation in film thickness, the resulting pattern configuration of the film will not be uniform. Therefore, in the wafer process, dry etching has been employed to inhibit the etching shift and the variation in the pattern configuration. On the other hand, since there is no step difference and variation in thickness on the mask substrate, it has not been necessary to deal with them in the mask fabrication.
  • the first reason is that the mask pattern size of 4 times larger than a pattern to be formed on the wafer is required because a scanner system is getting commonly used in the photolithography process instead of the conventionally utilized stepper system. All commercially available scanner systems form the resist pattern on a wafer by one-fourth reduction exposure. In short, reduction ratio of a mask is 4 times and it is smaller than a stepper system.
  • the second reason is that as the wafer is further miniaturized, a relationship between exposure light wavelength and patterning size is reversed and needs for a proximity exposure effect correction mask is increased.
  • an object e.g., a conductive film, an insulating film, a resist film
  • This adjustment requires extremely high resolution as compared with the prior art because a microscopic pattern that cannot be resolved on the wafer must be formed precisely on the mask. Accordingly, the miniaturization of the mask is an exigent objective.
  • forming the mask pattern by dry etching can improve the pattern configuration (edge roughness and sectional configuration) and the resolution of the microscopic pattern.
  • dry etching for fabricating the mask pattern generally utilizes a mixture gas of chlorine or dichloromethane and oxygen.
  • how to alleviate difference in etching rate depending on area to be etched is important to form a uniform and highly precise chrome mask pattern.
  • a resist pattern is formed on a chrome film which has been formed on a quartz substrate 40 and the chrome film is patterned into a chrome pattern 41 using the resist pattern as a mask.
  • the resist surrounding regions A, B and C are different in area, which varies the etching rate of the chrome film in each region.
  • the resulting chrome patterns vary in size.
  • FIG. 5 there is established a relationship among the width of space between the chrome pattern lines in the region A>the width of space between the chrome pattern lines in the region B>the width of space between the chrome pattern lines in the region C.
  • a difference between the space width of the chrome pattern lines in the region A and the space width of the chrome pattern lines in the region C is 0.02 ⁇ m. This is considered because molecules of the resist are decomposed through the etching and generate hydrogen ions, which inhibit the etching of the chrome film. Therefore, the more the resist exists around the chrome film to be etched, the greater the hydrogen ions occur, and as a result, the etching rate of the chrome film decreases.
  • the chrome film will have variation in width of the patterned lines in regions D, E and F due to the existence of the resist film 52 formed on the periphery of a unit cell (chip).
  • FIG. 6 there is established a relationship among the width of the patterned chrome line in the region D>the width of the line in the region E>the width of the patterned chrome line in the region F.
  • Japanese Unexamined Patent Publication No. Hei 8 (1996)-234410 proposes a method for inhibiting the difference in etching rate of the chrome film depending on the surrounding resist by providing on the chip periphery a dummy pattern for correcting the uniformity of the dry etching rate. According to this method, the size variation among the patterned chrome lines on regions E and F positioned near the chip periphery and the patterned chrome line on the region D in the chip center can be reduced. However, the variation depending on the layout of the pattern lines as shown in FIG. 5 cannot be reduced.
  • Japanese Unexamined Patent Publication No. Hei 9 (1997)-311432 proposes a method for forming a dummy pattern having almost the same width as that of the actual pattern in a semiconductor chip. According to the method, the difference in density of the pattern lines in the semiconductor chip is alleviated and thus the size variation of the resulting patterns can be reduced.
  • this method is intended for fabricating the semiconductor chips. For fabricating the mask, as shown in FIG. 6, the large resist film 52 remains in the chip periphery so that the size variation among the chrome pattern lines in the regions E and F near the periphery and the region D in the chip center cannot be reduced.
  • the concentration of the hydrogen ions inhibiting the chrome etching is controlled to be uniform on the mask surface by supplying the hydrogen ions to the etching gas. Accordingly the etching rate can be uniform on the entire surface, though the etching rate of the chrome film is lowered in total. Thus, the size variation in chrome pattern lines can be reduced.
  • the chrome pattern lines still vary in width even though the optimized etching gas is used.
  • the reason is considered that the positive resist pattern used to pattern the chrome film has not been uniformly formed. That is, in the lithography step using EB, a phenomenon called fogging occurs, in which electrons that once entered the resist film are reflected out, and reflected again on the EB optical system and then re-enter the resist film. Therefore, EB dosage is not uniformly formed depending on the configuration of the resist pattern to be obtained, and as a result, the variation of the resist pattern occurs. For example, in the case of forming a resist pattern corresponding to the chrome pattern shown in FIG. 5, the amount of electrons that re-enters the resist film due to the fogging increases in the region A surrounded by the large exposure area. Accordingly, the space width between the patterned resist lines increases as compared with that in the region B.
  • the size variation among the resist pattern lines caused by the fogging proceeds in the same direction as the variation of the chrome patterns caused by the etching. Therefore the reduction of the variation is quite difficult.
  • the present invention provides a method for fabricating a mask comprising the steps of: fabricating a light-shielding film on an entire surface of a substrate including an actual pattern region and an unoccupied region other than the actual pattern region; patterning the light-shielding film on the actual pattern region while leaving the light-shielding film on the unoccupied region; and removing the light-shielding film on the unoccupied region while leaving the patterned light-shielding film on the actual pattern region.
  • FIGS. 1 ( a ) to 1 ( f ) are sectional views of a major part for illustrating formation steps according to an embodiment of a method for fabricating a mask of the present invention
  • FIGS. 2 ( a ) to 2 ( f ) are views illustrating pattern data utilized for fabricating and removing a dummy pattern according to the method for fabricating the mask of the present invention
  • FIGS. 3 ( a ) and 3 ( b ) are plan views of a substrate and FIG. 3 ( c ) is a graph, both explaining evaluation of a mask obtained by the method for fabricating the mask of the present invention
  • FIGS. 4 ( a ) is a plan view of a substrate and FIG. 4 ( b ) is a graph, both explaining evaluation of a mask obtained by a comparative method to the method for fabricating the mask of the present invention
  • FIG. 5 is a plan view for illustrating a drawback of a conventional method for fabricating a mask
  • FIG. 6 is a plan view for illustrating a drawback of another conventional method for fabricating a mask.
  • FIG. 7 is a graph illustrating a relationship of variation in width of chrome pattern lines formed by conventional dry etching and the amount of added HCl gas.
  • a light-shielding film is formed on the entire surface of a semiconductor substrate having an actual pattern region and an unoccupied region other than the actual pattern region in the step (a).
  • the substrate utilizable in the present invention is not particularly limited as long as the substrate can transmit exposure light when it is subjected to photolithography as a mask substrate.
  • a quartz substrate can be used.
  • the thickness of the substrate may vary depending on the material used, but may be about 0.25 inches or more, for example.
  • the substrate includes at least an actual pattern region on which an actual pattern will be formed in a later step and an unoccupied region other than the actual pattern region.
  • the actual pattern in this context signifies a pattern finally provided on a finished mask.
  • the unoccupied region signifies in general a region in a unit cell on which the actual pattern is not formed.
  • the substrate may include, in addition to the above regions, a periphery region positioned around a field region of the substrate and regions between the cells to serve as dicing lines.
  • the light-shielding film formed on the entire surface of the substrate is not particularly limited as long as it can completely or almost completely shut out the exposure light with a certain thickness.
  • examples thereof include a metal film, an alloy film, a half tone film (e.g., MoSiO x N y (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1)) or a layered film thereof. Among them, a chrome film is preferable.
  • the light-shielding film can be formed by a known method, e.g., sputtering, chemical vapor deposition and the like.
  • the thickness of the light-shielding film is not particularly limited as long as it can completely or almost completely shut out the exposure light, but may be about 50 to about 120 nm, for example.
  • the light-shielding film on the actual pattern region is patterned into a desired configuration while leaving the light-shielding film on the unoccupied region.
  • the desired configuration in this context is preferably a final actual pattern configuration so that the patterned light-shielding film can serve as the actual pattern.
  • the light-shielding film may be patterned into not the final actual pattern configuration, but a pattern similar to it, depending on the configuration of the actual pattern to be obtained, the position and size of the actual pattern region and the position and size of the unoccupied region and the like.
  • the configuration of the actual pattern is not particularly limited and L/S, length and density of the pattern may suitably be selected according to the characteristics of a semiconductor device to be finally obtained.
  • the light-shielding film preferably remains on the whole surface of the unoccupied region while providing a certain space between the edge of the remaining light-shielding film and the actual pattern region.
  • the light-shielding film may remain not entirely, but partially on the unoccupied region by patterning into a desired configuration, depending on the configuration of the actual pattern, the position and size of the actual pattern region and the position and size of the unoccupied region.
  • the size and the configuration of the unoccupied region itself are not particularly limited.
  • the space between the edge of the light-shielding film remaining on the unoccupied region and the actual pattern region can be determined taking EB alignment margin into consideration.
  • the space may be about 1 to about 5 ⁇ m, or about 1 to about 3 ⁇ m.
  • the space may be double of the margin, i.e., about 2 ⁇ m.
  • the light-shielding film it is preferable to leave the light-shielding film also on the periphery region around the field region of the substrate and the regions between the cells.
  • the patterning of the light-shielding film can be performed by a known method, for example, photolithography and etching.
  • a photolithography step a positive or negative resist which is known in the art is applied on the light-shielding film and exposed to light for development using a known exposure system such as EB exposure system, laser exposure system or the like.
  • a resist mask is formed and the light-shielding film is etched using the resist mask.
  • the light exposure may be performed by full-wafer exposure or drawing exposure.
  • the etching is preferably performed by dry etching such as RIE. Conditions for the etching can suitably be selected depending on the thicknesses and kinds of the resist film, the thicknesses and kinds of the light-shielding film consisting the mask and the kind of dry etching technique.
  • the patterning in this step does determine the configuration of the actual pattern and preferably performed with high accuracy.
  • the light-shielding film on the unoccupied region is removed while leaving the patterned light-shielding film on the actual pattern region.
  • the light-shielding film on the unoccupied region must be removed completely.
  • the entire light-shielding film on the actual pattern region must remain as it is.
  • the configuration of the light-shielding film is similar to the final actual pattern but requires further patterning, it may be partially removed in this step so as to completely correspond to the final actual pattern.
  • the light-shielding film also on the periphery region and the regions between the cells.
  • the removal of the light-shielding film from the unoccupied region can be performed by a known method, e.g., photolithography and etching.
  • a positive or negative resist which is known in the art is applied on the light-shielding film and exposed to light for development using a known exposure system such as EB exposure system, laser exposure system or the like.
  • a resist mask is formed and the light-shielding film is etched using the resist mask.
  • the light exposure may be performed by full-wafer exposure or drawing exposure.
  • the resist mask For fabricating the resist mask, for example, original data of the actual pattern is prepared and plus resizing is performed to the original data. Then the resized data is reversed to obtain dummy pattern data and plus resizing is performed to the dummy pattern data.
  • the resist mask is formed to correspond to the thus resized dummy pattern data.
  • the resizing amount is suitably adjusted within about 0.5 to about 5 ⁇ m, or about 1 to about 3 ⁇ m, for example, taking the EB alignment margin into consideration.
  • the resist mask may be formed corresponding to a data obtained by reversing the original data of the actual pattern. Further, the resist mask may suitably be formed by any other known method than the above ones.
  • the etching is preferably performed by dry etching such as RIE.
  • This etching is not for the purpose of patterning the actual pattern, but for removing the so-called dummy pattern formed on the unoccupied region.
  • Conditions for the etching can suitably be selected depending on the thicknesses and kinds of the resist film, the thicknesses and kinds of the light-shielding film consisting the mask and the kind of dry etching technique, as long as damage and step difference are not caused on the substrate surface.
  • the patterning in this step does not affect the accuracy of the actual pattern and does not require high resolution and high accuracy for the exposure, as compared with the exposure described above.
  • the organic conductive film may be Espacer 100 manufactured by Showa Denko, for example, in a thickness of about 10 to about 30 nm.
  • pre-baking e.g., on a hot plate in air at about 190° C. for about 15 minutes
  • post baking e.g., on the hot plate in air at about 100° C. for about 15 minutes
  • a positive resist film 3 of about 150 to about 500 nm thick is formed entirely and a first light exposure is performed to the resist film 3 .
  • the first light exposure is performed using an EB exposure system under the acceleration voltage of 10 kV and the light exposure amount of 6.0 to 8.0 ⁇ C/cm 2 , so that actual resist patterns are formed in actual pattern regions R and dummy resist patterns are formed in unoccupied regions S that are regions other than the actual pattern regions to have a desired space from the actual resist patterns.
  • the first light exposure is carried out using data shown in FIG. 2 ( d ) as mentioned later. Since the dummy resist patterns are formed in the unoccupied regions S through the first light exposure, variation in size of the resulting resist patterns due to the fogging phenomenon caused by the difference in density of pattern layout does not occur.
  • the resist film 3 is developed by a known method to form the actual resist patterns 3 a corresponding to actual patterns on the actual pattern regions R and the dummy resist patterns 3 b corresponding to dummy patterns on the unoccupied regions S. Thereafter, a thermal treatment (post baking) for degassing the resist patterns 3 a and 3 b is performed.
  • the post baking is carried out on a hot plate in air at 100° C. for about 15 minutes.
  • the chrome film 2 is patterned into the actual patterns 2 a on the actual pattern regions R and the dummy patterns 2 b on the unoccupied regions S by dry etching as shown in FIG. 1 ( c ).
  • the dry etching is carried out by RIE using Cl 2 and O 2 gases under power of 300 W and pressure of 25 Pa.
  • the difference in area of the resist patterns surrounding regions for forming the actual patterns 2 a is greatly reduced. Accordingly, the difference in etching rate of the chrome film is also reduced. As a result, the size variation of the chrome patterns can be inhibited.
  • chrome patterns are formed on the periphery of the mask substrate 1 (not shown).
  • a resist film 4 of about 500 nm thick is formed on the resulting actual patterns 2 a and the dummy patterns 2 b. Then a film of about 20 nm thick is formed thereon as a conductive film 5 .
  • a second light exposure is then performed to the conductive film 5 and the resist film 4 .
  • the second light exposure is carried out using the EB exposure system under the acceleration voltage of 10 kV and the light exposure amount of about 2.8 to about 6.0 ⁇ C/cm 2 such that the resulting resist pattern opens above the dummy patterns 2 b on the unoccupied regions S and covers the actual patterns 2 a on the actual pattern regions R.
  • the second light exposure is performed using data shown in FIG. 2 ( e ) as described later.
  • the conductive film 5 is selectively removed using a deionized water spray and the resist film 4 is developed to form resist patterns 4 a which covers only the actual patterns 2 a. Thereafter, a thermal treatment is performed for degassing the resist patterns 4 a. The thermal treatment is carried out on the hot plate in air at 100° C. for about 15 minutes.
  • the dummy patterns 2 b are completely etched away as shown in FIG. 1 ( f ).
  • This etching is performed not for patterning involved in the mask formation, but for the removal of the dummy patterns on the unoccupied regions S. Accordingly, the etching is carried out by RIE, for example, using Cl 2 of about 80 sccm and O 2 of about 20 sccm as the etching gas under power of about 80 W and pressure of about 6.8 Pa so as not to generate step difference on the mask substrate 1 .
  • the mask making is completed.
  • Dummy pattern data is formed by conducting the following calculation using MEBES format data (EB exposure data for mask formation) manufactured by ETEC, USA.
  • a mask pattern including actual pattern lines 11 a width of a single patterned line: 0.7 ⁇ m; length: several ⁇ m to several hundreds ⁇ m; width of space between the pattern lines: 0.7 ⁇ m
  • a unit cell 10 e.g., several tens of mm ⁇ several tens of mm
  • original data of the actual pattern lines 11 a as shown in FIG. 2 ( a ) is obtained.
  • FIG. 2 ( b ) plus resizing is performed to the original data of the actual pattern lines 11 a shown in FIG. 2 ( a ).
  • the pattern lines contact or overlap with each other to form a single rectangular pattern 12 .
  • the resulting resized data is reversed (FIG. 2 ( c )).
  • data of dummy pattern 11 b is obtained.
  • OR calculation is performed to the obtained data of the dummy pattern 11 b and the original data of the actual pattern lines 11 a (FIG. 2 ( d )).
  • the resulting data is used for the first light exposure. For example, where a positive resist film is used for the first light exposure as described above, reverse exposure is performed using the data shown in FIG. 2 ( d ) such that a resist pattern is formed on regions for forming the dummy pattern 11 b and the actual pattern lines 11 a.
  • FIG. 2 ( e ) another plus resizing is performed to the data of the dummy pattern 11 b shown in FIG. 2 ( c ).
  • the resulting data including a pattern 13 is used in the second light exposure for two-dimensionally separating the actual patterns 2 a and the dummy patterns 2 b patterned in the step shown in FIG. 1 ( c ).
  • the edge A of the pattern 13 is positioned between the actual pattern lines 11 a and the dummy pattern 11 b in FIG. 2 ( d ).
  • the space between the actual pattern lines 11 a and the dummy pattern 11 b is determined by the resized width the resizing in the step shown in FIG. 2 ( b ).
  • the space between the actual pattern lines 11 a and the dummy pattern 11 b will be an alignment margin, which needs to be considered for the resizing.
  • the space between the actual pattern lines 11 a and the dummy pattern 11 b can be ensured by setting the space greater than the alignment margin (e.g., ⁇ 0.5 ⁇ m).
  • a resist film is formed on a periphery 20 around a field region 23 of a mask substrate 25 and plural unit cells 22 are formed on the field region 23 to form a mask as shown in FIG. 3 ( a ). Then the space width between the mask pattern lines in each cell on the mask substrate 25 is measured.
  • the mask is obtained by forming actual pattern lines 21 and dummy pattern 24 having the configuration as shown in FIG. 3 ( b ) on the unit cell 22 and then removing the dummy pattern 24 .
  • a single actual pattern line has the width of 0.7 ⁇ m and the length of several ⁇ m to several hundreds ⁇ m.
  • the width of space between the actual pattern lines 21 is 0.7 ⁇ m and the distance between the actual pattern lines 21 and the dummy pattern 24 is 2.0 ⁇ m.
  • a comparative mask is formed under the same conditions (EB lithography, chrome etching) except that actual pattern lines 33 as shown in FIG. 4 ( a ) are formed directly on the mask substrate. Then the space width between the mask pattern lines in each cell on the mask substrate is measured.
  • the mask can be formed without difference in density of the pattern layout. Consequently, in a photolithography step (formation of the resist pattern), the size difference of the resist pattern lines due to the fogging can be reduced.
  • the difference in etching rate due to the resist area can be reduced.
  • the size variation of the patterned lines can be reduced and as a result, a highly precise mask, which can be used as a proximity exposure effect correction mask, can be formed.
  • the accuracy in the pattern size can be more ensured because the light-shielding film is patterned and removed by dry etching, the light-shielding film is also formed on the periphery region surrounding the actual pattern region and the unoccupied region on the substrate and the light-shielding film is a chrome film and/or the substrate is a quartz substrate. Therefore, higher yield can be realized in the mask formation.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
US09/697,424 2000-05-02 2000-10-27 Method for fabricating mask Expired - Lifetime US6503667B1 (en)

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JP2000-133750 2000-05-02
JP2000133750A JP2001312045A (ja) 2000-05-02 2000-05-02 マスクの形成方法

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EP (1) EP1152290B1 (fr)
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KR (1) KR100403933B1 (fr)
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US20040121613A1 (en) * 2002-12-13 2004-06-24 Takeshi Morita Estimation of remaining film thickness distribution, correction of patterning and insulation film removing masks with remaining film thickness distribution, and production of semiconductor device with corrected patterning and insulation film removing masks
US20050076320A1 (en) * 2003-10-02 2005-04-07 Kawasaki Microelectronics, Inc. Layout structure of semiconductor integrated circuit and method for forming the same
US20070281218A1 (en) * 2006-06-02 2007-12-06 Howard S Landis Dummy Phase Shapes To Reduce Sensitivity Of Critical Gates To Regions Of High Pattern Density
US20080082953A1 (en) * 2006-10-02 2008-04-03 Samsung Electronics Co., Ltd. Mask for forming fine pattern and method of forming the same
US20080226992A1 (en) * 2007-03-16 2008-09-18 Landis Howard S Structure and method for sub-resolution dummy clear shapes for improved gate dimensional control
US20100206622A1 (en) * 2009-02-17 2010-08-19 Kuo-Hua Chen Substrate structure and package structure using the same
US20130063707A1 (en) * 2011-09-14 2013-03-14 Ryota Aburada Pattern generating method, pattern forming method, and pattern generating program

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US7257790B2 (en) * 2003-10-02 2007-08-14 Kawasaki Microelectronics, Inc. Layout structure of semiconductor integrated circuit and method for forming the same
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US20080082953A1 (en) * 2006-10-02 2008-04-03 Samsung Electronics Co., Ltd. Mask for forming fine pattern and method of forming the same
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EP1152290A3 (fr) 2003-11-19
EP1152290B1 (fr) 2007-05-02
TW471043B (en) 2002-01-01
KR20010100767A (ko) 2001-11-14
JP2001312045A (ja) 2001-11-09
EP1152290A2 (fr) 2001-11-07
DE60034661T2 (de) 2008-01-31
DE60034661D1 (de) 2007-06-14

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