US6353900B1 - Coding system having state machine based interleaver - Google Patents

Coding system having state machine based interleaver Download PDF

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US6353900B1
US6353900B1 US09/172,069 US17206998A US6353900B1 US 6353900 B1 US6353900 B1 US 6353900B1 US 17206998 A US17206998 A US 17206998A US 6353900 B1 US6353900 B1 US 6353900B1
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circumflex over
data
memory
addresses
address
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Nagabhushana T. Sindhushayana
Jeremy Stein
Rajiv Vijayan
Fuyun Ling
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Qualcomm Inc
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Qualcomm Inc
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Priority claimed from US09/158,457 external-priority patent/US6304985B1/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to US09/172,069 priority Critical patent/US6353900B1/en
Assigned to QUALCOMM INCORPORATED reassignment QUALCOMM INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SINDHUSHAYANA, NAGABHUSHANA T., VIJAYAN, RAJIV, LING, FUYUN, STEIN, JEREMY
Priority to PCT/US1999/024061 priority patent/WO2000022738A1/en
Priority to KR1020017004714A priority patent/KR20010080157A/ko
Priority to MXPA01003814A priority patent/MXPA01003814A/es
Priority to EP99953179A priority patent/EP1121761A1/en
Priority to CA002347237A priority patent/CA2347237A1/en
Priority to IL14256299A priority patent/IL142562A0/xx
Priority to AU65172/99A priority patent/AU6517299A/en
Priority to RU2001112766/09A priority patent/RU2001112766A/ru
Priority to JP2000576546A priority patent/JP2002527980A/ja
Priority to BR9914541-3A priority patent/BR9914541A/pt
Priority to IDW00200101068A priority patent/ID29939A/id
Priority to CNB998142719A priority patent/CN1186880C/zh
Priority to NO20011889A priority patent/NO20011889L/no
Priority to HK02101499.2A priority patent/HK1040011B/zh
Publication of US6353900B1 publication Critical patent/US6353900B1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2742—Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2757—Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2789—Interleaver providing variable interleaving, e.g. variable block sizes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes

Definitions

  • the present invention relates to coding. More particularly, the present invention relates to a novel and improved technique for performing iterative coding and decoding.
  • “Turbo coding” represents an important advancement in the area of forward error correction (FEC).
  • FEC forward error correction
  • turbo codes could improve the performance of wireless satellite links, where the limited downlink transmit power of the satellite necessitates receiver systems that can operate at low E b /N o levels.
  • Digital wireless telecommunication systems such as digital cellular and PCS telephone systems, also use forward error correction.
  • the IS-95 over-the-air interface standard, and its derivatives, such as IS-95B define a digital wireless communications system that uses convolutional encoding to provide coding gain to increase the capacity of the system.
  • a system and method for processing RF signals substantially in accordance with the use of the IS-95 standard is described in US pat. No. 5,103,459 entitled “System and Method for Generating Signal Waveforms in a CDMA ellular Telephone System” assigned to the assignee of the present invention and incorporated herein by reference ('459 patent). which are small and light.
  • this requires development of a semiconductor integrated circuit (“chip”) for performing most or all of the necessary processing. While convolutional encoding is relatively complex, the circuits necessary to perform convolutional encoding and decoding can be formed on a single chip along with any other necessary circuitry.
  • Turbo coding (in particular the decoding operation) is significantly more complex than convolutional encoding. Nonetheless, it would be highly desirable to include turbo coding in digital wireless telecommunication systems, including mobile digital communication systems. Thus, the present invention is directed to reducing the complexity associated with performing turbo coding, and therefore facilitating the use of turbo coding in systems where mobility is desirable, or where power consumption and circuit size are of concern.
  • the present invention is a novel and improved technique for performing coding with particular application to turbo, or iterative, coding techniques.
  • interleaving is performed by generating the address of a memory using a PN state generator. Data is written into a memory in sequential order, and then read out using addresses specified by the PN state generator. To deinterleave, the interleaved data is written into a memory using addresses specified by the PN state generator, and then read out in sequential order.
  • a set of PN state generators that provide excellent coding performance is provided.
  • FIGS. 1A and 1B are block diagrams of turbo coders when configured in accordance with one embodiment of the invention.
  • FIG. 2 is a block diagram of an interleaver when configured in accordance with one embodiment of the invention.
  • FIGS. 3A and 3B are diagrams of PN code generators when configured in accordance with one embodiment of the invention.
  • FIG. 4 is a block diagram of an alternative and more generalized embodiment of the invention.
  • FIGS. 5A and 5B are block diagrams of decoders configured in accordance with one embodiment of the invention.
  • FIG. 6 is a graph illustrating the performance of one embodiment of the invention.
  • FIG. 7 is a graph illustrating the performance of another embodiment of the invention.
  • the present invention is a novel and improved technique for performing turbo coding.
  • the exemplary embodiment is described in the context of the digital cellular telephone system. While use within this context is advantageous, different embodiments of the invention may be incorporated in different environments or configurations.
  • the various systems described herein may be formed using software-controlled processors, integrated circuits, or discreet logic, however, implementation in an integrated circuit is preferred.
  • the data, instructions, commands, information, signals, symbols and chips that may be referenced throughout the application are advantageously represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or a combination thereof.
  • the blocks shown in each block diagram may represent either hardware or method steps.
  • FIGS. 1A and 1B provide highly simplified illustrations of two types of turbo coders.
  • FIG. 1A depicts a parallel concatenated turbo encoder.
  • Coder 1 and interleaver 2 receive the encoder input data 4 , which is typically user information or control data.
  • Coder 1 outputs systematic symbols 5 (typically a copy of the original input bits) and parity symbols 3 .
  • Coder 6 receives the interleaved output of interleaver 2 and outputs a second set of parity symbols 7 .
  • the outputs of coder 1 and coder 6 are muxed into the output data stream for a total coding rate R of 1 ⁇ 3. Additional coder and interleaver pairs may be added to reduce the coding rate for increased forward error correction.
  • Coders 1 and 6 may be various types of coders including block coders or convolutional coders.
  • coders 1 and 6 typically have a small constraint length of such as 4 (four) to reduce complexity, and are recursive systematic convolutional (RSC) encoders. The lower constraint length reduces the complexity of the corresponding decoder.
  • FIG. 1B depicts a serial concatenated turbo coder.
  • Input data 13 is coded by coder 10 and the parity symbols are applied to interleaver 12 .
  • the resulting interleaved parity symbols are supplied to coder 14 , which performs additional encoding to generate parity symbols 15 .
  • coder 10 (the outer coder) may be various types of encoders including block encoders or convolutional encoders, but coder 14 (the inner coder) must be a recursive coder and is typically a recursive systematic encoder.
  • coders 10 and 14 As recursive systematic convolutional (RSC) encoders, coders 10 and 14 generate symbols at a coding rate R ⁇ 1. That is, for a given number of input bits N, M output symbols are generated where M>N.
  • the total coding rate for the serial concatenated turbo coder of FIG. 1B is the coding rate of coder 10 multiplied by the coding rate of coder 14 . Additional interleaver and coder pairs may also be added in series to reduce the coding rate and therefore provide additional error protection.
  • FIG. 2 is a block diagram of an interleaver configured in accordance with one embodiment of the invention.
  • the interleaver may be used, for example, as interleavers 2 or 12 within the circuits of FIG. 1A or FIG. 1 B.
  • memory 26 receives encoder input data 19 , as well as address data 21 from mux 20 .
  • Mux 20 supplies address data 21 from either counter 18 or PN state machine 22 and address filter 24 .
  • a control system (not shown for ease of drawing) controls mux 20 , counter 18 , PN state machine 22 and address filter 24 .
  • the control system is preferably comprised of a microprocessor or DSP running software instructions stored in memory.
  • encoder input data 19 is written into memory 26 with the address specified by the application of counter 18 to the address input using mux 20 .
  • the data is then read out to coder 14 by applying PN state machine 22 , after filtering by address filter 24 , to the address input of memory 26 via mux 20 .
  • the data is read out in an alternative order to coder 14 with respect to the encoder data received by coder 10 .
  • the PN state machine is applied to the address input of the memory as data is written in, and the counter is applied to the address input of the memory as data is written out.
  • Address filter 24 removes address from PN state machine 22 that are greater than the addressable memory space of memory 26 .
  • address filter 24 receives addresses from PN state machine 22 .
  • the possible set of addresses for a PN generator of length L is equal to 2 L ⁇ 1, where L is the number of bits in the PN state.
  • address filter 24 determines when an address from PN state machine 22 is greater than the memory size N. If so, address filter signals PN state machine 22 to switch to the next state, and performs the comparison again. So long as the address from PN state machine 22 exceeds N, address filter 24 will continue to advance the state of PN state machine 22 until an address that is less than N is generated.
  • N and increasing or decreasing the number of bits generated by PN state machine 22 , different sized memories can be accommodated by changing the value of N.
  • a state generator must be selected such that the PN state machine does not enter the same state twice, before covering all the possible states. This condition will be satisfied if the PN generator produces a maximal length shift register sequence. Making the PN generator a primitive polynomial in the Galois field GF 2 is one way to achieve this characteristic. Also, the state machine may be initialized with a logic one in the most significant position, followed by logic zeros in the remaining positions. Other initialization values may also be used.
  • address filter ensures that only addresses within the size of memory 26 are applied.
  • a value V may be subtracted from the address generated by the PN state machine. The result is then address is retained only if it lies within 1 and N. Values V of 1 or 64 are acceptable. In still another embodiment of the invention, the number V maybe subtracted when the right most registers of the state machine have a value of between V and N ⁇ 1+V, and used without subtraction of V otherwise.
  • an advantage of the invention is that more effective interleaving can be performed that provides high performance coding and decoding with a minimum of additional complexity.
  • PN state machine By using a PN state machine to generate the addresses, more complex interleaving can performed, and therefore higher performance coding and decoding obtained, with reduced circuit space and power consumption.
  • counter 18 may be replaced with another state machine.
  • a second PN state machine could be used in place of counter 18 , so long as the two PN state machines covered the necessary address space in different order.
  • a counter could simply be considered a PN state machine having a PN sequence equal to the binary counting sequence.
  • the sequence of the PN states generated is adjusted to further increase performance with little additional complexity.
  • S 1 , S 1 , S 3 . . . S N an integer k is found that is relatively prime to the period of the PN sequence 2 L ⁇ 1.
  • Significant performance improvements may be obtained by choosing k to be on the order of L.
  • two or more interleavers may be interlaced to generate a single interleaver of larger span.
  • the two interleavers can both be polynomial based, and generally use different polynomial. Combination of polynomial based and other types of interleavers is also contemplated.
  • two interleavers of equal length can be used in parallel to generate a single permutation in which the even and odd indices are permuted separately. This may be useful if the decoder needs to access two adjacent symbols of the interleaver input/output simultaneously without the use of a dual port memory.
  • two interleavers of different size may be interlaced to form a larger interleaver that is not an integral power of 2.
  • interleavers of span 2047 and 1023 may be interlaced to construct a larger interleaver of span 3070 .
  • the two constituent interleavers are obtained from primitive polynomials of degree 11 and 10 respectively.
  • FIGS. 3A and 3B illustrate two PN sequence generators when configured in accordance with one embodiment of the invention.
  • a set of latches 50 ( 1 )- 50 (L) store state variables S 1 -S L .
  • Polynomial coefficients C 1 -C L ⁇ 1 are applied to AND-gates 52 ( 1 )- 52 (L- 1 ), which also receive the state variables S 1 -S L ⁇ 1 .
  • State variables S 1 -S L ⁇ 1 are also applied to the input of the next latch.
  • XOR-gates 54 ( 1 )-(L- 1 ) receive the outputs of AND-gates 52 ( 1 )-(L).
  • XOR-gates 54 ( 1 )- 54 (L- 2 ) also receive the outputs of adjacent XOR-gates 54 ( 2 )- 54 (L- 1 ), and XOR-gate 54 (L) also receives the output of latch 50 (L).
  • the output of XOR-gate 54 ( 1 ) is the output of the PN state machine, as well as the input to latch 50 ( 1 ).
  • the polynomial coefficients determine the way the state variables change as data is clocked through.
  • the application of different polynomials changes the particular PN sequence generated, and the selection of certain polynomials generates a sequence of addresses which allow nearly optimal interleaving to be performed.
  • a circuit like that shown in FIG. 2A can use used. Such a circuit occupies significantly less circuit area than a corresponding look-up-table, and therefore reduces the overall required chip area to implement the turbo coder.
  • FIG. 3B provides an alternative method for generating PN states.
  • the XOR-gates 62 ( 1 )- 62 (L- 2 ) are coupled between latches 60 ( 0 )- 60 (L), and the output of latch 60 ( 0 ) is applied to AND-gates 64 ( 1 )- 64 (L- 1 ) as well as to latch 60 (L- 1 ).
  • AND-gates 64 ( 1 )- 64 (L- 1 ) also receive polynomial coefficients C( 1 )-C(L- 1 ).
  • the outputs of AND-gates 64 ( 1 )- 64 (L- 1 ) are applied to XOR-gates 62 ( 1 )- 62 (L- 2 ).
  • the application of different polynomials changes the particular PN sequence generated, and the selection of certain polynomials generates a sequence of addresses which allow nearly optimal interleaving to be performed.
  • the polynomials used in the PN state machine are as set forth in Table I:
  • the bit size of the address is preferably the smallest number L that gives a maximum address that is greater than or equal to the size N of the memory.
  • Table II provides still more polynomials that may be used in alternative embodiments of the invention.
  • Table III provides some polynomials that may be used in alternative embodiments of the invention.
  • FIG. 4 is a block diagram of an alternative and more generalized embodiment of the invention.
  • the interleaver address generation is performed by combining a row-column address generator with one or more PN address generator.
  • interleaver memory 200 has data input-output (I/O) 202 and address input 204 .
  • Address input 204 is comprised of row input 206 and column input 208 .
  • Column multiplexer 210 provides either the output of column counter 212 or column PN address generator to column input 208 .
  • Row multiplexer 220 provides either the output of row counter 222 or row PN address generator 214 to row input 206 .
  • Column PN address generator 214 receives polynomial values from PN polynomial bank 216 and row PN address generator 214 receives polynomial values from PN polynomial bank 226 .
  • each row is associated with a PN address generator of length c, with the particular generator defined by a different polynomial stored in PN polynomial bank 226 .
  • each column is associated with a PN interleaver of length r, with the particular generator defined by a different polynomial stored in PN polynomial bank 216 .
  • the interleavers associated with the different rows or columns may be identical or distinct.
  • the one of either the column or row address generators may be something other than a PN based address generator such as bit reversal address generator, cyclic shift address generator or even an identity address generator.
  • the data to be interleaved is written into the interleaver buffer in a row by row fashion using row counter 222 , while the columns are selected using column PN address generator 214 .
  • each row is addressed using row PN address generator 224 and the columns are addressed using column counter 212 .
  • the order or reading and writing may be interchanged.
  • the polynomial used by a PN address generator is changed for each row or column addressed by loading a new polynomial from a PN polynomial bank.
  • the different polynomials can be generated by using the “mirror” image of the polynomials listed in Tables I-III, where logic ones are set to logic zeros and vice-versa.
  • Other methods of changing the address generation from row to row (or colum to colum) may be used.
  • the starting states of the PN state machines may be changed from row to row.
  • the PN state machine could be clocked a different number of times for each row.
  • different state machines like the two state machines of FIG. 3, could be used for different rows.
  • the use of the interleaver as shown in FIG. 4 provides additional performance with only a minimal amount of complexity.
  • FIG. 5A is a block diagram of a decoder for parallel turbo coding when configured in accordance with one embodiment of the invention.
  • Receive data is received on input 40 and applied to decoder 44 and interleaver 46 .
  • the output of deinterleaver 46 is applied to decoder 48 and the outputs of decoders 44 and 48 are applied to summer 50 .
  • the output of summer 50 forms the output of the decoder, but is also applied as a second input through mux 42 for iterative decoding.
  • decoder 48 and decoder 44 are coupled via interleaver 50 and deinterleaver 52 .
  • data received by decoder 44 and decoder 48 is repeatedly decoded and exchanged after by interleaved and deinterleaved by interleaver 54 and deinterleaver 52 . Once a desired number of iterations are performed, or a desired error level achieve, the output is taken from summer 50 .
  • FIG. 5B is a block diagram of a decoder for serial turbo coding configured in accordance with one embodiment of the invention.
  • Input data 70 is received by decoder 72 , the output of which is applied to deinterleaver 74 .
  • the deinterleaved output of deinterleaver 74 is applied to decoder 76 .
  • the output of decoder 76 is applied to deinterleaver 78 , the output of which is applied to decoder 72 .
  • the output of decoder 76 also forms the output of the serial turbo decoder.
  • the received symbols are repeatedly decoded by decoders 72 and 76 . Once a desired number of decoder iterations are performed, or a desired error level achieved, output is taken from decoder 76 .
  • deinterleavers of FIGS. 4A and 4B are configured in a similar manner to that shown in FIG. 2 except, as described above, the PN state machine is applied during writing and the counter is applied during reading.
  • the interleavers are preferably configured as shown in FIG. 2 .
  • FIG. 6 is a graph illustrating the performance of a particular polynomial using a rate 1 ⁇ 4 serial concatenated turbo code when compared to other interleaving schemes which require the use of a look-up-table.
  • the value K is the size of the data frame being processed.
  • the frame error rate (FER) and the bit error rate (BER) are shown for an ideal interleaver and the PN based interleaver.
  • FER frame error rate
  • BER bit error rate
  • the performance of the PN based interleaving scheme is nearly identical to that of the look-up-table scheme at an error rate (error probability) of 1 ⁇ 10 ⁇ 3 .
  • This error rate is the preferred level of operation for an IS-95 based CDMA wireless telecommunications system, as well as many other digital wireless systems.
  • the savings in circuit space can be provides with little or no reduction in performance by use of the PN based interleaving scheme.
  • FIG. 7 is a graph illustrating a rate 1 ⁇ 2 serial concatenated turbo code when compared to other interleaving schemes which require the use of a look-up-table.
  • the difference between the ideal and PN base interleaver is small at error rate of 1 ⁇ 10 ⁇ 3 .
  • the savings in circuit space can be provides with little or no reduction in performance by use of the PN based interleaving scheme.

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US09/172,069 1998-09-22 1998-10-13 Coding system having state machine based interleaver Expired - Lifetime US6353900B1 (en)

Priority Applications (15)

Application Number Priority Date Filing Date Title
US09/172,069 US6353900B1 (en) 1998-09-22 1998-10-13 Coding system having state machine based interleaver
CNB998142719A CN1186880C (zh) 1998-10-13 1999-10-12 具有基于状态机的交织器的编码系统
AU65172/99A AU6517299A (en) 1998-10-13 1999-10-12 Coding system having state machine based interleaver
BR9914541-3A BR9914541A (pt) 1998-10-13 1999-10-12 Sistema de codificação possuindo intercalador baseado em máquina de estado
MXPA01003814A MXPA01003814A (es) 1998-10-13 1999-10-12 Sistema de codificacion que tiene una maquina de estado basada en un intercalador.
EP99953179A EP1121761A1 (en) 1998-10-13 1999-10-12 Coding system having state machine based interleaver
CA002347237A CA2347237A1 (en) 1998-10-13 1999-10-12 Coding system having state machine based interleaver
IL14256299A IL142562A0 (en) 1998-10-13 1999-10-12 Coding system having state machine based interleaver
PCT/US1999/024061 WO2000022738A1 (en) 1998-10-13 1999-10-12 Coding system having state machine based interleaver
RU2001112766/09A RU2001112766A (ru) 1998-10-13 1999-10-12 Система кодирования, имеющая перемежитель на основе конечного автомата
JP2000576546A JP2002527980A (ja) 1998-10-13 1999-10-12 状態マシンをベースとするインタリーバを有する符号化システム
KR1020017004714A KR20010080157A (ko) 1998-10-13 1999-10-12 스테이트 머신 기반 인터리버를 가지는 코딩 시스템
IDW00200101068A ID29939A (id) 1998-10-13 1999-10-12 Sistem pengkodean yang memiliki mesin kondisi berdasarkan interleaver
NO20011889A NO20011889L (no) 1998-10-13 2001-04-17 System for koding, med tilstandsmaskinbasert innfeller
HK02101499.2A HK1040011B (zh) 1998-10-13 2002-02-27 具有基於狀態機的交織器的編碼系統

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