US6337823B1 - Random access memory device capable of minimizing sensing noise - Google Patents

Random access memory device capable of minimizing sensing noise Download PDF

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Publication number
US6337823B1
US6337823B1 US09/612,169 US61216900A US6337823B1 US 6337823 B1 US6337823 B1 US 6337823B1 US 61216900 A US61216900 A US 61216900A US 6337823 B1 US6337823 B1 US 6337823B1
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signal
voltage
sense amplification
power supply
amplification activation
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Dong-Il Seo
Gi-hong Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Definitions

  • the present invention is in the field of semiconductor integrated circuit devices and is more specifically related to a dynamic random access memory device that minimizes noise induced by sense amplifier circuits.
  • FIG. 1 is a block diagram of a conventional dynamic random access memory device.
  • each memory cell MC includes an access transistor 10 acting as a switch and a capacitor 12 holding a data bit.
  • One of the electrodes of each capacitor 12 is coupled to a drain of a corresponding access transistor 10 , and the other electrode thereof is coupled to a plate voltage Vp.
  • a row decoder 14 decodes the row address signal and activates a word line corresponding to the decoded row address signal to thereby turn on all access transistors 10 of memory cells MC coupled to the activated word line.
  • Sense amplifier circuits 16 sense and amplify very small voltage difference resulting from charge flowing to corresponding bit lines.
  • Each of the sense amplifier circuits 16 responds to signals LAPG and LANG from a sense amplification activation signal generator 22 and drives a lower voltage on a bit line to a ground voltage VSS and a higher voltage of a bit line to an internal power supply voltage VCCA.
  • An input/output gate circuit 20 transfers the amplified bit line signals to a data output buffer 24 .
  • FIG. 2 is a circuit diagram of the sense amplification activation signal generator 22 illustrated in FIG. 1 .
  • This embodiment of the sense amplification activation signal generator 22 includes four inverters INV 1 , INV 2 , INV 3 , and INV 4 connected as illustrated in FIG. 2 .
  • the inverters INV 2 and INV 3 serve as a buffer.
  • the generator 22 provides a sense amplification activation signal LAPG at a high level and a sense amplification activation signal LANG at a low level when a row active command signal (e.g., a word line enable signal) is at a low level.
  • the generator 22 provides the signal LAPG at a low level and the signal LANG at a high level when the row active command signal is at a high level.
  • FIG. 3 is a circuit diagram showing sense amplifier circuits 16 .
  • Each of the sense amplifier circuits 16 is coupled between bit lines of a corresponding pair of bit lines, and is composed of two PMOS transistors MP 1 and MP 2 and two NMOS transistors MN 1 and MN 2 connected as illustrated in FIG. 3 .
  • First current electrodes of the PMOS transistors MP 1 and MP 2 in each of the sense amplifiers 16 are commonly coupled to a signal line LA, and first current electrodes of the NMOS transistors MN 1 and MN 2 are coupled to a signal line LAB.
  • the signal line LA is connected to an internal power supply voltage VCCA via a PMOS transistor MP 3 , which the sense amplification activation signal LAPG switches.
  • the line LAB is connected to a ground voltage VSS via an NMOS transistor MN 3 , which the sense amplification activation signal LANG switches.
  • each sense amplifier circuit 16 When a word line is selected, one of the respective bit lines of each pair changes to a voltage lower or higher than a precharge voltage (e.g., VCC/2), while the other bit line remains at the precharge voltage.
  • bit line voltages turn on one of the PMOS transistors MP 1 and MP 2 and one of the NMOS transistors MN 1 and MN 2 .
  • the sense amplification activation signals LAPG and LANG are activated respectively low and high, the signal lines LA and LAB are coupled to VCCA and VSS through corresponding transistors MP 3 and MN 3 , respectively.
  • each sense amplifier circuit 16 amplifies bit line voltages of a corresponding pair of bit lines BLj and BLjB to voltages VCCA and VSS or voltages VSS and VCCA.
  • FIG. 4 illustrates the timing of signals in the high and low supply voltage cases.
  • the conventional sense amplification activation signal generator 22 when a power supply voltage is high, noise such as power supply voltage bouncing or ground voltage bouncing is higher. Such noise may occur when multiple sense amplifier circuits 16 operate. As an internal power supply voltage (or an external power supply voltage) increases, rise/fall time of the respective signals LAPG and LANG (or the time required to turn on a transistor) becomes shorter. If the rise/fall time becomes shorter, the amount of current instantly supplied through each MOS transistor, i.e., the peak current increases.
  • the peak current may further increase when the transistors MP 3 and MN 3 simultaneously turned on, resulting in greater noise such as the power supply voltage bouncing and the ground voltage bouncing. This increases noise (referred to as a sensing noise) when sense amplifier circuits 16 operate simultaneously.
  • the power supply voltage bouncing and the ground voltage bouncing can cause a malfunction in peripheral circuits.
  • bouncing from operation of one bank affects operation of another bank. Accordingly, circuits and methods for minimizing the sensing noise resulting from operation of sense amplifier circuits are sought.
  • the embodiments of the present invention provide a random access memory device capable of minimizing sensing noise that causes variation of an operating voltage.
  • the advantages and features of the present invention can be exhibited in a dynamic random access memory (DRAM) device.
  • the DRAM device includes: a memory cell array for storing data; a plurality of bit line pairs coupled to the memory cell array; and a plurality of sense amplifier circuits coupled to respective bit line pairs.
  • each of the sense amplifier circuits senses a voltage difference between bit lines of a corresponding pair and amplifies the sensed voltages to a first and second power supply voltages or to the second and first power supply voltages.
  • a sense amplification activation signal generating circuit generates first and second sense amplification activation signals in response to a row active command signal.
  • the sense amplification activation signal generating circuit includes: a voltage comparator; a first signal generator, a second signal generator, and a switch.
  • the voltage comparator compares a third power supply voltage with a reference voltage to generate a comparison signal.
  • the first signal generator generates the first and second sense amplification activation signals of a first rise/fall time in response to the row active command signal.
  • the second signal generator generates the first and second sense amplification activation signals of a second rise/fall time, which is delayed more than the first rise/fall time, in response to the row active command signal.
  • the switch selects one of the first and second signal generators in response to the comparison signal to output signals from the selected signal generator as the first and second sense amplification activation signals.
  • Another embodiment of the invention is memory device that also includes: a memory cell array for storing data; a plurality of bit line pairs coupled to the memory cell array; and a plurality of sense amplifier circuits coupled to the respective bit line pairs.
  • Each of the sense amplifier circuits senses a voltage difference between bit lines of a corresponding pair and amplifies the sensed voltages either to first and second power supply voltages or to the second and first power supply voltages in response to first and second sense amplification activation signals.
  • a sense amplification activation signal generating circuit generates first and second sense amplification activation signals in response to a row active command signal.
  • the sense amplification activation signal generating circuit includes a voltage comparator, a signal generator, a first delay, and a second delay.
  • the voltage comparator compares a third power supply voltage with a reference voltage to generate a comparison signal.
  • the signal generator generates first and second signals in response to the row active command signal.
  • the first delay adjusts rise/fall time of the first signal to output the first signal thus adjusted as the first sense amplification activation signal, depending on a logic level of the comparison signal.
  • the second delay adjusts the rise/fall time of the second signal to output the second signal thus adjusted as the second sense amplification activation signal, depending on a logic level of the comparison signal.
  • FIG. 1 is a block diagram of a conventional dynamic random access memory device.
  • FIG. 2 is a circuit diagram of a sense amplification activation signal generator illustrated in FIG. 1 .
  • FIG. 3 is a circuit diagram including sense amplifier circuits corresponding to respective bit line pairs illustrated in FIG. 1 .
  • FIG. 4 is a timing diagram showing a relationship between variations of bit line voltage and enable/disable speed of sense amplification activation signals for different power supply voltages in the device of FIG. 1 .
  • FIG. 5 is a block diagram of a random access memory device according to an embodiment of the present invention.
  • FIG. 6 is circuit diagram of an embodiment of a sense amplification activation signal generating circuit illustrated in FIG. 5 .
  • FIG. 7 is a timing diagram showing a relationship between variations of bit line voltage and enable/disable speed of sense amplification activation signals for different power supply voltages in the device of FIG. 5;
  • FIG. 8 shows a block diagram of a random access memory device according to another embodiment of the present invention.
  • FIG. 9 is circuit diagram of an embodiment of a sense amplification activation signal generating circuit illustrated in FIG. 8 .
  • FIG. 5 shows a dynamic random access memory device according to an embodiment of the present invention.
  • the constituent elements that are identical to those in the conventional art of FIG. 1 are labeled with the same reference numerals, and description thereof is omitted.
  • a sense amplification activation signal generating circuit 100 produces sense amplification activation signals LAPG and LANG, which are commonly supplied to sense amplifier circuits 16 , in response to a row active command signal.
  • the circuit 100 includes a voltage comparator 120 , first and second sense amplification activation signal generators 140 and 160 , and a switch 180 .
  • the voltage comparator 120 compares a power supply voltage (internal or external power supply voltage) with a predetermined reference voltage to generate a comparison signal COMP.
  • the first signal generator 140 activates first sense amplification activation signals LAPG 1 and LANG 1 in response to activation of a row active command signal.
  • the second signal generator 160 activates second sense amplification activation signals LAPG 2 and LANG 2 in response to activation of the row active command signal.
  • Second sense amplification activation signals LAPG 2 and LANG 2 have a rise/fall time (or a slope) that is longer (or slower) than that of the first signals LAPG 1 and LANG 1 .
  • the switch 180 transfers either the first signals LAPG 1 and LANG 1 or the second signals LAPG 2 and LANG 2 as the output signals LAPG and LANG from the circuit 100 .
  • FIG. 6 is a circuit diagram of an embodiment of the sense amplification activation signal generating circuit 100 .
  • the voltage comparator 120 compares a first input voltage Vin 1 as an operating voltage (an internal or external power supply voltage) with a second input voltage Vin 2 as the reference voltage, and generates the comparison signal COMP.
  • the first input voltage Vin 1 is the operating voltage VDD, which is 3.0 ⁇ 0.3 volts
  • the second voltage Vin 2 is from an internal voltage generating circuit (not shown) that sets the second input voltage Vin 2 to 1.5 volts. More generally, the second input voltage Vin 2 depends on the first input voltage Vin 1 and the threshold voltages of transistors MN 4 and MN 5 .
  • the comparator 120 includes a differential amplifier having a positive input terminal (+) receiving the first input voltage Vin 1 and a negative input terminal ( ⁇ ) receiving the second input voltage Vin 2 . With this configuration, the comparator 120 generates the comparison signal COMP at a low level when the first input voltage Vin 1 after voltage drops through transistors MN 4 and MN 5 is lower than the second input voltage Vin 2 . The comparator 120 generates the comparison signal COMP at a high level when the first input voltage Vin 1 after voltage drops through transistors MN 4 and MN 5 is higher than the second input voltage Vin 2 .
  • the first sense amplification activation signal generator 140 includes four inverters INV 5 to INV 8 , which have the same sizes and speed as those in FIG. 2 .
  • the inverters INV 6 and INV 7 serve as a buffer.
  • the output signals LAPG 1 and LANG 1 of the generator 140 have the same slopes (referred to herein as “a first slope”) or rise/fall time as signals LAPG and LANG in FIG. 2 .
  • the second sense amplification activation signal generator 160 includes four inverters INV 9 to INV 12 and four resistors R 1 to R 4 connected as illustrated in FIG. 6 .
  • the inverters INV 10 and INV 11 serve as a buffer.
  • the signals LAPG 2 and LANG 2 have shallower slopes (referred to herein as “a second slope”) than do the signals LAPG 1 and LANG 1 .
  • the switch 180 includes four transfer gates TG 1 , TG 2 , TG 3 , and TG 4 and an inverter INV 13 connected as illustrated in FIG. 6 .
  • the comparison signal COMP When the comparison signal COMP is low, the transfer gates TG 1 and TG 2 are enabled, and the transfer gates TG 3 and TG 4 are disabled. As a result, the switch 180 outputs the signals LAPG 1 and LANG 1 as the output signals LAPG and LANG of the circuit 100 .
  • the comparison signal COMP is high (i.e., when the power supply voltage after voltage drops through transistors MN 4 and MN 5 is higher than the reference voltage)
  • the transfer gates TG 1 and TG 2 are disabled, and the transfer gates TG 3 and TG 4 are enabled.
  • the switch 180 outputs the signals LAPG 2 and LANG 2 as the output signals LAPG and LANG of the circuit 100 . Accordingly, the slopes of the output signals LAPG and LANG increase more slowly than do the slopes of signals LAPG 1 and LANG 1 .
  • one bit line from each pair has a voltage changed into a voltage either higher or lower than a precharge voltage (e.g., VCC/2), and the other bit line of the pair remains at the precharge voltage.
  • a precharge voltage e.g., VCC/2
  • one of the PMOS transistors MP 1 and MP 2 of each sense amplifier circuit 16 is turned on, and one of the NMOS transistors MN 1 and MN 2 thereof is turned on.
  • the sense amplification activation signal generating circuit 100 produces the signals LAPG and LANG having either the first slope or the second slope in accordance with the level of the supply voltage, as will be more fully described below.
  • the first and second sense amplification activation signal generators 140 and 160 produce corresponding signals LAPG 1 , LANG 1 , LAPG 2 and LANG 2 in response to a row active command signal. If the power supply voltage has a higher than the nominal level, the voltage comparator 120 in FIG. 6 generates the comparison signal COMP at a high level. This forces the signals LAPG 2 and LANG 2 of the second slope (i.e., delayed rise/fall time) to be the output signals LAPG (HVCC) and LANG (HVCC) of the circuit 100 . As compared with the signals LAPG and LANG illustrated in FIG. 4, the output signals LAPG and LANG from the circuit 100 have shallower slopes. Thus, although the power supply voltage is higher than a predetermined voltage, the peak current issued at an activation of the sense amplifier circuits 16 is reduced.
  • the voltage comparator 120 When the power supply voltage is lower than the reference voltage, the voltage comparator 120 generates the comparison signal COMP at a low level, and the signals LAPG 1 and LANG 1 in a period A of FIG. 7 are the output signals LAPG and LANG from the circuit 100 .
  • the signal lines LA and LAB commonly coupled to the sense amplifier circuit 16 are respectively coupled to voltages VCCA and VSS through corresponding PMOS and NMOS transistors MP 3 and MN 3 , which the signals LAPG and LANG turn on.
  • the slope of signals LAPG and LANG are determined according to the power supply voltage level.
  • each sense amplifier circuit 16 amplifies voltages on bit lines of the corresponding pair to voltages VCCA and VSS (or VSS and VCCA), but the peak currents for the operations are reduced to correspondingly reduce noise in the supply voltages.
  • FIG. 8 shows a dynamic random access memory (DRAM) device according to another embodiment of the present invention.
  • DRAM dynamic random access memory
  • the sense amplification activation signal generating circuit 200 includes a voltage comparator 220 , a sense amplification activation signal generator 240 , a first delay 260 , and a second delay 280 .
  • the voltage comparator 220 compares a power supply voltage (internal or external power supply voltage) with a predetermined reference voltage to generate a comparison signal COMP.
  • the sense amplification activation signal generator 240 produces signals LAPG′ and LANG′ in response to a row active command signal (e.g., word line enable signal).
  • the first and second delays 260 and 280 adjust the rise/fall time (or slope) of corresponding signals according to a logic level of the comparison signal COMP, as will be more fully described below.
  • FIG. 9 is a circuit diagram of an embodiment of the sense amplification activation signal generating circuit 200 .
  • a voltage comparator 220 compares an internal or external power supply voltage as a first input voltage Vin 1 with a predetermined reference voltage as a second input voltage Vin 2 , and then outputs a comparison signal COMP of either a low level or a high level.
  • the voltage comparator 220 includes a differential amplifier which has a positive input terminal (+) receiving the first input voltage Vin 1 , which is supplied via diode-connected NMOS transistors MN 6 and MN 7 , and a negative input terminal ( ⁇ ) receiving the second input voltage Vin 2 .
  • the comparator 220 when the first input voltage Vin 1 after voltage drops through NMOS transistors MN 6 and MN 7 is lower than the second input voltage Vin 2 , the comparator 220 outputs the comparison signal COMP at a low level. When the first input voltage Vin 1 (after voltage drops) is higher than the second input voltage Vin 2 , the comparator 220 outputs the comparison signal COMP at a high level.
  • the sense amplification activation signal generator 240 includes four inverters INV 14 to INV 17 , which have the same or similar sizes and speeds as do inverters INV 1 to INV 4 in FIG. 2 .
  • the generator 240 asserts signals LAPG′ and LANG′ in response to a row active command signal.
  • the signals LAPG′ and LANG′ have the same slopes (the first slope) as those from the generator in FIG. 2 when a stable power supply voltage at the nominal level is used.
  • the first delay 260 includes two PMOS transistors MP 4 and MP 5 , two NMOS transistors MN 8 and MN 9 , two resistors R 5 and R 6 , and an inverter INV 18 connected as illustrated in FIG. 9 .
  • the second delay 280 includes two PMOS transistors MP 6 and MP 7 , two NMOS transistors MN 10 and MN 11 , two resistors R 7 and R 8 , and an inverter INV 19 connected as illustrated in FIG. 9 .
  • the slopes (or rise/fall time) of the signals LAPG′ and LANG′ are not changed. This means that the signals LAPG′ and LANG′ have the first slope, respectively.
  • the comparison signal COMP is at a high level, the PMOS and NMOS transistors MP 4 and MN 9 of the first delay 260 and the PMOS and NMOS transistors MN 6 and MN 11 of the second delay 280 are off.
  • the slopes (or rise/fall time) of the signals LAPG′ and LANG′ become slower (this means that the signals LAPG′ and LANG′ have the second slope).
  • one of the bit lines of each pair changes to a voltage higher than the precharge voltage (e.g., VCC/2), while the other thereof remains at the precharge voltage.
  • One of the PMOS transistors MP 1 and MP 2 and one of the NMOS transistors MN 1 and MN 2 of each sense amplifier circuit 16 turns on according to the bit line voltages.
  • the sense amplification activation signal generating circuit 200 generates the sense amplification activation signals LAPG and LANG of either the first slope or the second slope according to the power supply voltage level (external or internal power supply voltage level), as will be more fully described below.
  • the sense amplification activation signal generator 240 yields the signals LAPG′ and LANG′ in response to a row active command signal. If the power supply voltage is higher than the nominal voltage, the voltage comparator 220 of FIG. 9 generates the comparison signal COMP of a high level. This turns off the PMOS and NMOS transistors MP 4 and MN 9 of the first delay 240 and the PMOS transistor and NMOS transistors MP 6 and MN 11 of the second delay 260 . With transistors MP 4 , MN 9 , MP 6 , and MN 11 off, the resistors R 5 and R 6 in the delay 260 and the resistors R 7 and R 8 in the delay 280 restrict currents in delays 260 and 280 . Thus, slopes of the signals LAPG and LANG output from delays 260 and 280 are shallower than those of the signals LAPG′ and LANG′.
  • the voltage comparator 220 If the power supply voltage is lower than the reference voltage, the voltage comparator 220 generates the comparison signal COMP of a low level. This turns on the PMOS and NMOS transistors MP 4 and MN 9 of the first delay 240 and the PMOS transistor and NMOS transistors MP 6 and MN 11 of the second delay 260 . As a result, delays 260 and 280 have fast responses, and the slopes of signals LAPG and LANG are the same as the slopes of the signals LAPG′ and LANG′. The slopes of signals LAPG and LANG control the speed of the connection of the signal lines LA and LAB commonly coupled to the sense amplifier circuits 16 to voltages VCCA and VSS via the PMOS and NMOS transistors MP 3 and MN 3 .
US09/612,169 1999-08-12 2000-07-08 Random access memory device capable of minimizing sensing noise Expired - Lifetime US6337823B1 (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6584035B2 (en) 2000-12-28 2003-06-24 Micron Technology, Inc. Supply noise reduction in memory device column selection
US6605929B2 (en) * 2001-01-31 2003-08-12 Nec Corporation Power supply noise sensor
US20040141398A1 (en) * 2003-01-22 2004-07-22 Hyong-Ryol Hwang Semiconductor memory device with a decoupling capacitor
US20090323420A1 (en) * 2008-06-27 2009-12-31 Seungpil Lee Minimizing power noise during sensing in memory device
US20090323421A1 (en) * 2008-06-27 2009-12-31 Seungpil Lee Memory device with power noise minimization during sensing
US9257154B2 (en) 2012-11-29 2016-02-09 Micron Technology, Inc. Methods and apparatuses for compensating for source voltage

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027324A (en) * 1989-06-10 1991-06-25 Samsung Electronics Co., Ltd. Sense amplifier driver for use in memory device
US5491435A (en) * 1993-11-17 1996-02-13 Samsung Electronics Co., Ltd. Data sensing circuit with additional capacitors for eliminating parasitic capacitance difference between sensing control nodes of sense amplifier
US5544110A (en) * 1994-02-16 1996-08-06 Hyundai Electronics Industries Co. Ltd. Sense amplifier for semiconductor memory device having pull-up and pull-down driving circuits controlled by a power supply voltage detection circuitry
US5638333A (en) * 1994-06-10 1997-06-10 Samsung Electronics Co., Ltd. Bit line sensing circuit and method of a semiconductor memory device
US5646899A (en) * 1994-12-20 1997-07-08 Samsung Electronics Co., Ltd. Bit line sensing circuit of a semiconductor memory device
US5646900A (en) * 1995-01-12 1997-07-08 Mitsubishi Denki Kabushiki Kaisha Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device
US6205068B1 (en) * 1998-07-13 2001-03-20 Samsung Electronics, Co., Ltd. Dynamic random access memory device having a divided precharge control scheme

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970003710B1 (ko) * 1987-09-04 1997-03-21 미다 가쓰시게 저잡음 반도체 메모리
US5870343A (en) * 1998-04-06 1999-02-09 Vanguard International Semiconductor Corporation DRAM sensing scheme for eliminating bit-line coupling noise

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027324A (en) * 1989-06-10 1991-06-25 Samsung Electronics Co., Ltd. Sense amplifier driver for use in memory device
US5491435A (en) * 1993-11-17 1996-02-13 Samsung Electronics Co., Ltd. Data sensing circuit with additional capacitors for eliminating parasitic capacitance difference between sensing control nodes of sense amplifier
US5544110A (en) * 1994-02-16 1996-08-06 Hyundai Electronics Industries Co. Ltd. Sense amplifier for semiconductor memory device having pull-up and pull-down driving circuits controlled by a power supply voltage detection circuitry
US5638333A (en) * 1994-06-10 1997-06-10 Samsung Electronics Co., Ltd. Bit line sensing circuit and method of a semiconductor memory device
US5646899A (en) * 1994-12-20 1997-07-08 Samsung Electronics Co., Ltd. Bit line sensing circuit of a semiconductor memory device
US5646900A (en) * 1995-01-12 1997-07-08 Mitsubishi Denki Kabushiki Kaisha Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device
US6205068B1 (en) * 1998-07-13 2001-03-20 Samsung Electronics, Co., Ltd. Dynamic random access memory device having a divided precharge control scheme

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6584035B2 (en) 2000-12-28 2003-06-24 Micron Technology, Inc. Supply noise reduction in memory device column selection
US6605929B2 (en) * 2001-01-31 2003-08-12 Nec Corporation Power supply noise sensor
US20040141398A1 (en) * 2003-01-22 2004-07-22 Hyong-Ryol Hwang Semiconductor memory device with a decoupling capacitor
US7002872B2 (en) 2003-01-22 2006-02-21 Samsung Electronics Co., Ltd. Semiconductor memory device with a decoupling capacitor
US20090323420A1 (en) * 2008-06-27 2009-12-31 Seungpil Lee Minimizing power noise during sensing in memory device
US20090323421A1 (en) * 2008-06-27 2009-12-31 Seungpil Lee Memory device with power noise minimization during sensing
US7751250B2 (en) 2008-06-27 2010-07-06 Sandisk Corporation Memory device with power noise minimization during sensing
US7751249B2 (en) 2008-06-27 2010-07-06 Sandisk Corporation Minimizing power noise during sensing in memory device
US9257154B2 (en) 2012-11-29 2016-02-09 Micron Technology, Inc. Methods and apparatuses for compensating for source voltage
US9595303B2 (en) 2012-11-29 2017-03-14 Micron Technology, Inc. Methods and apparatuses for compensating for source voltage
US10204663B2 (en) 2012-11-29 2019-02-12 Micron Technology, Inc. Methods and apparatuses for compensating for source voltage
US10665272B2 (en) 2012-11-29 2020-05-26 Micron Technology, Inc. Methods and apparatuses for compensating for source voltage

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US20020057613A1 (en) 2002-05-16
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