US6110781A - Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices - Google Patents

Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices Download PDF

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US6110781A
US6110781A US09/115,305 US11530598A US6110781A US 6110781 A US6110781 A US 6110781A US 11530598 A US11530598 A US 11530598A US 6110781 A US6110781 A US 6110781A
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silicon
etching
layer
silicon oxide
process according
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Felice Russo
Giuseppe Miccoli
Alessandro Torsi
Koteswara Rao Chintapalli
Giuseppe Cautiero
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • This invention broadly relates to an improvement to a anisotropic chemical etching process of silicon oxide.
  • this invention relates to a process of the above kind in which a layer of silicon nitride is isotropically deposited on the silicon oxide and is eventually oxidised after deposition, in order to increase the anisotropy of a subsequent anisotropic chemical etching stage of the silicon oxide.
  • Flash EPROM electrically programmable, non-volatile memories
  • FMOS floating gate avalanche injection MOS transistors
  • FAMOS transistors Flash EPROM memory devices Such need is particularly severe in the production of FAMOS transistors Flash EPROM memory devices, since said FAMOS transistors are substantially constituted by MOS transistors having their gate region insulated with respect to its external environment.
  • the manufacturing process of a FAMOS transistor preferably is carried out by performing the following steps.
  • a thin layer of silicon dioxide designated as “Tunnel Oxide” or “Gate Oxide” is grown on the whole substrate, which is already provided with straight parallel sectors having a thick layer of silicon dioxide, designated as “Field Oxide”, grown thereupon.
  • a layer of poly-crystalline silicon (or polysilicon), designated as "poly-1" is deposited upon said Tunnel Oxide" and it is subsequently doped, for instance with phosphorous, in order to make it even more conductive. Said poly-1 forms the floating gate region.
  • An electrically insulating three-layer silicon structure (oxidenitride-oxide: SiO 2 --Si 3 N 4 --SiO 2 ), designated as "ONO", is subsequently deposited upon said poly-1 layer.
  • a layer of polysilicon designated as "poly-2" is deposited upon said ONO layer and it is subsequently doped, for instance again with phosphorous, and lastly a metal layer of tungsten silicide (WSi) is deposited upon said poly-2 layer.
  • WSi tungsten silicide
  • a photolithographic process is carried out to define the length of the FAMOS transistor cell and a suitable plasma-assisted chemical etching step, also designated as "stack etch” step etches the stack of silicide, poly-2, ONO and poly-1 layers and removes them wherever necessary, up to the tunnel oxide layer where the etching operation is stopped and in this way it defines the sizes of the gate stacks of the concerned FAMOS transistors and consequently the sizes of the cells.
  • a thermal "annealing” treatment is performed under oxygen atmosphere in order to cause a thin layer of oxygen dioxide to grow on the whole exposed surfaces of the gate stacks, thereby creating in particular the oxide barrier on the side walls of the poly-1 layer, as it is necessary to prevent any leakage of the charge stored in the floating gate regions toward the poly-2, drain and source regions.
  • the process provides for defining the areas constituting the connection lines of the source regions upon which the thin layers of said tunnel oxide and the thick layers of said field oxide are alternatively applied, by means of a photolithographic process. Such areas are then subjected to an anisotropic, plasma assisted, chemical etching operation of the oxide, designated as "Self Aligned Source (SAS) etch", aimed at exposing the underlying substrate to the subsequent operation of the dopant agent implantation.
  • SAS Self Aligned Source
  • the subsequent chemical treatment steps of the devices provide for doping the drain regions, by means of an implantation operation through the gate oxide acting as a shield, and subsequently for metallising and passivating the so manufactured devices.
  • DRL figure An important parameter to evaluate the quality of a Flash EPROM memory is the so called “Data Retention Loss", also known as DRL figure. Said DRL figure is quantitatively expressed by checking the capability of the concerned memory device to retain test data upon being subjected to highly stressing treatment.
  • an oxide layer be provided on the side walls of the poly-1 layer as well as that a gate oxide layer be maintained at the base of the gate stack.
  • the maintainment of the gate oxide at the base of the gate stack also allows to obtain a higher immunity or sturdiness in respect of any electric noise between contiguous cells, thereby avoiding spurious deletion and/or write effects.
  • interstitial silicon atoms are very rapidly diffused to such extent as to agglomerate upon already existing defects, thereby causing the formation of dislocations, also designated as "stacking faults" which, in turn, cause the formation of short circuits between the source and drain regions.
  • the object of this invention therefore, to enhance the anisotropy of a chemical etching process, possibly a plasma assisted process, if desired, of silicon oxide, in order to enable, in simple and reliable way, in a manufacturing process of FAMOS transistor Flash EPROM memory devices, the oxide layer to be maintained on the side walls of the poly-1 layer as well as the tunnel oxide to be maintained at the bottom of the gate stack, so as to minimise the DRL figure and improve the insensitivity to electric noise among the memory cells, without modifying the FAMOS transistor characteristics.
  • Specific subject-matter of this invention is an improvement to the anisotropic chemical etching process of silicon oxide, having an etching direction, characterised in that the following steps are performed:
  • a first anisotropic chemical etching or break-through stage along said etching direction, aimed at removing the nitride layer from the silicon oxide surfaces orthogonal to said etching direction;
  • a second anisotropic chemical etching stage along said etching direction, aimed at removing the silicon oxide surfaces orthogonal to said etching direction.
  • said process can also provide, after said preliminary deposition step of a silicon nitride layer, a surface oxidisation step of said silicon nitride layer, in aqueous vapour, preferably at a temperature lower than the temperatures at which the thermal oxidisation of the silicon and the diffusion of the dopants are performed.
  • said preliminary deposition operation is a plasma-assisted chemical vapour deposition (PCVD) or a low-pressure chemical vapour deposition (LPCVP) or an energy-enhanced chemical vapour deposition and it takes place at a temperature lower than the temperatures at which the thermal oxidisation of the silicon and the diffusion of the dopants are performed.
  • PCVD plasma-assisted chemical vapour deposition
  • LPCVP low-pressure chemical vapour deposition
  • a first set of chemical-physical treatment steps for forming the gate stacks of said FAMOS transistors ending with an anisotropic chemical etching step, possibly plasma assisted, or stack etch step, aimed at defining the dimensions of said gate stacks and with an annealing step, under oxygen atmosphere, aimed at growing a thin layer of silicon oxide on the whole exposed surfaces of said gate stacks, and
  • a first anisotropic chemical etching operation possibly plasma assisted, or break-through step, having such an etching direction as to remove the nitride layer from said source line forming areas,
  • FIG. 1 is schematic fragmentary plan view of a FAMOS transistor memory device, before the SAS etch step in the manufacturing process;
  • FIG. 2 is a front elevation cross-section view of a device according to FIG. 1, before the SAS etch step in a conventional manufacturing process;
  • FIG. 3 is a front elevation cross-section view of a device according to FIG. 1, after the SAS etch step in conventional manufacturing process;
  • FIG. 4 is a front elevation cross-section view of a device according to FIG. 1, before the SAS etch step of the manufacturing process according to this invention.
  • FIG. 5 is a front elevation cross-section view of a device according to FIG. 1 after the SAS etch step of the manufacturing process according to this invention.
  • a FAMOS transistor Flash EPROM memory device includes horizontal parallel sectors 1 having the thick oxide layer or so-called Field Oxide grown thereupon and arranged in such a way as to separate from one another the horizontal sectors 2 upon which the FAMOS transistor cells are manufactured.
  • Said FAMOS transistor cells are centrally provided with a gate stack 3 which is laid upon the substrate channel separating the drain region 4 and the source region 5.
  • Vertical sectors 6 constitute the source lines. Each source line is so designed as to connect the various source regions 5 belonging to it in short circuit, in order to form the common source line for a word of the memory device. Aiming at forming this connection, as previously described, the local oxide is to be removed from each of said vertical sectors 6, by performing said SAS etch step, and the necessary dopant agent is to be implanted therein.
  • FIG. 2 A cross-section view along line A-A' of FIG. 1 is shown in FIG. 2, in respect of a horizontal sector 2 of a device manufactured according to a conventional process, before the SAS etch step.
  • a layer 7 of poly-1, a layer 8 of ONO, a layer 9 of poly-2 and a layer 10 of silicide can be observed within the gate stack 3.
  • the annealing step carried out after the stack etch step causes a thin layer 11 of silicon dioxide to grow around the gate stack 3.
  • a protection layer 12 of "resist” is shown in dashed line in the Figure, said protection layer being patterned according to photolithographic techniques, the resolution limits of which do not allow a perfect alignment to the edge of the gate stack 3 to be achieved. It is also possible to observe the Tunnel Oxide layer 13.
  • FIG. 3 A cross-section view of FIG. 2 is shown in FIG. 3, after having performed the SAS etch step according to a conventional manufacturing process. It can be observed that the removal of the Tunnel Oxide layer 13 (as well as of the Field Oxide layer) exposes the silicon substrate portion 14 corresponding to the source region (and line).
  • the oxide layer 11 existing on the side walls of the gate stack, on the side of the source region 5 appears to have been at least partially etched and particularly it appears to have been completely removed at the top section 15 and to have been noticeably thinned at the bottom section 16 of the walls, with respect to the side of the drain region 4.
  • the approach suggested according to this invention provides for depositing a thin layer 17 of silicon nitride (Si 3 N 4 ) on the whole device being manufactured, said deposition being carried out after said annealing step subsequent to the stack etch step and before the photolithographic step by which the source lines are defined.
  • the surface of such layer 17 of silicon nitride can be oxidised, in order to form silicon oxi-nitride.
  • Such oxidisation operation improves the characteristics of the concerned nitride in view of the subsequent chemical etching treatment and of the magnetic permeability.
  • the SAS etching step aimed at etching the source line oxide is preceded by a plasma-assisted anisotropic chemical etching operation, of very short duration, intended to remove the nitox layer from the horizontal surfaces, so as to expose the source lines to the subsequent SAS etch step.
  • a plasma-assisted anisotropic chemical etching operation of very short duration, intended to remove the nitox layer from the horizontal surfaces, so as to expose the source lines to the subsequent SAS etch step.
  • Such a chemical etching operation applied to the nitox layer also designated as "break-through” operation has a very short duration and sufficient anisotropic properties as not to substantially etch the nitox layer on the vertical walls.
  • said SAS etching operation is designed so as to be extremely selective in respect of the nitox layer 17 and to rapidly etch the silicon oxide.
  • the oxide etching rate therefore, is extremely higher than the nitox etching rate.
  • FIG. 5 shows the results obtained by means of a SAS etching operation carried out by low performance equipment and, therefore, it illustrates a particularly negative case.
  • higher performance apparatuses it is possible to obtain a protection of the concerned oxide layer 11 on the whole side wall of the gate stack 3 and on the top section 15, as well.
  • the above illustrated nitox layer 17 is adapted to protect the oxide layer 11 on the side wall of the gate stack 3 even when the stack etch operation creates a not-sharp and tilted profile of said gate stack 3, thereby reducing the sensitivity of the manufacturing process of these devices to the possible variations of the stack etch step performances, namely enhancing the tolerance figure of the process in respect of such variations and increasing in this way the sturdiness of the process.
  • the above said nitox layer 17 obviously also protects the base portion 16 of the gate stack 3 and thus prevents the Tunnel Oxide layer 13 from being etched away from below the stack itself. By maintaining such portion of said Tunnel Oxide layer 13 in integral condition, an increase in immunity to electric noise caused by write or delete operations in adjacent cells is achieved.
  • the impact on the characteristics of the FAMOS transistor cells is also easily controllable.
  • the increase in the length of the transistor channel, as caused by the thickness of said nitox layer 17, can be easily balanced for instance by extending the diffusion times of the implanted dopant agents or by reducing the thickness of the oxide grown during the annealing operation carried out subsequently to the stack etch step.
  • the temperatures at which the deposition of nitride and its oxidisation in aqueous vapour are carried out are significantly lower than the temperatures at which the thermal oxidisation and dopant diffusion operations are performed. In view of this, said temperatures have a substantially negligible impact on the device being manufactured, because the sole doped regions existing before the SAS etch step are geometrically extended and have a low dopant concentration, as well.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Silicon Compounds (AREA)
  • Semiconductor Memories (AREA)
US09/115,305 1997-07-14 1998-07-14 Anisotropic chemical etching process of silicon oxide in the manufacture of MOS transistor flash EPROM devices Expired - Lifetime US6110781A (en)

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IT97RM000430A IT1293535B1 (it) 1997-07-14 1997-07-14 Perfezionamento nel procedimento di attacco chimico anisotropo dell'ossido di silicio, in particolare nella fabbricazione di
ITRM97A0430 1997-07-14

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US (1) US6110781A (enrdf_load_stackoverflow)
EP (1) EP0893820A3 (enrdf_load_stackoverflow)
KR (1) KR19990013849A (enrdf_load_stackoverflow)
IT (1) IT1293535B1 (enrdf_load_stackoverflow)
SG (1) SG71131A1 (enrdf_load_stackoverflow)
TW (1) TW480620B (enrdf_load_stackoverflow)

Cited By (2)

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KR101024252B1 (ko) * 2003-10-30 2011-03-29 주식회사 하이닉스반도체 반도체소자 제조 방법
CN105070718A (zh) * 2015-08-18 2015-11-18 上海华虹宏力半导体制造有限公司 一种降低sonos存储器串联电阻的方法

Families Citing this family (3)

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KR100607322B1 (ko) * 1999-06-30 2006-07-28 주식회사 하이닉스반도체 플래쉬 이이피롬 셀의 제조 방법
JP4149644B2 (ja) * 2000-08-11 2008-09-10 株式会社東芝 不揮発性半導体記憶装置
US7276755B2 (en) * 2005-05-02 2007-10-02 Advanced Micro Devices, Inc. Integrated circuit and method of manufacture

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US5766992A (en) * 1997-04-11 1998-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure
US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit

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US5275972A (en) * 1990-02-19 1994-01-04 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor integrated circuit device including the self-aligned formation of a contact window
US5019879A (en) * 1990-03-15 1991-05-28 Chiu Te Long Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area
TW203148B (enrdf_load_stackoverflow) * 1991-03-27 1993-04-01 American Telephone & Telegraph
JP3259349B2 (ja) * 1992-06-09 2002-02-25 ソニー株式会社 不揮発性半導体装置及びその製造方法
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US5897360A (en) * 1996-10-21 1999-04-27 Nec Corporation Manufacturing method of semiconductor integrated circuit
US5766992A (en) * 1997-04-11 1998-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101024252B1 (ko) * 2003-10-30 2011-03-29 주식회사 하이닉스반도체 반도체소자 제조 방법
CN105070718A (zh) * 2015-08-18 2015-11-18 上海华虹宏力半导体制造有限公司 一种降低sonos存储器串联电阻的方法
CN105070718B (zh) * 2015-08-18 2019-01-04 上海华虹宏力半导体制造有限公司 一种降低sonos存储器串联电阻的方法

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ITRM970430A0 (enrdf_load_stackoverflow) 1997-07-14
KR19990013849A (ko) 1999-02-25
TW480620B (en) 2002-03-21
IT1293535B1 (it) 1999-03-01
EP0893820A3 (en) 2003-10-29
SG71131A1 (en) 2000-03-21
EP0893820A2 (en) 1999-01-27
ITRM970430A1 (it) 1999-01-14

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