US6046493A - Semiconductor device with special emitter connection - Google Patents

Semiconductor device with special emitter connection Download PDF

Info

Publication number
US6046493A
US6046493A US08/887,980 US88798097A US6046493A US 6046493 A US6046493 A US 6046493A US 88798097 A US88798097 A US 88798097A US 6046493 A US6046493 A US 6046493A
Authority
US
United States
Prior art keywords
emitter
semiconductor device
region
base
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/887,980
Other languages
English (en)
Inventor
Ronald Dekker
Ronald Koster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Morgan Stanley Senior Funding Inc
Hanger Solutions LLC
Original Assignee
US Philips Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Philips Corp filed Critical US Philips Corp
Assigned to U.S. PHILIPS CORPORATION reassignment U.S. PHILIPS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DEKKER, RONALD, KOSTER, RONALD
Application granted granted Critical
Publication of US6046493A publication Critical patent/US6046493A/en
Assigned to NXP B.V. reassignment NXP B.V. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: U.S. PHILIPS CORPORATION
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. SECURITY AGREEMENT Assignors: NXP B.V.
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. reassignment MORGAN STANLEY SENIOR FUNDING, INC. CORRECTIVE ASSIGNMENT TO CORRECT THE RECORDATION COVER SHEET OF THE SECURITY AGREEMENT PREVIOUSLY RECORDED ON REEL 018806 FRAME 0201. ASSIGNOR(S) HEREBY CONFIRMS THE EXECUTION DATE SHOULD BE CHANGED FROM 12/1/2006; 12/7/2006 TO 9/29/2006. Assignors: NXP B.V.
Assigned to CALLAHAN CELLULAR L.L.C. reassignment CALLAHAN CELLULAR L.L.C. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NXP B.V.
Assigned to NXP B.V. reassignment NXP B.V. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC.
Anticipated expiration legal-status Critical
Assigned to NXP B.V. reassignment NXP B.V. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC
Assigned to HANGER SOLUTIONS, LLC reassignment HANGER SOLUTIONS, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTELLECTUAL VENTURES ASSETS 158 LLC
Assigned to INTELLECTUAL VENTURES ASSETS 158 LLC reassignment INTELLECTUAL VENTURES ASSETS 158 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CALLAHAN CELLULAR L.L.C.
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors

Definitions

  • the invention relates to a semiconductor device provided with a semiconductor substrate with a bipolar transistor having a collector region of a first conductivity type, a base region adjoining the collector region and of a second conductivity type opposed to the first, and an elongate emitter region of the first conductivity type adjoining the base region, said collector, base, and emitter regions being provided with conductive tracks which are connected to conductive connection surfaces.
  • the English abstract of Japanese Patent Application 62-269360 discloses a device of the kind mentioned in the opening paragraph in which the substrate forms the collector region.
  • the base and emitter regions are provided with so-called fingers, i.e. the base and emitter regions are each split up into a number of smaller regions which are electrically connected to one another and to the connection surfaces.
  • the known device described has the disadvantage that the transistor cannot easily supply comparatively high powers.
  • the invention has for its object inter alia to counteract the above disadvantage.
  • the device is for this purpose characterized in that the conductive track on the elongate emitter region has a connection to a connection surface for achieving a further electrical connection at each of the two ends of the emitter region.
  • the elongate emitter regions are then connected at both longitudinal ends to connection surfaces for further electrical connections, such as bonding wires or so-called bumps.
  • the bonding wires or bumps in that case connect the emitter of the bipolar transistor to, for example, a lead frame or printed circuit board.
  • An elongate emitter is used in practice because the parasitic capacitances at the ends of the emitter region are minimized in the case of an elongate emitter.
  • a given power can be accommodated in the most efficient manner by means of an elongate emitter region, given a certain available substrate surface area.
  • the invention is based on the recognition that no high powers can be supplied by the known transistor because the maximum emitter length, and accordingly the maximum power which can be applied given a certain substrate surface area is limited by the transport of charge carriers through the conductive tracks on the elongate emitter. Restrictions relating to electromigration in the tracks play a part in this respect.
  • Providing connections at both ends of the emitter region to respective connection surfaces for a further connection has the result that the emitter region can be made longer, because the two-sided connection of the emitter region effectively halves the length of the emitter region. Indeed, the charge carriers need be transported over at most half the emitter length now.
  • the device according to the invention is characterized in that the collector region is connected to a connection surface which is present at a same side of the semiconductor substrate as the connection surfaces of the base and emitter regions, while the semiconductor substrate is of the same conductivity type as the base region.
  • the substrate serves as the collector in the known transistor. This leads to a comparatively high capacitance of the base compared with the collector. This capacitance adversely affects the performance of the transistor.
  • the device can then be given a final mounting on a lead frame with the substrate on an emitter lead.
  • the bonding wires which connect the emitter connection surfaces to the emitter lead may be kept short in that case, which improves the transistor's performance.
  • the base has a somewhat greater capacitance as compared with the emitter, but this capacitance has little influence on the performance.
  • an additional advantage is obtained when the semiconductor substrate is of rectangular shape, and an active region of the transistor is present along a diagonal of the rectangular substrate.
  • active region is here understood to mean that portion of a collector, emitter, and base region of the transistor through which a comparatively large portion of the current runs. The size of the active region may be maximized then.
  • connection surfaces for the emitter region are present on either side of the diagonal in this case. Comparatively much space is available then for these connection surfaces, while in addition the emitter bonding wires have little influence on one another.
  • the device is characterized in that three or more connection surfaces for the emitter region are present.
  • Current levels are high in modern bipolar transistors, which in combination with high operating frequencies has the result that the impedance formed by the self-induction in the emitter bonding wires has a strong influence on the transistor's behavior. The result of this is that a negative feedback effect will arise in the case of a small number of emitter bonding wires, and the high-frequency gain of the transistor will be reduced.
  • a number of three or more connection surfaces for the emitter region renders it possible to provide three or more bonding wires for the electrical connection of the emitter region. Such a number of bonding wires leads to a low impedance of the bonding wires and good high-frequency properties.
  • connection surfaces is comparatively easy to provide owing to the diagonal placement of the active region.
  • Three connection surfaces are sufficient for a transistor with a power of approximately 500 mW, and four connection wires are sufficient for a transistor with a power of approximately 1000 mW.
  • the device according to the invention is characterized in that more than one connection surface for the collector region is present. More than one bonding wire for the collector may be used then, so that the performance of the transistor is not adversely affected by an excessive impedance in the collector connection in the case of comparatively strong currents through the collector.
  • the device according to the invention is characterized in that the transistor is built up symmetrically along a diagonal of the rectangular substrate. Such a symmetrical arrangement of the device is favorable for the thermal stability of the transistor.
  • FIG. 1 is a plan view of a known semiconductor device
  • FIG. 2 is a cross-section taken on the line a-a' in FIG. 1 of a known semiconductor device
  • FIG. 3 is a plan view of a semiconductor device according to the invention.
  • FIG. 4 is a detailed plan view of the region A indicated with a dotted line in FIG. 3, the first metal layer being shown hatched,
  • FIG. 5 is a detailed plan view of the region A indicated with a dotted line in FIG. 3, the contact holes (or vias) in the insulating layer between the first and the second metal layer being shown hatched,
  • FIG. 6 is a detailed plan view of the region A indicated with a dotted line in FIG. 3 with the second metal layer shown hatched,
  • FIG. 7 is a cross-section taken on the line A-A' in FIGS. 4, 5, and 6,
  • FIG. 8 is a cross-section taken on the line B-B' in FIGS. 4, 5, and 6,
  • FIG. 9 is a plan view of the pattern of the first metal layer viewed as in FIG. 3,
  • FIG. 10 is a plan view of the pattern of the vias in the insulating layer between the first and the second metal layer viewed as in FIG. 3,
  • FIG. 11 is a plan view of the pattern of the second metal layer viewed as in FIG. 3, and
  • FIG. 12 is a plan view of a semiconductor device according to the invention in which a semiconductor substrate provided with a bipolar transistor is mounted on a lead frame.
  • FIG. 1 is a plan view and FIG. 2 a cross-section taken on the line a-a' of a known semiconductor device 1 provided with a semiconductor substrate 2 and comprising a bipolar transistor with a collector region 2, 3 of a first conductivity type.
  • the substrate 2 in the known device is a strongly doped n + -type silicon wafer.
  • a more weakly doped n - -type epitaxial layer 3 is provided on this substrate.
  • a base region 4 of a second conductivity type opposed to the first, in this example a p-type, is provided so as to adjoin the collector region 3. This base region 4 adjoins the surface 5 in the present example.
  • the circumference of the base region 4 is indicated with the dotted line in FIG. 1.
  • the dotted line at the same time indicates the so-called active region of the transistor.
  • the base region 4 is provided with an elongate, strongly doped p + -type base contact region 6.
  • the base contact region in this example is split up into a plurality of base contact regions 6.
  • the emitter region in the present example is split up into a plurality of emitter regions 7.
  • An elongate emitter region 7 is used in practice because the parasitic capacitances at the longitudinal end of the emitter region 7 can be minimized in the case of an elongate emitter region 7.
  • the collector region 2, 3 is provided with a conductive layer 8 on a lower side of the substrate 1 which acts as a connection surface C.
  • the base contact region 6 and the emitter region 7 are split up into a plurality of regions, the so-called fingers.
  • the elongate base contact regions 6 and the elongate emitter regions 7 alternate with one another, such that the base contact regions 6 and the emitter regions 7 are connected by means of conductive tracks 10, 11 to conductive connection surfaces B, E, respectively.
  • This known device as described has the disadvantage that the transistor cannot easily supply comparatively high powers given a certain substrate surface area. Thus it is not easy to increase the number or length of the fingers in the transistor shown in FIG. 1. Neither is it possible to provide an additional row of fingers.
  • FIG. 3 is a plan view
  • FIGS. 4, 5, and 6 show details from the plan view of FIG. 3
  • FIGS. 7 and 8 are cross-sections taken on the lines A-A' and B-B' in FIGS. 4, 5, and 6 of a semiconductor device according to the invention.
  • the semiconductor device according to the invention is provided with a semiconductor substrate 2 with a bipolar transistor having a collector region 3 of a first conductivity type.
  • the substrate 2 in this example has a p-type doping and the collector region 3 an n - -type doping.
  • the collector region is electrically connected by means of a buried n + -type layer 30 and an n + -type connection plug 300.
  • a base region 4 of a second conductivity type opposed to the first, in this example a p-type, is provided such that it adjoins the collector region 3. This base region 4 adjoins the surface 5 in the present example.
  • the base region 4 is provided with an elongate, strongly doped p + -type base contact region 6.
  • the base contact region is split up into a plurality of base contact regions 6 in this example.
  • the emitter region is split up into a plurality of emitter regions 7 in the present example.
  • the split-up base contact regions 6 and emitter regions 7 form so-called fingers.
  • the elongate base contact regions 6 and the elongate emitter regions 7 alternate with one another.
  • the base, collector, and emitter regions are connected to respective connection surfaces B, C and E by means of conductive tracks 10, 11, 110, 12, and 120.
  • the semiconductor device utilizes conductive tracks in two metal layers IN1 and IN2 separated by an insulating dielectric 15.
  • FIG. 3 is a plan view of the entire semiconductor device according to this embodiment, both metal layers IN1 and IN2 being shown.
  • the metal layer IN1 here lies below the metal layer IN2.
  • Conductor tracks in the lower metal layer IN1 are shown in broken lines where they end below the metal layer IN2.
  • Conductor tracks in the upper metal layer IN2 are shown in full lines.
  • FIG. 3 only the upper metal layer IN2 is drawn in the active region A, i.e. the region indicated with the dotted line A for reasons of clarity.
  • the semiconductor substrate in this example is of a rectangular shape, and the active region A of the transistor formed by the collector, base, and emitter regions 3, 30, 300, 4, 6, and 7 is present along a diagonal of the rectangular substrate. The size of the active region A can be maximized then.
  • the connections of the collector, base, and emitter regions 300, 6, and 7 to the conductor tracks are shown in the detailed plan views of FIGS. 4, 5, and 6.
  • a plan view as in FIG. 3 with only the first metal layer IN1 being drawn is shown in FIG. 9.
  • a plan view as in FIG. 3 with only the intermetal dielectric 15 and the locations of the vias is shown in FIG. 10.
  • FIG. 11 is a plan view as in FIG. 3 with only the second metal layer IN2.
  • connection surface 3 shows how the base contact regions 6 are connected to the connection surfaces B via conductor track 10 in metal layer IN1 and a conductor track 10 in metal layer IN2.
  • the semiconductor device is further provided with a covering layer 20 and with contact holes at the areas of the connection surface E, B and C.
  • FIG. 12 is a plan view of a semiconductor device according to the invention in which a semiconductor substrate provided with a bipolar transistor is mounted on a lead frame 21, 22, 23.
  • bonding wires 25 connect the emitter connection surfaces E, base connection surfaces B, and collector connection surfaces C of the bipolar transistor to leads 21, 22, 23 of the lead frame.
  • the semiconductor substrate in this example has a rectangular shape, and an active region A of the transistor formed by the collector, base, and emitter regions is arranged along a diagonal of the rectangular substrate.
  • the connection surfaces E for the emitter region 7 are present on either side of the diagonal.
  • FIGS. 3 and 12 show how comparatively much space is available for these connection surfaces E in the semiconductor device according to the invention.
  • connection surfaces E for the emitter region 7 are present, in the present example of a 1000 mW transistor there are four.
  • the four bonding wires 25 provide a low impedance and good high-frequency properties of the electrical connection between connection surfaces E and leads 21 of the lead frame.
  • This number of connection surfaces E is comparatively easy to provide thanks to the diagonal placement of the active region A.
  • More than one connection surface C is present also for the collector region 3, 30, 300, two in this example, so that no problems relating to electromigration in the conductive tracks will occur even in the case of strong collector currents.
  • the transistor according to this example is built up symmetrically along a diagonal of the rectangular substrate. Such a symmetrical construction of the device is favorable for the thermal stability of the transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
US08/887,980 1996-07-03 1997-07-03 Semiconductor device with special emitter connection Expired - Lifetime US6046493A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP962018222 1996-07-03
EP96201822 1996-07-03

Publications (1)

Publication Number Publication Date
US6046493A true US6046493A (en) 2000-04-04

Family

ID=8224128

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/887,980 Expired - Lifetime US6046493A (en) 1996-07-03 1997-07-03 Semiconductor device with special emitter connection

Country Status (6)

Country Link
US (1) US6046493A (de)
EP (1) EP0865670B1 (de)
JP (1) JPH11512235A (de)
KR (1) KR100471520B1 (de)
DE (1) DE69727788T2 (de)
WO (1) WO1998001908A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476495B2 (en) * 2000-12-28 2002-11-05 Rohm Co., Ltd. Transistor which can minimize the DC resistance of the wiring and lead formed on a semiconductor chip

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000075998A1 (en) * 1999-06-03 2000-12-14 Koninklijke Philips Electronics N.V. Connection arrangement for a semiconductor device and method of manufacturing same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58158965A (ja) * 1982-03-17 1983-09-21 Hitachi Ltd 半導体装置
US4656496A (en) * 1985-02-04 1987-04-07 National Semiconductor Corporation Power transistor emitter ballasting
JPS62269360A (ja) * 1986-05-17 1987-11-21 Toshiba Corp 高周波半導体装置
US5414296A (en) * 1992-12-22 1995-05-09 Spectrian, Inc. Venetian blind cell layout for RF power transistor
US5569952A (en) * 1993-10-01 1996-10-29 U.S. Philips Corporation Semiconductor device with a semiconductor element provided in a mesa structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3788500T2 (de) * 1986-10-31 1994-04-28 Nippon Denso Co Bipolarer Halbleitertransistor.
US5204735A (en) * 1988-04-21 1993-04-20 Kabushiki Kaisha Toshiba High-frequency semiconductor device having emitter stabilizing resistor and method of manufacturing the same
US5374844A (en) * 1993-03-25 1994-12-20 Micrel, Inc. Bipolar transistor structure using ballast resistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58158965A (ja) * 1982-03-17 1983-09-21 Hitachi Ltd 半導体装置
US4656496A (en) * 1985-02-04 1987-04-07 National Semiconductor Corporation Power transistor emitter ballasting
JPS62269360A (ja) * 1986-05-17 1987-11-21 Toshiba Corp 高周波半導体装置
US5414296A (en) * 1992-12-22 1995-05-09 Spectrian, Inc. Venetian blind cell layout for RF power transistor
US5569952A (en) * 1993-10-01 1996-10-29 U.S. Philips Corporation Semiconductor device with a semiconductor element provided in a mesa structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476495B2 (en) * 2000-12-28 2002-11-05 Rohm Co., Ltd. Transistor which can minimize the DC resistance of the wiring and lead formed on a semiconductor chip

Also Published As

Publication number Publication date
DE69727788T2 (de) 2004-12-30
WO1998001908A1 (en) 1998-01-15
KR100471520B1 (ko) 2005-04-14
JPH11512235A (ja) 1999-10-19
EP0865670A1 (de) 1998-09-23
EP0865670B1 (de) 2004-02-25
KR19990044370A (ko) 1999-06-25
DE69727788D1 (de) 2004-04-01

Similar Documents

Publication Publication Date Title
JP2922462B2 (ja) 半導体デバイス
KR101264926B1 (ko) 반도체 장치의 제조 방법 및 반도체 장치
US20190122996A1 (en) Semiconductor structure
GB1154805A (en) Monolithic Semiconductor Microcircuits with Improved Means for Connecting Points of Common Potential
US7105910B2 (en) Semiconductor device having SOI construction
US6593628B2 (en) Semiconductor device and method of manufacturing same
US6953981B1 (en) Semiconductor device with deep substrates contacts
US4631570A (en) Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection
US6127716A (en) Heterojunction bipolar transistor and manufacturing method thereof
US3981070A (en) LSI chip construction and method
US6046493A (en) Semiconductor device with special emitter connection
US6897547B2 (en) Semiconductor device including bipolar junction transistor, and production method therefor
US5683919A (en) Transistor and circuit incorporating same
JPH0629376A (ja) 集積回路装置
JP2002110988A (ja) 半導体装置
JP3753498B2 (ja) 半導体装置
JP3600069B2 (ja) 半導体装置
JPH0629466A (ja) 半導体集積回路
JP2002231818A (ja) 半導体集積回路
JPH10173040A (ja) 半導体集積回路装置
JPH03173169A (ja) 寄生電流に対する保護を備えたモノリシック垂直型半導体電力デバイス
JP2004327919A (ja) 半導体装置
JPS6153756A (ja) 半導体装置
JP2003249504A (ja) 半導体装置及びその製造方法
JPS60136362A (ja) 半導体装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: U.S. PHILIPS CORPORATION, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DEKKER, DONALD;KOSTER, RONALD;REEL/FRAME:008919/0977

Effective date: 19970821

Owner name: U.S. PHILIPS CORPORATION, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DEKKER, RONALD;KOSTER, RONALD;REEL/FRAME:008919/0977

Effective date: 19970821

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: NXP B.V., NETHERLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:U.S. PHILIPS CORPORATION;REEL/FRAME:018635/0755

Effective date: 20061127

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., ENGLAND

Free format text: SECURITY AGREEMENT;ASSIGNOR:NXP B.V.;REEL/FRAME:018806/0201

Effective date: 20061201

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., UNITED KINGDO

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE RECORDATION COVER SHEET OF THE SECURITY AGREEMENT PREVIOUSLY RECORDED ON REEL 018806 FRAME 0201. ASSIGNOR(S) HEREBY CONFIRMS THE EXECUTION DATE SHOULD BE CHANGED FROM 12/1/2006; 12/7/2006 TO 9/29/2006;ASSIGNOR:NXP B.V.;REEL/FRAME:026799/0362

Effective date: 20060929

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: CALLAHAN CELLULAR L.L.C., DELAWARE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NXP B.V.;REEL/FRAME:027265/0798

Effective date: 20110926

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: NXP B.V., NETHERLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:028162/0004

Effective date: 20110930

AS Assignment

Owner name: NXP B.V., NETHERLANDS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC;REEL/FRAME:050315/0443

Effective date: 20190903

AS Assignment

Owner name: HANGER SOLUTIONS, LLC, GEORGIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTELLECTUAL VENTURES ASSETS 158 LLC;REEL/FRAME:051486/0425

Effective date: 20191206

AS Assignment

Owner name: INTELLECTUAL VENTURES ASSETS 158 LLC, DELAWARE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CALLAHAN CELLULAR L.L.C.;REEL/FRAME:051727/0155

Effective date: 20191126