US5920784A - Method for manufacturing a buried transistor - Google Patents

Method for manufacturing a buried transistor Download PDF

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Publication number
US5920784A
US5920784A US08/933,839 US93383997A US5920784A US 5920784 A US5920784 A US 5920784A US 93383997 A US93383997 A US 93383997A US 5920784 A US5920784 A US 5920784A
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regions
well
forming
impurities
oxide layer
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US08/933,839
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English (en)
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Woon-kyung Lee
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/60—Peripheral circuit regions
    • H10B20/65—Peripheral circuit regions of memory structures of the ROM only type

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  • the present invention relates generally to a method for manufacturing transistors, and, more particularly, to a method for manufacturing a buried transistor in which the source/drain regions thereof are self-aligned with an insulating film formed on a channel region thereof.
  • a buried transistor is a transistor which is made by forming the source/drain regions thereof prior to forming the gate electrode thereof, in contrast to a conventional transistor, in which the gate electrode is formed first and then used as a mask for formation of the source/drain regions thereof.
  • buried transistors are employed as the transistors constituting the cell array of read only memory devices (ROMs).
  • FIGS. 1A-1G a conventional method for manufacturing buried transistors of a semiconductor memory device (e.g., a ROM) will now be described.
  • a semiconductor memory device e.g., a ROM
  • an N-well 12 and a P-well 14 are formed in a surface region of a semiconductor substrate 10 by using conventional CMOS twin well process technology.
  • a pad oxide film 16 is formed on the upper surface of the semiconductor substrate 10.
  • a silicon nitride (Si 3 N 4 ) film 18 is deposited on the pad oxide film 16.
  • a photoresist layer is formed on the silicon nitride film 18, and then patterned, to thereby provide a patterned photoresist mask 20 having apertures over regions of the substrate 10 where field oxide regions are to be subsequently formed.
  • the portions of the pad oxide film 16 and silicon nitride film 18 underlying the apertures in the photoresist mask 20 are etched away, to thereby expose portions of the upper surface of the semiconductor substrate 10 corresponding to the regions where the field oxide regions are to be subsequently formed.
  • the photoresist mask 20 is removed, and a patterned photoresist mask 22 is formed on the resultant structure.
  • boron ions are ion-implanted in the exposed surface regions of the semiconductor substrate 10, to thereby form channel stop regions 24 in the P-well 14.
  • the photoresist mask 22 is removed, and the resultant structure is exposed to an oxide atmosphere, to thereby form field oxide regions 26 in the surface regions of both the N-well 12 and the P-well 14.
  • impurities are ion-implanted in the resultant structure to control the threshold voltage of the transistors to be subsequently formed in the N-well 12 and the P-well 14.
  • a patterned photoresist mask 28 is formed on the resultant structure depicted in FIG. 1C, and source/drain regions 30 separated from one another by a distance "L" are formed in the cell region of the P-well 14, by ion-implanting N-type impurities into the surface region of the P-well 14, using the photoresist mask 28 as an ion-implantation mask.
  • the photoresist mask 28 is removed, and a patterned photoresist mask 32 is formed on the resultant structure.
  • the photoresist mask 32 exposes only the cell region of the resultant structure.
  • impurities are ion-implanted in the cell region of the P-well 14 to control the threshold voltage of transistors to be formed in the cell region of the P-well 14, using the photoresist mask 32 as an ion-implantation mask.
  • the photoresist mask 32 is removed, and a gate insulation film 34 and a gate electrode layer are sequentially formed on the resultant structure.
  • a patterned photoresist mask 38 is formed on the resultant structure.
  • the gate electrode layer is etched, using the photoresist mask 38 as an etching mask, to thereby form gate electrodes 36.
  • the NMOS memory cell transistors formed in the cell region of the P-well 14 are completed.
  • LDD lightly doped source/drain
  • the source/drain regions of a buried transistor manufactured in accordance with the conventional technology are formed prior to formation of the gate electrode thereof. Consequently, the length "L" of the channel region of the buried transistors formed in the cell region of the semiconductor memory device is determined by the geometries of the photoresist mask 28, and the width of the channel region of the buried transistors formed in the cell region of the device is determined by the width of the gate electrode 36.
  • the reference numeral 3 designates the portion of the source/drain regions 30 which is present before the gate insulation film 34 is formed
  • the reference numeral 6 designates extended portions (OED regions) of the source/drain regions 30 which are formed after the gate insulation film 34 is formed
  • reference numeral 4 designates relatively thin portions of the gate insulation film 34 formed on channel regions of the buried transistors formed in the P-well 14
  • reference numeral 5 designates relatively thick portions of the gate insulation film 34 formed on the source/drain regions 30 of the buried transistors formed in the P-well 14
  • reference numeral 8 designates the encircled channel stop layer 24
  • reference numeral 7 designates the encircled field oxide region 26
  • the reference numeral 9 designates the encircled portion of the gate electrode 36 formed on the cell region of the P-well 14.
  • the effective channel length 1 of the buried transistors formed in the P-well 14 is shortened (and the effective length 2 of the source/drain regions 30 lengthened) due to the formation of the extended portions 6 of the source/drain regions 30 as a consequence of the formation of the gate insulation film 34, which lowers the punch-through voltage of the buried transistors formed in the cell region of the P-well 14.
  • HTO high temperature oxide
  • BPSG layer not shown
  • the portions of the gate insulation film 34 on the source/drain regions 30 have a greater thickness than the portions of the gate insulation film 34 on the channel regions therebetween.
  • impurities e.g., arsenic or phosphorus ions
  • the oxidation enhanced diffusion (OED) regions 6 are formed at the boundaries between the channel region and the source/drain regions of the buried transistors when the gate insulation film 34 is formed, thereby significantly extending the effective length of the source/drain regions 30 of the buried transistors, and, conversely, significantly reducing the effective channel length of the buried transistors.
  • OED oxidation enhanced diffusion
  • the channel length "L" of the buried transistors tends to be shorter and less uniform than desired, thereby further degrading the performance and punch-through voltage characteristics of the buried transistors manufactured in accordance with the conventional technology.
  • the present invention encompasses a method for manufacturing a buried transistor, which includes the steps of forming a field oxide layer in a substrate, the field oxide region having a central portion having a greater thickness than opposite edge portions thereof, forming source/drain regions in the substrate, on opposite sides of the field oxide layer, removing the field oxide layer, and forming a gate electrode on the resultant structure.
  • FIGS. 1A-1G are cross-sectional views depicting successive steps of a conventional method for manufacturing buried transistors
  • FIG. 2 is an enlarged view of a portion (designated II) of the device depicted in FIG. 1G;
  • FIGS. 3A-3F are cross-sectional views depicting successive steps of a method for manufacturing a buried transistor in accordance with a preferred embodiment of the present invention
  • FIG. 4A is an enlarged view of a portion (designated A) of the device depicted in FIG. 3D;
  • FIG. 4B is an enlarged view of a portion (designated B) of the device depicted in FIG. 3F;
  • FIG. 5 is a cross-sectional view depicting an alternative step of the method for manufacturing a buried transistor in accordance with the preferred embodiment of the present invention.
  • the device includes an NMOS region, a PMOS region, and a cell region.
  • an N-well 12 and a P-well 14 are formed in a semiconductor substrate 10, in a conventional manner, e.g., by doping N-type impurities such as arsenic and phosphorus (i.e., pentavalent ions) in the substrate 10 for the N-well 12, and by doping P-type impurities such as boron (i.e., trivalent ions) for the P-well 14.
  • N-type impurities such as arsenic and phosphorus (i.e., pentavalent ions)
  • P-type impurities such as boron (i.e., trivalent ions) for the P-well 14.
  • a pad oxide film 16 is formed on the upper surface of the substrate 10, and a silicon nitride (Si 3 N 4 ) film 18 is formed on the pad oxide film 16.
  • a patterned photoresist mask 44 is formed on the silicon nitride film 18, and then, exposed portions of the silicon nitride film 18 and corresponding, underlying portions of the pad oxide film 16 are etched away, using the photoresist mask 44 as an etching mask.
  • the method of the present invention differs from the conventional method in that, with the method of the present invention, the photolithographic etching process exposes the surface portions of the cell region of the P-well 14 corresponding to channel regions of buried transistors to be subsequently formed in the cell region of the P-well 14, in addition to the surface portions of the N-well 12 and P-well 14 where field oxide regions (i.e., device separation regions) are to be subsequently formed.
  • the photolithographic etching process exposes the surface portions of the cell region of the P-well 14 corresponding to channel regions of buried transistors to be subsequently formed in the cell region of the P-well 14, in addition to the surface portions of the N-well 12 and P-well 14 where field oxide regions (i.e., device separation regions) are to be subsequently formed.
  • the photomask 44 is removed, and a patterned photoresist mask 22 is then formed on the resultant structure.
  • P-type impurities such as boron or other trivalent ions, are ion-implanted in exposed portions of the NMOS region of the P-well 14, using the photomask 22 as an ion-implantation mask, to thereby form channel stop regions 24.
  • the channel stop regions 24 serve to enhance the NMOS device isolation characteristics.
  • the photomask 22 is removed, and then the entire surface of the resultant structure is exposed to an oxide atmosphere, to thereby form field oxide regions 26 in the exposed surface portions of the N-well 12 and P-well 14 and mask oxide regions 56 in the cell region of the P-well 14.
  • the field oxide regions 26 and mask oxide regions 56 are preferably formed by a chemical vapor deposition (CVD) process, so that the central portion thereof is formed thicker than the edge portions thereof.
  • the field oxide regions 26 and mask oxide regions 56 can be thermally grown, e.g., by employing a local oxidation of silicon (LOCOS) process.
  • LOC local oxidation of silicon
  • the method of the present invention differs from the conventional method, in that with the method of the present invention, mask oxide regions 56 are formed in the channel regions of the cell region of the P-well 14, in addition to the field oxide regions 26 formed in the device separation regions of the NMOS region of the P-well 14 and the PMOS region of the N-well 12.
  • impurities of the appropriate conductivity type are preferably ion-implanted in the exposed surface regions of both the N-well 12 and the P-well 14 to controllably adjust the threshold voltage of the buried transistors to be formed therein.
  • a patterned photoresist mask 32 is formed on the resultant structure depicted in FIG. 3C, to cover the PMOS and NMOS regions of the structure, and to expose the cell region of the structure.
  • source/drain regions 46 are formed on opposite sides of the mask oxide regions 56 in the cell region of the P-well 14, e.g., by ion-implanting N-type impurities, such as arsenic, phosphorus, or other pentavalent ions.
  • the source/drain regions 46 are double-diffused regions, whereby two different types of impurities of the same conductivity type (in the present instance, N-type) having different diffusion coefficients, e.g., arsenic and phosphorus ions, are simultaneously, or sequentially, ion-implanted, at preferably different concentrations.
  • two different types of impurities of the same conductivity type in the present instance, N-type
  • different diffusion coefficients e.g., arsenic and phosphorus ions
  • a first type of impurity e.g., arsenic
  • a second type of impurity e.g., phosphorus
  • the first concentration be greater than the second concentration.
  • the source/drain regions 46 are self-aligned with the mask oxide regions 56 in the cell region of the device, and the dimensions of the source/drain regions 46 are determined by the dimensions (i.e., thickness and width) of the mask oxide regions 56. Accordingly, the dimensions (e.g., length) of the channel regions of the buried transistors to be formed in the cell region of the P-well 14 can be easily and precisely controlled by controlling the thickness and width of the mask oxide regions 56.
  • an appropriate type and concentration of impurities e.g., boron ions
  • impurities e.g., boron ions
  • this step can be performed after the mask oxide regions 56 are removed in the step described below.
  • the mask oxide regions 56 in the cell region of the device are removed, e.g., by employing a wet etching process, thereby exposing the channel regions of the buried transistors to be formed in the cell region of the P-well 14.
  • the photomask 32 is removed, and a gate insulation film 48 and a gate electrode layer are sequentially formed on the resultant structure.
  • a patterned photoresist mask (not shown--but like the photomask 38 depicted in FIG. 1F) is formed on the resultant structure.
  • the gate electrode layer is etched, using the photoresist mask as an etching mask, to thereby form gate electrodes 50.
  • the buried NMOS memory cell transistors formed in the cell region of the P-well 14 are completed.
  • the photoresist mask is removed, and low concentration impurities of the appropriate conductivity type (e.g., P-type impurities for the N-well 12 and N-type impurities for the P-well 14) are ion-implanted in the PMOS and NMOS regions of the N-well 12 and P-well 14, on opposite sides of the gate electrodes 50.
  • sidewall spacers 52 are formed on the sidewalls of the gate electrodes 50 in the PMOS and NMOS regions of the N-well 12 and P-well 14.
  • a high concentration of impurities of the appropriate conductivity type are ion-implanted in the PMOS and NMOS regions of the N-well 12 and P-well 14, on opposite sides of the gate electrodes 50, to thereby provide lightly doped drain (LDD)-structure source/drain regions 54, and thereby complete the buried PMOS transistor in the N-well 12 and the buried NMOS transistor in the NMOS region of the P-well 14.
  • LDD lightly doped drain
  • the reference numeral 46a represents the first diffused portion of the double-diffused source/drain regions 46
  • the reference numeral 46b represents the second diffused portion of the double-diffused source/drain regions 46.
  • the first diffused portion 46a is formed by the first ion-implantation step which is performed in forming the double-diffused source/drain regions 46
  • the second diffused portion 46b is formed by the second ion-implantation step which is performed in forming the double-diffused source/drain regions 46.
  • the reference numeral 1 represents the effective length of the channel regions of the buried transistors formed in the cell region of the P-well 14, and the reference numeral 2 represents the effective length of the double-diffused source/drain regions 46 of the buried transistors formed in the cell region of the P-well 14.
  • the upper dotted line in FIG. 4A represents the height of the mask oxide regions 56 when the first diffusion portion 46a of the double-diffused source/drain regions 46 is formed, and the solid line therebeneath represents the height of the mask oxide regions 56 when the second diffusion portion 46b of the double-diffused source/drain regions 46 is formed.
  • the lower dotted line 54 illustrates the majority carrier concentration profile.
  • the double-diffused source/drain regions 46 of the buried transistors do not have extended portions (OED regions) which reduce the effective channel length of the channel regions and increase the effective channel length of the source/drain regions, such as do the buried transistors made by the conventional method discussed hereinbefore. Additionally, the concentration of majority carriers is closer to the surface in the channel regions of the buried transistors made by the method of the present invention, and, consequently, the impurity concentration of the source/drain depletion regions is increased, thereby increasing the punch-through voltage of the buried transistors.
  • the alternative embodiment differs from the above-described preferred embodiment only with respect to the sequence of the formation of the channel stop regions 24 and field oxide regions 26. More particularly, in the alternative embodiment, the channel stop regions 24 are formed after the field oxide regions 26 are formed, whereas, in the preferred embodiment, the channel stop regions 24 are formed before the field oxide regions 26 are formed.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US08/933,839 1994-06-08 1997-09-19 Method for manufacturing a buried transistor Expired - Lifetime US5920784A (en)

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KR1019940012852A KR0126789B1 (ko) 1994-06-08 1994-06-08 매몰형 트랜지스터 제조방법
KR94-12852 1994-06-08
US48298695A 1995-06-07 1995-06-07
US08/933,839 US5920784A (en) 1994-06-08 1997-09-19 Method for manufacturing a buried transistor

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291308B1 (en) * 1998-08-14 2001-09-18 Samsung Electronics Co., Ltd. Mask ROM fabrication method
US6566203B2 (en) * 2001-02-23 2003-05-20 Macronix International Co. Ltd. Method for preventing electron secondary injection in a pocket implantation process
US6573574B2 (en) * 2000-02-24 2003-06-03 Samsung Electronics Co., Ltd. Cell array region of a NOR-type mask ROM device and fabricating method therefor
US6617258B1 (en) * 2001-07-23 2003-09-09 Advanced Micro Devices, Inc. Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same

Citations (12)

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Publication number Priority date Publication date Assignee Title
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
JPS5696865A (en) * 1979-12-30 1981-08-05 Fujitsu Ltd Manufacture of semiconductor device
US5091324A (en) * 1990-08-10 1992-02-25 Advanced Micro Devices, Inc. Process for producing optimum intrinsic, long channel, and short channel mos devices in vlsi structures
US5234859A (en) * 1988-06-28 1993-08-10 Mitsubishi Denki Kabushiki Kaisha LOCOS type field isolating film and semiconductor memory device formed therewith
US5328859A (en) * 1993-01-04 1994-07-12 Xerox Corporation Method of making high voltage PNP bipolar transistor in CMOS
US5332682A (en) * 1990-08-31 1994-07-26 Micron Semiconductor, Inc. Local encroachment reduction
US5342796A (en) * 1991-05-28 1994-08-30 Sharp Kabushiki Kaisha Method for controlling gate size for semiconduction process
US5453391A (en) * 1992-01-22 1995-09-26 Macronix International Co., Ltd. Method for manufacturing a contactless floating gate transistor array
US5453395A (en) * 1994-03-21 1995-09-26 United Microelectronics Corp. Isolation technology using liquid phase deposition
US5470774A (en) * 1993-10-08 1995-11-28 Nec Corporation Fabrication method of a read-only semiconductor memory device
US5480823A (en) * 1995-01-19 1996-01-02 United Microelectronics Corporation Method of making high density ROM, without using a code implant
US5536670A (en) * 1994-08-09 1996-07-16 United Microelectronics Corporation Process for making a buried bit line memory cell

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4013489A (en) * 1976-02-10 1977-03-22 Intel Corporation Process for forming a low resistance interconnect in MOS N-channel silicon gate integrated circuit
JPS5696865A (en) * 1979-12-30 1981-08-05 Fujitsu Ltd Manufacture of semiconductor device
US5234859A (en) * 1988-06-28 1993-08-10 Mitsubishi Denki Kabushiki Kaisha LOCOS type field isolating film and semiconductor memory device formed therewith
US5091324A (en) * 1990-08-10 1992-02-25 Advanced Micro Devices, Inc. Process for producing optimum intrinsic, long channel, and short channel mos devices in vlsi structures
US5332682A (en) * 1990-08-31 1994-07-26 Micron Semiconductor, Inc. Local encroachment reduction
US5342796A (en) * 1991-05-28 1994-08-30 Sharp Kabushiki Kaisha Method for controlling gate size for semiconduction process
US5453391A (en) * 1992-01-22 1995-09-26 Macronix International Co., Ltd. Method for manufacturing a contactless floating gate transistor array
US5328859A (en) * 1993-01-04 1994-07-12 Xerox Corporation Method of making high voltage PNP bipolar transistor in CMOS
US5470774A (en) * 1993-10-08 1995-11-28 Nec Corporation Fabrication method of a read-only semiconductor memory device
US5453395A (en) * 1994-03-21 1995-09-26 United Microelectronics Corp. Isolation technology using liquid phase deposition
US5536670A (en) * 1994-08-09 1996-07-16 United Microelectronics Corporation Process for making a buried bit line memory cell
US5480823A (en) * 1995-01-19 1996-01-02 United Microelectronics Corporation Method of making high density ROM, without using a code implant

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291308B1 (en) * 1998-08-14 2001-09-18 Samsung Electronics Co., Ltd. Mask ROM fabrication method
US6573574B2 (en) * 2000-02-24 2003-06-03 Samsung Electronics Co., Ltd. Cell array region of a NOR-type mask ROM device and fabricating method therefor
US6566203B2 (en) * 2001-02-23 2003-05-20 Macronix International Co. Ltd. Method for preventing electron secondary injection in a pocket implantation process
US6617258B1 (en) * 2001-07-23 2003-09-09 Advanced Micro Devices, Inc. Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same

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JP3494758B2 (ja) 2004-02-09
JPH0846184A (ja) 1996-02-16
KR0126789B1 (ko) 1998-04-02

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