US5904530A - Method of making LDD structure spaced from channel doped region - Google Patents

Method of making LDD structure spaced from channel doped region Download PDF

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Publication number
US5904530A
US5904530A US08/873,949 US87394997A US5904530A US 5904530 A US5904530 A US 5904530A US 87394997 A US87394997 A US 87394997A US 5904530 A US5904530 A US 5904530A
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substrate
region
conductivity type
insulating layer
gate
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Hyung Soon Shin
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MagnaChip Semiconductor Ltd
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Goldstar Electron Co Ltd
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Assigned to MAGNACHIP SEMICONDUCTOR LTD. reassignment MAGNACHIP SEMICONDUCTOR LTD. CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Assignors: US BANK NATIONAL ASSOCIATION
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/299—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations
    • H10D62/307—Channel regions of field-effect devices of FETs of IGFETs having lateral doping variations the doping variations being parallel to the channel lengths
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/018—Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0217—Manufacture or treatment of FETs having insulated gates [IGFET] forming self-aligned punch-through stoppers or threshold implants under gate regions

Definitions

  • the present invention relates to a structure of a MOSFET (metal oxide semiconductor field effect transistor) and a manufacturing method thereof, and more particularly to a MOSFET having a LDD (lightly doped drain) structure which is capable of decreasing hot carrier and doping compensation effects.
  • MOSFET metal oxide semiconductor field effect transistor
  • a MOSFET is a semiconductor element which is made of substantially three portions: a gate; a source region; and a drain region.
  • a MOSFET utilizes the effect that, when a predetermined voltage is applied to the gate, a channel is produced between the source region and the drain region, and thereby electrons may be moved along the channel from the source region to the drain region (in the case of an n-channel type MOSFET).
  • FIGS. 1(a) to 2(b) The structure and manufacturing method and operation of the above-described conventional MOSFET will be described with reference to the FIGS. 1(a) to 2(b) as follows.
  • FIG. 1(a) illustrates gate 2 formed on p-type substrate 1.
  • Gate oxide film 3 is interposed between gate 2 and substrate 1, and high density n-type source region 4 and high density n-type drain region 4a are formed in substrate 1 below the outside edge portions r1 of gate 2 as shown in FIG. 1(a).
  • carrier concentration is abruptly decreased as illustrated in FIG. 1(b) (generally indicated by the dotted line in FIG. 1(b)) at the edge portion r1 of gate 2 (where gate 2 and drain region 4a adjoin each other) when a driving voltage is applied to gate 2, and an abrupt high electric field is formed (generally indicated by the solid line in FIG. 1(b)).
  • hot electrons may be generated at the portion of gate 2 adjoining drain region 4a, and these hot electrons may be trapped by thin gate oxide film 3. Since trapped hot electrons may recombine with positive holes collected at interface between gate oxide film 3 and gate 2, variations in the threshold voltage of the MOSFET or other undesirable effects may occur. This phenomenon is referred to as the hot carrier effect. Since the reliability of the MOSFET may be decreased due to the hot carrier effect, research is being conducted into ways for preventing its occurrence. Although increasing the length of the gate is included among the suggested approaches, increased gate length is somewhat contradictory in that it means retrogressing against the trend for high integration. Therefore, an LDD (lightly doped drain) structure as shown in FIG. 2(c) has been proposed as a method for decreasing the hot carrier effect. An LDD structure is a structure for decreasing the electric field, which exerts a great influence on the hot carrier effect near the drain region.
  • FIGS. 2(a), (b) and (c) illustrate cross sectional views of a manufacturing process of a MOSFET having a conventional LDD structure.
  • gate oxide film 6 is grown on p-type silicon substrate 5.
  • a p-type ion implantation is performed including in what is to be the channel region in order to suppress the threshold voltage of punch through, which can occur with a short channel.
  • polysilicon is formed on gate oxide film 6, and gate 7 is formed by patterning the polysilicon. Thereafter, low density n-type source region 9 and low density n-type drain region 10 for an LDD structure are formed by a low density n-type ion implantation using gate 7 as a mask.
  • a CVD (chemical vapour deposition) oxide film is deposited and etched back, forming side wall oxide films 8 and 8a at side walls of gate 7. Thereafter, high density n-type source region 9a and high density n-type drain region 10a are formed by a high density n-type ion implantation, and thereby a MOSFET of an LDD structure is completed.
  • CVD chemical vapour deposition
  • the MOSFET of such a conventional LDD structure operates as a MOSFET generally similar to that discussed in connection with FIG. 1.
  • low density n-type drain region 10 is formed between gate 7 (and the channel region below) and high density n-type drain 10a, the hot carrier effect could be decreased in that the hot carrier effect increases as the electric field increases, and the electric field is decreased in the structure shown in FIG. 2.
  • the lower the density of the n-type drain region against the p-type channel region a wider depletion region is formed.
  • the higher the density of the p-type channel against the n-type drain region a narrower depletion region is formed.
  • the depletion region is more widely formed, and the electric field is decreased.
  • a p-type ion implantation is performed in the channel region.
  • the density of the p-type channel region against the n-type drain region is higher than the density of the substrate.
  • the increased p-type density in the channel region tends to increase the electric field, and simultaneously the hot carrier effect is increased.
  • the density of n-type source/drain regions should be higher than that of the p-type channel region.
  • the present invention is intended to solve such problems. Accordingly, it is an object of the present invention to provide a structure of MOSFET and its manufacturing method capable of decreasing hot carrier and doping compensation effects.
  • the ion implantation of the channel region for decreasing short channel effects is performed only at a predetermined region within the channel region in a manner isolated from the n-type source/drain regions of low density.
  • FIG. 1(a) is a cross sectional view of a structure of general MOSFET
  • FIG. 1(b) is a diagram illustrating the carrier concentration and electric field in the structure of FIG. 1(a);
  • FIGS. 2(a), (b) and (c) are cross sectional views of a manufacturing process of a conventional MOSFET.
  • FIGS. 3(a), (b), (c), (d) and (e) are cross sectional views of a manufacturing process of a MOSFET according to a preferred embodiment of the present invention.
  • FIGS. 3(a) to (e) The manufacturing process and structure of a MOSFET of the present invention will be described in detail with reference to the accompanying drawings of FIGS. 3(a) to (e) as follows.
  • FIGS. 3(a)-(e) illustrate cross sectional views of a manufacturing process of a preferred embodiment of a MOSFET of the present invention.
  • nitride film 12 is deposited on p-type silicon substrate 11, and a portion of nitride film 12 is eliminated by a photo/etching process.
  • an oxide film is deposited on the overall surface, and then side wall oxide film 13 is formed on the side walls of nitride film 12, portions of oxide film having been eliminated by etching back.
  • An ion implantation of a p-type impurity is performed in a central region of the channel region for preventing short channel effects such as threshold voltage variations or punch through.
  • side wall oxide film 13 is eliminated by etching, and then gate oxide film 14 is formed. Thereafter, a layer of polysilicon is thickly formed over the surface, and gate 15 is formed by an etch back process.
  • nitride film 12 is eliminated by etching, and low density n-type source region 17 and low density n-type drain region 18 for an LDD structure are formed by a low density n-type ion implantation using gate 15 as a mask.
  • an oxide film is deposited on the surface and etched back, thereby forming side wall oxide film 16 on gate 15. Thereafter, high density n-type source region 17a and high density n-type drain region 18a for an LDD structure are formed by a high density n-type ion implantation.
  • a MOSFET according to the present invention thus is completed.
  • a MOSFET according to the present invention has a MOSFET structure in which gate oxide film 14 and gate 15 are formed in turn on a predetermined region of the top side of p-type silicon substrate 11 as shown in FIG. 3(e), side wall oxide films 16 are formed on both side walls of gate oxide film 14 and gate 15, low density n-type source region 17 and low density n-type drain region 18 are formed on substrate 11 below side wall oxide film 16, high density n-type source region 17a and high density n-type drain region 18a are formed on the substrate below the outside edged portions of side wall oxide film 16, and p-type ion implantation layer 19 for preventing short channel effects is formed at the central portion within the channel region below gate 15 isolated from low density n-type source region 17 and low density n-type drain region 18.
  • the depletion region is more widely formed, and thereby the electric field is more decreased and simultaneously the hot carrier effect can also be decreased.
  • the density of the channel region is same as the density of the substrate, the relative difference of the densities between the n-type source/drain regions against the channel region becomes larger, and doping compensation effects are such that the doping of the n-type source/drain regions becomes more stable.
  • junction capacity between the n-type source/drain regions and the channel region can be decreased.
  • mobility of the electrons also may be improved.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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US08/873,949 1991-05-15 1997-06-12 Method of making LDD structure spaced from channel doped region Expired - Lifetime US5904530A (en)

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US08/873,949 US5904530A (en) 1991-05-15 1997-06-12 Method of making LDD structure spaced from channel doped region

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Application Number Priority Date Filing Date Title
KR1019910007882A KR920022553A (ko) 1991-05-15 1991-05-15 Ldd 소자의 구조 및 제조방법
KR7882/19911 1991-05-15
US88308592A 1992-05-15 1992-05-15
US28813594A 1994-08-09 1994-08-09
US59947196A 1996-01-23 1996-01-23
US08/873,949 US5904530A (en) 1991-05-15 1997-06-12 Method of making LDD structure spaced from channel doped region

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JP (1) JPH06204469A (en, 2012)
KR (1) KR920022553A (en, 2012)
DE (1) DE4208537C2 (en, 2012)
TW (1) TW252210B (en, 2012)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6077747A (en) * 1997-08-26 2000-06-20 Nec Corporation Method of manufacturing semiconductor device
US6180468B1 (en) * 1998-10-23 2001-01-30 Advanced Micro Devices Inc. Very low thermal budget channel implant process for semiconductors
US6225173B1 (en) * 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
US6333244B1 (en) 2000-01-26 2001-12-25 Advanced Micro Devices, Inc. CMOS fabrication process with differential rapid thermal anneal scheme
US6355528B1 (en) * 1999-08-11 2002-03-12 Advanced Micro Devices, Inc. Method to form narrow structure using double-damascene process
US6361874B1 (en) 2000-06-20 2002-03-26 Advanced Micro Devices, Inc. Dual amorphization process optimized to reduce gate line over-melt
US6368947B1 (en) 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6420218B1 (en) 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6479356B1 (en) * 1998-07-31 2002-11-12 Mitsubishi Denki Kabushi Kaisha Method of manufacturing a semiconductive device with an enhanced junction breakdown strength
US20020175364A1 (en) * 2001-05-28 2002-11-28 Masayuki Ichige Non-volatile semiconductor memory device with multi-layer gate structure
US6521502B1 (en) 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6566212B1 (en) 1998-11-06 2003-05-20 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit with ultra-shallow source/drain extensions
US6583004B2 (en) 2000-09-18 2003-06-24 Samsung Electronics Co., Ltd. Semiconductor memory device and method for manufacturing the same
US6630386B1 (en) 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US20040036117A1 (en) * 2002-08-26 2004-02-26 Tran Luan C. Semiconductor constructions
US20040238883A1 (en) * 1999-12-03 2004-12-02 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US9184163B1 (en) * 2012-12-28 2015-11-10 Texas Instruments Incorporated Low cost transistors
CN105633156A (zh) * 2015-02-09 2016-06-01 中国科学院微电子研究所 半导体器件及其制造方法
CN111092120A (zh) * 2018-10-24 2020-05-01 长鑫存储技术有限公司 场效应管器件及其制造方法
US10714474B2 (en) * 2011-10-28 2020-07-14 Texas Instruments Incorporated High voltage CMOS with triple gate oxide

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FR2788629B1 (fr) * 1999-01-15 2003-06-20 Commissariat Energie Atomique Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur
JP2000332236A (ja) * 1999-05-18 2000-11-30 Univ Hiroshima 微細化に適した新しい高性能ｍｏｓｆｅｔ
DE19957540B4 (de) 1999-11-30 2005-07-07 Infineon Technologies Ag Verfahren zum Herstellen eines Feldeffekttransistors mit Anti-Punch-Through-Implantationsgebiet
JP2007088488A (ja) * 2006-10-18 2007-04-05 Renesas Technology Corp 電界効果トランジスタ及びその製造方法

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JPH036863A (ja) * 1989-06-05 1991-01-14 Takehide Shirato 半導体装置
US5073512A (en) * 1989-04-21 1991-12-17 Nec Corporation Method of manufacturing insulated gate field effect transistor having a high impurity density region beneath the channel region
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US5082794A (en) * 1989-02-13 1992-01-21 Motorola, Inc. Method of fabricating mos transistors using selective polysilicon deposition
US5073512A (en) * 1989-04-21 1991-12-17 Nec Corporation Method of manufacturing insulated gate field effect transistor having a high impurity density region beneath the channel region
JPH036863A (ja) * 1989-06-05 1991-01-14 Takehide Shirato 半導体装置

Cited By (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6077747A (en) * 1997-08-26 2000-06-20 Nec Corporation Method of manufacturing semiconductor device
US6479356B1 (en) * 1998-07-31 2002-11-12 Mitsubishi Denki Kabushi Kaisha Method of manufacturing a semiconductive device with an enhanced junction breakdown strength
US6180468B1 (en) * 1998-10-23 2001-01-30 Advanced Micro Devices Inc. Very low thermal budget channel implant process for semiconductors
US6225173B1 (en) * 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
US6566212B1 (en) 1998-11-06 2003-05-20 Advanced Micro Devices, Inc. Method of fabricating an integrated circuit with ultra-shallow source/drain extensions
US6355528B1 (en) * 1999-08-11 2002-03-12 Advanced Micro Devices, Inc. Method to form narrow structure using double-damascene process
US7078776B2 (en) * 1999-12-03 2006-07-18 Kabushiki Kaisha Toshiba Low threshold voltage semiconductor device
US20040238883A1 (en) * 1999-12-03 2004-12-02 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6333244B1 (en) 2000-01-26 2001-12-25 Advanced Micro Devices, Inc. CMOS fabrication process with differential rapid thermal anneal scheme
US6420218B1 (en) 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6368947B1 (en) 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
US6361874B1 (en) 2000-06-20 2002-03-26 Advanced Micro Devices, Inc. Dual amorphization process optimized to reduce gate line over-melt
US6630386B1 (en) 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
US6521502B1 (en) 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6600187B2 (en) 2000-09-18 2003-07-29 Samsung Electronics Co., Ltd. Semiconductor memory device and method for manufacturing the same
US6583004B2 (en) 2000-09-18 2003-06-24 Samsung Electronics Co., Ltd. Semiconductor memory device and method for manufacturing the same
US7045423B2 (en) 2001-05-28 2006-05-16 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device with multi-layer gate structure
US20020175364A1 (en) * 2001-05-28 2002-11-28 Masayuki Ichige Non-volatile semiconductor memory device with multi-layer gate structure
US20050104120A1 (en) * 2001-05-28 2005-05-19 Masayuki Ichige Non-volatile semiconductor memory device with multi-layer gate structure
US6853029B2 (en) * 2001-05-28 2005-02-08 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device with multi-layer gate structure
US20050280033A1 (en) * 2002-08-26 2005-12-22 Tran Luan C Semiconductor constructions
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US20040094788A1 (en) * 2002-08-26 2004-05-20 Tran Luan C. Methods of forming semiconductor constructions
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JPH06204469A (ja) 1994-07-22
TW252210B (en, 2012) 1995-07-21
DE4208537A1 (de) 1992-11-19
KR920022553A (ko) 1992-12-19
DE4208537C2 (de) 1997-04-17

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