US5434624A - Apparatus for producing a multi-scene video signal - Google Patents

Apparatus for producing a multi-scene video signal Download PDF

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Publication number
US5434624A
US5434624A US08/183,954 US18395494A US5434624A US 5434624 A US5434624 A US 5434624A US 18395494 A US18395494 A US 18395494A US 5434624 A US5434624 A US 5434624A
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data
signals
memory
address
video
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US08/183,954
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Tuneaki Ishimura
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/222Studio circuitry; Studio devices; Studio equipment
    • H04N5/262Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/2624Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen

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  • This invention relates to an apparatus for producing a multi-scene video signal consisting of a plurality of video signals having different synchronizations respectively so that a plurality of scenes provided by the respective video signals can be simultaneously displayed in one frame.
  • multi-scene video signal producing apparatus indicates such an apparatus which can produce a video signal for simultaneously displaying N ⁇ N scenes (where N is a factor splitting one frame in both the horizontal and vertical directions and is a positive integer larger than and including 2), or the term indicates such an apparatus which can produce a video signal for simultaneously displaying a plurality of scenes in a superposed relation in one frame.
  • N is a factor splitting one frame in both the horizontal and vertical directions and is a positive integer larger than and including 2
  • FIG. 6 shows schematically the structure of a prior art multi-scene video signal producing apparatus.
  • digital video input signals 50, 51, 52 and 53 applied with timing of respectively different phases or frequencies are connected to memories 54, 55, 56 and 57 storing data corresponding to 1/4 of one frame respectively.
  • the video input signals 50 to 53 compressed in their scene sizes to 1/4 of one frame respectively are written in the memories 54 to 57 with their phases or frequencies synchronized with the input timing respectively.
  • the read timing that does not coincide with the write timing
  • the memories 54 to 57 are changed over to read out the data composing one frame size, so that a multi-scene video signal including four scenes in one frame appears at an output terminal 58 of the apparatus.
  • the write timing and the read timing for each of the memories 54 to 57 differ in the phase or frequency.
  • the four video input signals must be written in the large capacity memory with a plurality of timings having different phases or frequencies respectively, and the stored data must then be read out from the memory with read timings different from the write timings respectively, resulting in complexity of the memory read/write access timing. After all, such a large capacity memory could not be used in the prior art apparatus.
  • the positions of individual data are detected on the basis of both data position pulses synchronous with the individual video input signals respectively and memory synchronization pulses synchronous with memory drive pulses, and, on the basis of the result of decoding the data position detection signals, the delayed video input signals and the corresponding delayed addresses are selected by the selectors, so that the video input signals having different synchronizations are converted into the form that can be synchronized with the read timing.
  • a plurality of video input signals can be written in a single large capacity memory, so that a multi-scene video signal producing apparatus which is inexpensive and requires a small number of component parts can be provided.
  • FIG. 1 is a schematic block diagram showing the structure of an embodiment of the multi-scene video signal producing apparatus according to the present invention.
  • FIG. 2 shows that one frame is split into four regions for displaying four scenes respectively.
  • FIG. 3 is a timing chart showing, by way of example, the timing of the video signals, that of the data position pulses and that of the memory synchronization pulses in the embodiment shown in FIG. 1.
  • FIG. 4 is a block diagram showing in detail the structure of the data delay part in the embodiment shown in FIG. 1.
  • FIG. 5 is a circuit diagram showing in detail the structure of the data position detection/holding part in the embodiment shown in FIG. 1.
  • FIG. 6 is a schematic block diagram showing the structure of a prior art multi-scene video signal producing apparatus.
  • FIG. 1 shows the structure of an embodiment of the multi-scene video signal producing apparatus according to the present invention.
  • FIG. 1 shows only those circuits required for producing such a video signal for displaying scenes on upper half regions A and B of one frame when one frame is split into four regions A, B, C and D as shown in FIG. 2.
  • two video input signals for displaying scenes on the upper half regions A and B respectively are connected to a single memory 25.
  • the structure of the circuits for displaying scenes on the lower half regions C and D are similar to those illustrated, so that any detailed description of the latter circuits will be unnecessary.
  • two digital video input signals 1 and 2 having different phases or frequencies with respect to their data timing are connected to data delay parts 3 and 4 respectively, and a plurality of sets of delayed video signals corresponding to the delay times of the data delay parts 3 and 4 appear at the outputs of the data delay parts 3 and 4 to be connected to data selectors 5 and 6 respectively.
  • Address signals 7 and 8 corresponding to the digital video input signals 1 and 2 are produced by timing pulse generators 43 and 44 on the basis of the video input signals 1 and 2 respectively.
  • the address signals 7and 8 are connected to address delay parts 9 and 10 respectively, and a plurality of sets of delayed address signals corresponding to the delay times of the address delay parts 9 and 10 appear at the outputs of the address delay parts 9 and 10 to be connected to address selectors 11 and 12 respectively.
  • the timing pulse generator 43 produces data position pulses 17, 18 and 19 representing the data positions in the delayed video signals. These data position pulses 17 to 19 are connected to a position detection/holding part 13, and corresponding output signals 32, 33 and 34 of the position detection/holding part 13 are connected to a decoder 15.
  • the timing pulse generator 44 produces data position pulses 20, 21 and 22 representing the data positions in the delayed video signals.
  • These data position pulses 20 to 22 are connected to a position detection/holding part 14, and corresponding output signals of the position detection/holding part 14 are connected to a decoder 16.
  • each of the data selectors 5 and 6 selects one of the delayed video signals from the corresponding set of the delayed video signals to apply the selected delayed video signal to a selector/latch 23.
  • the selector/latch 23 selects one of the input signals and applies the selected signal to a data input terminal of the memory 25.
  • each of the address selectors 11 and 12 selects one of the delayed address signals from the corresponding set of the delayed address signals to apply the selected delayed address signal to a selector/latch 24.
  • the selector/latch 24 selects one of the input signals and applies the selected signal to an address terminal of the memory 25.
  • the video data stored in the memory 25 are then read out to appear as the multi-scene video signal from an output circuit 46.
  • the digital video input signal 1 applied to the data delay part 3 is delayed with timing as shown in FIG. 3, and the resultant delayed video signals 27, 28 and 29 are inputted to the data selector 5.
  • the digital video input signal 2 applied to the data delay part 4 is also delayed, and the resultant delayed video signals are inputted to the data selector 6.
  • Each of data (1), (2) and (3) shown in FIG. 3 corresponds to one picture element or a plurality of picture elements, and the delay time ⁇ is equal to the period of a 1/4 picture element or a plurality of picture elements.
  • the address signals 7 and 8 corresponding to the video input signals 1 and 2 are delayed by the address delay parts 9 and 10 by the same amount as that for the video input signals 1 and 2 and are inputted to the address selectors 11 and 12 respectively.
  • FIG. 4 is a block diagram showing in detail the structure of the data delay part 3.
  • the data delay part 3 consists of two flip-flops 30 and 31 whose delay time is ⁇ , so that the three delayed video signals 27 to 29 appear when the video input signal 1 is inputted to the data delay part 3.
  • the data delay part 4 and the address delay parts 9, 10 have a structures similar to that of the data delay part 3. When more than three delayed output signals are required, this requirement can be dealt with by increasing the number of the flip-flops connected in cascade.
  • the data position pulses 17 to 19 corresponding to the delayed video signals 27 to 29 respectively indicate the period where the data is stable. Therefore, in the period where each of the data position pulses 17 to 19 is in its "H" level as shown in FIG. 3, the corresponding delayed video signal is changing and unstable. On the other hand, in the period where each of the data position pulses 17 to 19 is in its "L" level, the corresponding delayed video signal is stable.
  • the period where the data position pulses 17 to 19 are in their "H" level is determined by taking into consideration the data changing period, the set-up time as well as the hold time of each of the selector/latches 23 and 24, etc., and the data position pulses 17 to 19 are used to detect the relation between the phase of the video input signals and that of memory synchronization pulses 26 generated from a memory synchronization pulse generator circuit
  • the selector/latch 23 fetches the delayed video signals.
  • each of the data position pulses are in its "L" level at the time corresponding to the leading edge of the corresponding memory synchronization pulse 26, the data is directly latched by the selector/latch 23.
  • the relation among the phase of the delayed video signal 27, that of the data position pulse 17 and that of the memory synchronization pulse 26 is as shown in FIG. 3, the data cannot be stably latched.
  • the decoder 15 produces a control signal for controlling the data selector 5, and, according to this control signal, the data selector 5 selects one of the delayed video signals, that is, the delayed video signal 28 conforming to the timing of the memory synchronization pulse 26 from the set of the delayed video signals.
  • the address selector 11 selects one of the delayed address signals, that is, the delayed address signal corresponding to the delayed video signal 28 from the set of the delayed address signals.
  • a change in the relation between the phase or frequency of each of the video input signals 1, 2 and that of the memory synchronization pulses 26 may result in the relation between the phase of the data position pulse 18 and that of a memory synchronization pulse 26' as shown in FIG. 3.
  • the data selector 5 selects the delayed video signal 29 according to the control signal outputted from the decoder 15.
  • the delayed address signal is similarly changed over by the address selector 11.
  • FIG. 5 is a circuit diagram showing in detail the structure of the position detection/holding part 13.
  • the position detection/holding part 13 consists of a plurality of flip-flops 35, 36, 37, 38, 39, 40 and a plurality of AND gates 41, 42, and a clear pulse 63 resets the operation of the flip-flops 35, 36 and 37 with a suitable period, for example, that of the horizontal synchronizing signal.
  • the circuit structure of the position detection/holding part 14 is similar to that shown in FIG. 5.
  • the data positions in the video input signals 1 and 2 are detected on the basis of the combination of the data position pulses 17, 18, 19 and the memory synchronization pulses 26, and the combination of the data position pulses 20, 21, 22 and the memory synchronization pulses 26, respectively.
  • the delayed video signals and the delayed address signals synchronous with the clock driving the memory 25 are selected by the data selectors 5, 6 and the address selectors 11, 12, respectively. That is, because the plural video input signals 1 and 2 having different synchronizations are converted into the data synchronous with the clock driving the memory 25, so that the data included in the video input signals 1 and 2 can be written in the single memory 25.
  • the aforementioned embodiment of the present invention has referred to the case where the two video input signals 1 and 2 are applied to the apparatus, it is apparent that the number of the video input signals may be more than two. In such a case, the effect similar to that described above can be exhibited when the number of the data delay parts, that of the data selectors, that of the address delay parts, that of the address selectors, that of the position detection/holding parts and that of the decoders are selected to be more than two.
  • nine video input signals are applied, and nine circuits corresponding to the nine inputs respectively are prepared.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Editing Of Facsimile Originals (AREA)
US08/183,954 1993-01-29 1994-01-19 Apparatus for producing a multi-scene video signal Expired - Lifetime US5434624A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP05013052A JP3137486B2 (ja) 1993-01-29 1993-01-29 多画面分割表示装置
JP5-013052 1993-01-29

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0703706A3 (de) * 1994-09-20 1997-01-15 Toshiba Kk Digitaler Fernsehempfänger
US5633683A (en) * 1994-04-15 1997-05-27 U.S. Philips Corporation Arrangement and method for transmitting and receiving mosaic video signals including sub-pictures for easy selection of a program to be viewed
US5990976A (en) * 1996-03-14 1999-11-23 Matsushita Electric Industrial Co., Ltd. Video image processing apparatus and the method of the same
US6028643A (en) * 1997-09-03 2000-02-22 Colorgraphic Communications Corporation Multiple-screen video adapter with television tuner
US6429903B1 (en) 1997-09-03 2002-08-06 Colorgraphic Communications Corporation Video adapter for supporting at least one television monitor
US6522342B1 (en) 1999-01-27 2003-02-18 Hughes Electronics Corporation Graphical tuning bar for a multi-program data stream
US20070052852A1 (en) * 2005-08-31 2007-03-08 Keisuke Yorioka Motion picture display device
US7757252B1 (en) 1998-07-20 2010-07-13 Thomson Licensing S.A. Navigation system for a multichannel digital television system
US7765568B1 (en) 1999-01-27 2010-07-27 The Directv Group, Inc. Graphical tuning bar
US20110078735A1 (en) * 2009-09-30 2011-03-31 Echostar Technologies L.L.C. Apparatus, systems and methods for rich media electronic program guides
US8073955B1 (en) 1999-01-27 2011-12-06 The Directv Group, Inc. Method and apparatus for tuning used in a broadcast data system
EP3029950A1 (de) 2014-12-03 2016-06-08 Advanced Digital Broadcast S.A. System und Verfahren für Mosaik einer grafischen Benutzeroberfläche

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19847403B4 (de) * 1997-10-22 2004-09-02 Püllen, Rainer Bildaufzeichnungssystem (interaktive Raumbilderfassung)
KR100287728B1 (ko) * 1998-01-17 2001-04-16 구자홍 영상프레임동기화장치및그방법
CA2750047A1 (en) 2009-01-21 2010-07-29 Basilea Pharmaceutica Ag Novel bicyclic antibiotics

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US5016106A (en) * 1988-07-08 1991-05-14 Samsung Electronics Co., Ltd. Image signal processing circuit for producing multiple pictures on a common display screen
US5040067A (en) * 1988-07-06 1991-08-13 Pioneer Electronic Corporation Method and device for processing multiple video signals
US5130801A (en) * 1989-08-23 1992-07-14 Fujitsu Limited Image superimposing apparatus having limited memory requirement
US5161012A (en) * 1988-07-30 1992-11-03 Samsung Electronics Co., Ltd. Multi-screen generation circuit

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US5040067A (en) * 1988-07-06 1991-08-13 Pioneer Electronic Corporation Method and device for processing multiple video signals
US5016106A (en) * 1988-07-08 1991-05-14 Samsung Electronics Co., Ltd. Image signal processing circuit for producing multiple pictures on a common display screen
US5161012A (en) * 1988-07-30 1992-11-03 Samsung Electronics Co., Ltd. Multi-screen generation circuit
US5130801A (en) * 1989-08-23 1992-07-14 Fujitsu Limited Image superimposing apparatus having limited memory requirement

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633683A (en) * 1994-04-15 1997-05-27 U.S. Philips Corporation Arrangement and method for transmitting and receiving mosaic video signals including sub-pictures for easy selection of a program to be viewed
EP0703706A3 (de) * 1994-09-20 1997-01-15 Toshiba Kk Digitaler Fernsehempfänger
US5990976A (en) * 1996-03-14 1999-11-23 Matsushita Electric Industrial Co., Ltd. Video image processing apparatus and the method of the same
US6028643A (en) * 1997-09-03 2000-02-22 Colorgraphic Communications Corporation Multiple-screen video adapter with television tuner
US6100936A (en) * 1997-09-03 2000-08-08 Colorgraphic Communications Corporation Multiple-screen video adapter with television tuner
US6429903B1 (en) 1997-09-03 2002-08-06 Colorgraphic Communications Corporation Video adapter for supporting at least one television monitor
US7757252B1 (en) 1998-07-20 2010-07-13 Thomson Licensing S.A. Navigation system for a multichannel digital television system
US6522342B1 (en) 1999-01-27 2003-02-18 Hughes Electronics Corporation Graphical tuning bar for a multi-program data stream
US7765568B1 (en) 1999-01-27 2010-07-27 The Directv Group, Inc. Graphical tuning bar
US8073955B1 (en) 1999-01-27 2011-12-06 The Directv Group, Inc. Method and apparatus for tuning used in a broadcast data system
US20070052852A1 (en) * 2005-08-31 2007-03-08 Keisuke Yorioka Motion picture display device
US7884882B2 (en) * 2005-08-31 2011-02-08 Panasonic Corporation Motion picture display device
US20110078735A1 (en) * 2009-09-30 2011-03-31 Echostar Technologies L.L.C. Apparatus, systems and methods for rich media electronic program guides
US8448210B2 (en) 2009-09-30 2013-05-21 Echostar Technologies L.L.C. Apparatus, systems and methods for rich media electronic program guides
US9179193B2 (en) 2009-09-30 2015-11-03 Echostar Technologies L.L.C. Apparatus, systems and methods for rich media electronic program guides
US9554159B2 (en) 2009-09-30 2017-01-24 Echostar Technologies L.L.C. Apparatus, systems and methods for rich media electronic program guides
EP3029950A1 (de) 2014-12-03 2016-06-08 Advanced Digital Broadcast S.A. System und Verfahren für Mosaik einer grafischen Benutzeroberfläche

Also Published As

Publication number Publication date
JPH06233185A (ja) 1994-08-19
JP3137486B2 (ja) 2001-02-19
DE4402447C2 (de) 1995-02-23
DE4402447A1 (de) 1994-08-11

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