US4719628A - Method and apparatus for decoding error correction code - Google Patents

Method and apparatus for decoding error correction code Download PDF

Info

Publication number
US4719628A
US4719628A US06/767,783 US76778385A US4719628A US 4719628 A US4719628 A US 4719628A US 76778385 A US76778385 A US 76778385A US 4719628 A US4719628 A US 4719628A
Authority
US
United States
Prior art keywords
error correction
code
correction code
decoding
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US06/767,783
Other languages
English (en)
Inventor
Shinya Ozaki
Kentaro Odaka
Tadashi Fukumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP24052583A external-priority patent/JPH0628343B2/ja
Priority claimed from JP1983198079U external-priority patent/JPS60104947U/ja
Application filed by Sony Corp filed Critical Sony Corp
Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: FUKUMI, TADASHI, ODAKA, KENTARO, OZAKI, SHINYA
Application granted granted Critical
Publication of US4719628A publication Critical patent/US4719628A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/158—Finite field arithmetic processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1525—Determination and particular use of error location polynomials
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909—Product codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H03M13/293—Decoding strategies with erasure setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes

Definitions

  • This invention relates to a method and an apparatus for decoding error correction code.
  • Product codes are well known such that information symbols are arranged in two-dimensional form; error correction codes are encoded for each row and column on the two-dimensional arrangement so that each information symbol is included in two error correction code series.
  • error correction codes are encoded for each row and column on the two-dimensional arrangement so that each information symbol is included in two error correction code series.
  • an error correction code is decoded for each column, and an error correction code can be decoded for each row by employing the decoded information.
  • the decoded information is called a pointer.
  • An object of this invention is to provide a method and an apparatus for decoding error correction codes which enable one to reduce the number of pointers required in decoding as well as the memory space required for pointers and to reduce the number needed for times of reading and writing the pointers.
  • Another object of this invention is to provide a method and an apparatus for decoding error correction codes which enable one to markedly reduce the number of processing steps in dependence upon the fact that the pointers with respect to each row are the same.
  • Still another object of this invention is to provide an apparatus for decoding error correction codes which enables one to reduce the number of calculating steps in an erasure correction.
  • a still further object of this invention is to provide a method for decoding error correction codes which can obtain error values in decoding in dependence upon a simple construction and using a small number of processing steps.
  • the present invention provides a method of decoding error correction code in which first error correction code of (n 1 , k 1 ) (where n 1 denotes the code length) are encoded for every k 1 information symbols in each column of two-dimensional arrangement (k 1 ⁇ k 2 ) and second error correction code of (n 2 , k 2 ) (where n 2 denotes the code length) are encoded for every k 2 information symbols in each row
  • the method for decoding error correction code comprises the steps of storing first pointers formed by decoding the first error correction code in a memory having n 2 bits, storing second pointers formed by decoding the second error correction code in at least a memory having k 1 bits, and evaluating the reliability on the basis of the status of the first and second pointers in outputting the information symbols.
  • a method of decoding error correction codes comprises the steps of storing first pointers formed by decoding the first error correction code in a memory having n 2 bits, implementing erasure correction with respect to each code series of the second error correction code by employing the first pointer and implementing a part of calculations for obtaining error values in the erasure correction only once with respect to each code series of the second error correction code in decoding the second error correction code.
  • an apparatus for decoding error correction code stores a syndrome in a syndrome register and forms an error value with respect to a single symbol by subtracting other error values from a value stored in the syndrome register in correcting a plurality of erroneous symbols.
  • FIG. 1 is a schematic block diagram showing an encoder according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram for assistance in explaining the operation of an embodiment of the present invention.
  • FIG. 3 is a schematic block diagram showing a decoder according to one embodiment of this invention.
  • FIG. 4 is a block diagram showing an embodiment of this invention.
  • FIG. 5 is a block diagram showing an essential portion of an embodiment of this invention.
  • FIG. 6 is a block diagram showing an construction of an embodiment for use with this invention.
  • FIG. 7 is a block diagram for assistance in explaining a processing circuit of FIG. 6.
  • FIG. 1 shows a structure of an encoder for product code.
  • the reference numeral 1 denotes an input terminal
  • the reference numeral 2 denotes a C 2 (the second error correction code) parity generator.
  • the input data from the input terminal 1 are supplied to the C 2 parity generator 2 and one input terminal of a selector 3, and the C 2 parity data formed by the C 2 parity generator 2 are supplied to the other input terminal of the selector 3.
  • the selector 3 repeats k 1 times the operations for selecting (n 2 -k 2 ) parity data after k 2 information symbols are selected. During this operation, the information symbols and the parity data are stored in a RAM (Random Access Memory) 4 in sequence under control of an address controller 5.
  • RAM Random Access Memory
  • the data read out from the RAM 4 are supplied to a C 1 (the first error correction code) parity generator 6 and the one input terminal of a selector 7, and the C 1 parity data formed by the C 1 parity generator 6 are supplied to the other input terminal of the selector 7.
  • the selector 7 selects ((n 1 -k 1 ) ⁇ k 2 ) C 1 parity data after having selected (k 1 ⁇ n 2 ) symbols including the C 2 parity data.
  • the digital data derived from an output terminal 8 of the selector 7 are transmitted or recorded on a magnetic tape (not shown) with a magnetic head, for instance. In this case, it is possible to write again the encoded output once into the RAM 4 and to read it out in a different sequence for recording.
  • FIG. 2 shows a configuration of code formed by the encoder as described above.
  • the information symbols are arranged in two dimensions of (k 1 ⁇ k 2 ).
  • the k 2 information symbols in every lateral direction, that is, in every row of the two-dimensional arrangement, are subjected to encoding process for the C 2 code.
  • the k 1 information symbols in every vertical direction, that is, in every column, are subjected to encoding process for the C 1 code.
  • the C 2 parity data are also encoded into the C 1 code.
  • the C 1 code is, for instance, (n 1 , k 1 ) Reed-Solomon code, by which it is possible to correct errors of up to (n 1 -k 1 )/2 symbols.
  • An error location polynominal ⁇ (z) and an error evaluation polynominal ⁇ (z) are obtained by employing the syndrome S j .
  • Euclid's mutual division method, Varlay-Camp's method, Peterson's method and so on have been proposed.
  • the error value Y i can be obtained on the basis of the error location X i and the error evaluation polynominal ⁇ (z).
  • FIG. 3 shows a configuration of the encoder of this embodiment.
  • the reproduced data are supplied from an input terminal designated by the reference numeral 11 and to a C 1 decoder 12.
  • the C 1 decoder 12 the decoding of the C 1 code is performed. All errors of up to (n 1 -k 1 )/2 symbols are corrected in the C 1 decoding. In the case, however, where the number of errors in a single series of C 1 code is more than or equal to a ( ⁇ (n 1 -k 1 )/2), the C 1 pointers of this series is set to "1", the other pointers are set to "0".
  • the reference numeral 13 denotes a pointer memory for storing the pointers of the C 1 code, which has n 2 bits.
  • the output of the C 1 decoder 12 is stored temporarily in a RAM 14 in sequence under the control of an address controller 15.
  • the output read out from the RAM 14 are supplied to a C 2 decoder 16 to be subjected to the decoding of the C 2 code.
  • the C 2 decoder 16 is supplied with the C 1 pointer from the pointer memory 13. Since the C 1 pointer is common to the all of K 1 series of C 2 code, it is possible to decode the C 2 code in accordance with the same procedure in each series.
  • the C 2 decoder 16 corrects errors of up to (n 2 -k 2 )/2 symbols and generate three kinds of pointers in the C 2 code which is stored in a pointer memory 17.
  • the C 2 pointers with respect to the series is set to "0".
  • the C 2 pointers are set to "1".
  • the C 2 pointers are set to "2". Therefore, the C 2 pointers have 2 bits and the pointer memory 17 has 2K 1 bits.
  • These pointer memories 13 and 17 are disposed separately from the RAM 14 for storing information symbols and parity data in decoding or disposed in common with the RAM 14 by using a part of memory regions of the RAM 14.
  • the C 1 pointer may have 2 bits or more. Further, it is possible to implement the error correction code processing of C 2 code for the C 1 parity, while providing a C 2 pointer memory of (2n 1 ) bits.
  • the interpolation circuit 18 performs the mean value interpolation, for instance.
  • the interpolation circuit 18 is controlled by a control circuit 19 which is supplied with the C 1 pointers and the C 2 pointers from the pointer memories 13 and 17.
  • the output data of the interpolation circuit 18 are derived at an output terminal 20.
  • the control circuit 19 determines by every information symbol whether interpolation is necessary on the basis of the c 1 pointer and c 2 pointer. In FIG. 2, There exist all the combinations of C 1 pointers designated as 13' and C 2 pointers designated as 17'.
  • the reliability of the C 1 pointers is evaluated by the C 2 decoder. For instance, provided that up to 2 symbol errors can be corrected by the C 2 code, if correction by the C 2 code can not be performed in spite of the fact that only one C 1 pointer is "1", it is determined that the reliability of the C 1 pointer is low because the above is abnormal. Even if errors are not corrected by the C 2 code, it is possible to eliminate the necessity of interpolation by providing three kinds (0, 1, 2) of the C 2 pointers and by discriminating the copies of C 1 pointers from all errors.
  • the erasure correction is made where the number of the C 1 pointers is less than or equal to (n 2 -k 2 ) and when the erasure correction is made, the C 2 pointer is set to "0".
  • the decoding of the Reed-Solomon code is performed by calculation of the error location polynominal ⁇ (z) and the error evaluation polynominal ⁇ (z) in every row and by employing syndrome obtained by n 2 symbols in each row.
  • the denominator term can be determined by only the error locations. For instance, provided that the error locations shown by the C 1 pointer are X 1 , X 2 , X 3 , the terms of denominator of the expressions for obtaining the error values Y 1 , Y 2 , Y 3 are:
  • the pointers stored in the pointer memory 13 are the same in all of the K 1 series of the C 2 code. Therefore, it is sufficient to implement the calculation of the denomimator term in the above expression to obtain error value only once with respect to the k i series.
  • FIG. 4 shows the configuration of an error correcting decoder for use with the above mentioned C 1 decoder and C 2 decoder.
  • the received data are supplied to an input terminal designated by the reference numeral 21 and supplied to a delay circuit 22 and a syndrome generating circuit 23.
  • the syndromes formed by the syndrome generating circuit 23 are supplied to an error location and error value calculating circuit 24.
  • the error data from the error location and error value calculating circuit 24 are supplied to an exclusive OR gate 25 and added to the received data from the delay circuit 22 in (mod. 2).
  • the received data from the delay circuit 22 and the error corrected data from the exclusive OR gate 25 are supplied to a selector 26.
  • the selector 26 is controlled by the error location data.
  • the output of the exclusive OR gate 25 is selected by the selector 26 to be derived at an output terminal 27 in place of the received data.
  • FIG. 5 shows a part of the error location and error value calculating circuit 24.
  • the reference numeral 28 denotes a data bus through which data and syndrome and so on are transferred.
  • the reference numeral 29 denotes a syndrome register in which the syndrome S 0 is stored through the data bus 28, a bus buffer 30 and an exclusive OR gate 31.
  • the syndrome S 0 has m bits in the case of Reed-Solomon code on GF(2 m ).
  • the syndrome S 0 from the syndrome register 29 is supplied to the exclusive OR gate 31 and the bus buffer 32.
  • the error value Y 4 is left in the syndrome register 29.
  • the error value Y 4 is outputted to the data bus 28 through the bus buffer 32 to be employed for error correction.
  • FIG. 6 shows another example of hardware for decoding in an erasure correction.
  • a main RAM 35 is connected to the data bus 28 through a writing register 33 and a reading register 34.
  • the syndrome register 29, a working RAM 36 and an operation logic circuit 37 are provided to the data bus 28.
  • n Number of erasure
  • n, X k , S.sub. ⁇ , are known, Y k is unknown.
  • the syndrome includes (n-1) erasures. Therefore, by reducing n by 1, Y n-1 can be obtained: ##EQU19## By this calculation, Y n-1 is obtained and Y n-1 X n-1 .sup. ⁇ is added to each syndrome S as follows:
  • correction code is a product code
  • 30 symbols are arranged in the vertical direction
  • 128 symbols are arranged in the lateral direction
  • the C 1 code is formed to the vertical direction
  • the C 2 code is formed to the lateral direction
  • the erasure corresponds to the location of the C 1 pointers
  • the method as above described has advantages such that it is possible to markedly reduce the number of calculation steps, processing time, hardware load for processing and so on as compared with the conventional method.
  • FIG. 7 a concept as shown in FIG. 7 is adopted.
  • the reference numerals 38, 39, 40 denote registers
  • the reference numeral 41 denotes an adder
  • the reference numeral 42 denotes a multiplier
  • the reference numeral 43 denotes a selector, which are comprise the operation logic 37.
  • S 0 is set to the register 39 38, Y i is set to the register, respectively through the data bus 28 from the syndrome register 29 and the working RAM 36 and so on. S 0 +Y i is outputted from the adder 41 to the data bus 28.
  • X 1 to X n are assumed as erasures
  • X 1 to X n-1 are erasures and X n is an error
  • the number of unknown quantity are (n+1) of Y 1 to Y n and X n .
  • X n can be obtained by using the above ⁇ nnj as follows: ##EQU22## Therefore, the unknown quantity are Y 1 to Y n , and thereafter, these unknown quantity can be obtained in the same way as in the erasure correction.
  • n+1 syndromes of S 1 to S n+1 are necessary, so that n ⁇ d-2.
  • the number of erasures is n-1 ⁇ d-3.
  • the remaining syndromes can be used for checking as in the above case.
  • the pointer areas are required for the total number of data (n 1 , n 2 ) corrsponding to the error correction code.
  • the present invention it is possible to reduce the number of pointers to (n 2 +2n 1 ) and further to reduce the capacity of the memory required in decoding. Further, according to the present invention, it is possible to reduce the number of steps for writing or reading the pointers.
  • the erasure correction in the C 2 decoding is implemented by the use of pointers formed by the C 1 decoding, since the pattern of the pointers with respect to each series of C 2 code is common and a part of the operations to obtain error value become common, it is possible to implement the operation only once. Therefore it is possible to markedly reduce the number of processing steps in decoding and to realize a high-speed in decoding operation.
  • the present invention makes it unnecessary to obtain the whole error values in accordance with complicated error evaluation polynomial in obtaining a plurality of error values, it is possible to obtain one of the error values by a simple construction and to reduce the number of the processing steps.

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Algebra (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Executing Machine-Instructions (AREA)
  • Selective Calling Equipment (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
US06/767,783 1983-12-20 1984-12-19 Method and apparatus for decoding error correction code Expired - Lifetime US4719628A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP58-240525 1983-12-20
JP24052583A JPH0628343B2 (ja) 1983-12-20 1983-12-20 積符号の復号方法
JP58-198079 1983-12-23
JP1983198079U JPS60104947U (ja) 1983-12-23 1983-12-23 エラ−訂正復号器
PCT/JP1984/000603 WO1985002958A1 (en) 1983-12-20 1984-12-19 Method and apparatus for decoding error correction code

Publications (1)

Publication Number Publication Date
US4719628A true US4719628A (en) 1988-01-12

Family

ID=26510757

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/767,783 Expired - Lifetime US4719628A (en) 1983-12-20 1984-12-19 Method and apparatus for decoding error correction code

Country Status (8)

Country Link
US (1) US4719628A (de)
EP (3) EP0387924B1 (de)
KR (1) KR930003997B1 (de)
AT (2) ATE128585T1 (de)
BR (1) BR8407228A (de)
DE (3) DE3486471T2 (de)
HK (1) HK118795A (de)
WO (1) WO1985002958A1 (de)

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988009966A1 (en) * 1987-06-08 1988-12-15 Exabyte Corporation Multiple pass error correction process and apparatus for product codes
US4794602A (en) * 1983-06-17 1988-12-27 Sony Corporation Method for error detection
US4819236A (en) * 1986-01-24 1989-04-04 Sony Corporation Data transmission method suitable for a disc
US4847842A (en) * 1987-11-19 1989-07-11 Scs Telecom, Inc. SM codec method and apparatus
US4849976A (en) * 1987-08-03 1989-07-18 Scs Telecom, Inc. PASM and TASM forward error correction and detection code method and apparatus
US4956709A (en) * 1988-03-11 1990-09-11 Pbs Enterprises, Inc. Forward error correction of data transmitted via television signals
US4972416A (en) * 1987-11-13 1990-11-20 Matsushita Electric Industrial Co., Ltd. Error detection and correction method
US5040179A (en) * 1989-08-18 1991-08-13 Loral Aerospace Corp. High data rate BCH encoder
US5068855A (en) * 1988-07-18 1991-11-26 Canon Kabushiki Kaisha Error correcting method and apparatus
US5107505A (en) * 1988-07-07 1992-04-21 Schlumberger Industries Circuit of encoding and formatting data for rotating head recorders
US5136592A (en) * 1989-06-28 1992-08-04 Digital Equipment Corporation Error detection and correction system for long burst errors
US5231638A (en) * 1989-04-11 1993-07-27 Fujitsu Limited Error correction control apparatus
US5315583A (en) * 1991-04-11 1994-05-24 Usa Digital Radio Method and apparatus for digital audio broadcasting and reception
US5323402A (en) * 1991-02-14 1994-06-21 The Mitre Corporation Programmable systolic BCH decoder
US5432800A (en) * 1991-10-29 1995-07-11 Hitachi, Ltd. Methods and apparatuses for transmission and reception of information signals
US5467360A (en) * 1990-01-18 1995-11-14 U.S. Philips Corporation Storage device for reversibly storing digital data on a multitrack storage medium, a decoding device, an information reproducing apparatus for use with a storage medium, and a unitary storage medium for use with such a storage device decoding device and/o
US5517509A (en) * 1993-03-31 1996-05-14 Kabushiki Kaisha Toshiba Decoder for decoding ECC using Euclid's algorithm
US5517484A (en) * 1993-02-09 1996-05-14 Matsushita Electric Industrial Co., Ltd. Optical disk and optical disk recording and reproducing apparatus
US5537429A (en) * 1992-02-17 1996-07-16 Mitsubishi Denki Kabushiki Kaisha Error-correcting method and decoder using the same
US5541937A (en) * 1993-12-27 1996-07-30 Canon Kabushiki Kaisha Apparatus for uniformly correcting erasure and error of received word by using a common polynomial
US5680156A (en) * 1994-11-02 1997-10-21 Texas Instruments Incorporated Memory architecture for reformatting and storing display data in standard TV and HDTV systems
US5712861A (en) * 1994-07-12 1998-01-27 Mitsubishi Denki Kabushiki Kaisha Error correcting method and decoder with improved reliability
US5835509A (en) * 1994-10-24 1998-11-10 Sony Corporation Method of and apparatus for recording and reproducing data and transmitting data
US6038692A (en) * 1993-06-28 2000-03-14 Samsung Electronics Co., Ltd. Error correcting memory system
US6085348A (en) * 1990-10-17 2000-07-04 Canon Kabushiki Kaisha Error correction code encoder and decoder
US6415411B1 (en) * 1998-12-28 2002-07-02 Nec Corporation Error correcting decoder
US20030007487A1 (en) * 2001-04-16 2003-01-09 Sindhushayana Nagabhushana T. Method and an apparatus for use of codes in multicast transmission
US20030061558A1 (en) * 2001-09-25 2003-03-27 Fackenthal Richard E. Double error correcting code system
US6584595B2 (en) * 1998-09-24 2003-06-24 Sun Microsystems, Inc. Technique for correcting single-bit errors in caches with sub-block parity bits
US6631492B2 (en) * 2001-01-02 2003-10-07 Eastman Kodak Company Multitrack data recording and read out of recorded multitrack digital data for error correction
DE19733738B4 (de) * 1996-08-06 2004-09-30 Samsung Electronics Co., Ltd., Suwon Fehlerkorrekturvorrichtung und -Verfahren eines digitalen Verarbeitungssystems
US20040250199A1 (en) * 1999-07-08 2004-12-09 Samsung Electronics Co., Ltd. Error correction method for high density disc
US20040249840A1 (en) * 2003-06-03 2004-12-09 Sunplus Technology Co., Ltd. Device and method for block code error correction
US20050229076A1 (en) * 2004-03-30 2005-10-13 Elpida Memory, Inc. Semiconductor device and testing method for same
US7100101B1 (en) * 2002-11-08 2006-08-29 Xilinx, Inc. Method and apparatus for concatenated and interleaved turbo product code encoding and decoding
US7134069B1 (en) * 1999-06-16 2006-11-07 Madrone Solutions, Inc. Method and apparatus for error detection and correction
US7159164B1 (en) * 2000-06-05 2007-01-02 Qualcomm Incorporated Method and apparatus for recovery of particular bits of a frame
US7328395B1 (en) * 2004-04-13 2008-02-05 Marvell International Ltd. Iterative Reed-Solomon error-correction decoding
US8869006B2 (en) 2012-02-02 2014-10-21 International Business Machines Corporation Partial-maximum distance separable (PMDS) erasure correcting codes for storage arrays
US8918701B2 (en) 2011-02-28 2014-12-23 SK Hynix Inc. Nested multiple erasure correcting codes for storage arrays
US20150006990A1 (en) * 2011-12-13 2015-01-01 Broadcom Corporation Encoding Methods and Systems For Binary Product Codes
US9058291B2 (en) 2011-02-28 2015-06-16 International Business Machines Corporation Multiple erasure correcting codes for storage arrays
US9252815B2 (en) 2013-12-16 2016-02-02 International Business Machines Corporation Extension of product codes with applications to tape and parallel channels
US20180219561A1 (en) * 2017-02-01 2018-08-02 Tsofun Algorithm Ltd. Device, system and method of implementing product error correction codes for fast encoding and decoding
US10417090B2 (en) 2013-12-23 2019-09-17 Cnex Labs, Inc. Computing system with data protection mechanism and method of operation thereof

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0235782B1 (de) * 1986-03-04 1992-01-22 Sony Corporation Digitalwiedergabegerät
JPS63193723A (ja) * 1987-02-06 1988-08-11 Sony Corp リ−ドソロモン符号の復号方法
AU622626B2 (en) * 1987-06-03 1992-04-16 Sony Corporation Method of processing data
EP0329789B1 (de) * 1987-06-30 1995-02-08 Matsushita Electric Industrial Co., Ltd. Galois-feld-recheneinheit
JP2881773B2 (ja) * 1988-07-30 1999-04-12 ソニー株式会社 誤り訂正装置
CA2013484A1 (en) * 1989-06-26 1990-12-26 Can A. Eryaman Erasure arrangement for an error correction decoder
KR0133505B1 (ko) * 1992-07-16 1998-04-22 구자홍 디지탈 브이씨알의 오류정정 부호화 방법
KR950010768B1 (ko) * 1993-10-20 1995-09-22 주식회사 Lg전자 에러 정정 코드 복호 장치 및 그 방법
US5483236A (en) * 1993-12-20 1996-01-09 At&T Corp. Method and apparatus for a reduced iteration decoder
JP3154607B2 (ja) * 1993-12-28 2001-04-09 三菱電機株式会社 誤り訂正復号装置及び誤り訂正復号方法
US5677919A (en) * 1994-06-10 1997-10-14 Hughes Electronics Faster linear block decoding apparatus and method for receivers in digital cellular communication and other systems
JP3562544B2 (ja) * 1996-08-13 2004-09-08 ソニー株式会社 復号化装置および復号化方法
TW311189B (en) * 1996-09-30 1997-07-21 United Microelectronics Corp The error-corrected decoding method and its apparatus for Reed-Soloman code
NL1006174C2 (nl) * 1997-04-17 1998-12-01 United Microelectronics Corp Foutdecoderingswerkwijze alsmede apparaat voor het decoderen.
US6625774B1 (en) * 1999-10-29 2003-09-23 Stmicroelectronics, Inc. Redundancy system and method for locating errors in interleaved code words
US6738942B1 (en) 2000-06-02 2004-05-18 Vitesse Semiconductor Corporation Product code based forward error correction system
DE10216999A1 (de) * 2002-04-16 2003-11-06 Thomson Brandt Gmbh ECC-Block-Enkodierer und -Dekodierer mit reduziertem RAM-Speicherbedarf
GB2415873A (en) * 2004-06-30 2006-01-04 Nokia Corp Erasure information generation in Forward Error Correction decoding

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3714629A (en) * 1971-06-01 1973-01-30 Ibm Double error correcting method and system
US4030067A (en) * 1975-12-29 1977-06-14 Honeywell Information Systems, Inc. Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes
US4142174A (en) * 1977-08-15 1979-02-27 International Business Machines Corporation High speed decoding of Reed-Solomon codes
US4236247A (en) * 1979-01-15 1980-11-25 Organisation Europeene De Recherches Spatiales Apparatus for correcting multiple errors in data words read from a memory
US4546474A (en) * 1980-06-20 1985-10-08 Sony Corporation Method of error correction
US4646301A (en) * 1983-10-31 1987-02-24 Hitachi, Ltd. Decoding method and system for doubly-encoded Reed-Solomon codes

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4044328A (en) * 1976-06-22 1977-08-23 Bell & Howell Company Data coding and error correcting methods and apparatus
US4107650A (en) * 1976-08-13 1978-08-15 The Johns Hopkins University Error correction encoder and decoder
US4205324A (en) * 1977-12-23 1980-05-27 International Business Machines Corporation Methods and means for simultaneously correcting several channels in error in a parallel multi channel data system using continuously modifiable syndromes and selective generation of internal channel pointers
GB2093238B (en) * 1981-02-18 1985-04-17 Kokusai Denshin Denwa Co Ltd Error correcting system for simultaneous errors in a code
GB2107496B (en) * 1981-09-30 1985-11-20 Hitachi Ltd Error flag processor
JPS58171144A (ja) * 1982-04-01 1983-10-07 Mitsubishi Electric Corp 復号化装置
JPS58219648A (ja) * 1982-06-15 1983-12-21 Toshiba Corp ガロア体における除算装置
JPS5943646A (ja) * 1982-09-03 1984-03-10 Mitsubishi Electric Corp 復号化システム

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3714629A (en) * 1971-06-01 1973-01-30 Ibm Double error correcting method and system
US4030067A (en) * 1975-12-29 1977-06-14 Honeywell Information Systems, Inc. Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes
US4142174A (en) * 1977-08-15 1979-02-27 International Business Machines Corporation High speed decoding of Reed-Solomon codes
US4236247A (en) * 1979-01-15 1980-11-25 Organisation Europeene De Recherches Spatiales Apparatus for correcting multiple errors in data words read from a memory
US4546474A (en) * 1980-06-20 1985-10-08 Sony Corporation Method of error correction
US4646301A (en) * 1983-10-31 1987-02-24 Hitachi, Ltd. Decoding method and system for doubly-encoded Reed-Solomon codes

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
U. Olderdissen, "Fast Double Error Correction", IBM TDM, vol. 25, No. 5, 10/1982, pp. 2343-2346.
U. Olderdissen, Fast Double Error Correction , IBM TDM, vol. 25, No. 5, 10/1982, pp. 2343 2346. *

Cited By (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794602A (en) * 1983-06-17 1988-12-27 Sony Corporation Method for error detection
US4819236A (en) * 1986-01-24 1989-04-04 Sony Corporation Data transmission method suitable for a disc
US4845714A (en) * 1987-06-08 1989-07-04 Exabyte Corporation Multiple pass error correction process and apparatus for product codes
WO1988009966A1 (en) * 1987-06-08 1988-12-15 Exabyte Corporation Multiple pass error correction process and apparatus for product codes
US4849976A (en) * 1987-08-03 1989-07-18 Scs Telecom, Inc. PASM and TASM forward error correction and detection code method and apparatus
US4972416A (en) * 1987-11-13 1990-11-20 Matsushita Electric Industrial Co., Ltd. Error detection and correction method
US4847842A (en) * 1987-11-19 1989-07-11 Scs Telecom, Inc. SM codec method and apparatus
US4956709A (en) * 1988-03-11 1990-09-11 Pbs Enterprises, Inc. Forward error correction of data transmitted via television signals
US5107505A (en) * 1988-07-07 1992-04-21 Schlumberger Industries Circuit of encoding and formatting data for rotating head recorders
US5068855A (en) * 1988-07-18 1991-11-26 Canon Kabushiki Kaisha Error correcting method and apparatus
US5631914A (en) * 1988-07-18 1997-05-20 Canon Kabushiki Kaisha Error correcting apparatus
US5231638A (en) * 1989-04-11 1993-07-27 Fujitsu Limited Error correction control apparatus
US5136592A (en) * 1989-06-28 1992-08-04 Digital Equipment Corporation Error detection and correction system for long burst errors
US5040179A (en) * 1989-08-18 1991-08-13 Loral Aerospace Corp. High data rate BCH encoder
US5467360A (en) * 1990-01-18 1995-11-14 U.S. Philips Corporation Storage device for reversibly storing digital data on a multitrack storage medium, a decoding device, an information reproducing apparatus for use with a storage medium, and a unitary storage medium for use with such a storage device decoding device and/o
US6085348A (en) * 1990-10-17 2000-07-04 Canon Kabushiki Kaisha Error correction code encoder and decoder
US5323402A (en) * 1991-02-14 1994-06-21 The Mitre Corporation Programmable systolic BCH decoder
US5315583A (en) * 1991-04-11 1994-05-24 Usa Digital Radio Method and apparatus for digital audio broadcasting and reception
US5432800A (en) * 1991-10-29 1995-07-11 Hitachi, Ltd. Methods and apparatuses for transmission and reception of information signals
US5537429A (en) * 1992-02-17 1996-07-16 Mitsubishi Denki Kabushiki Kaisha Error-correcting method and decoder using the same
US5517484A (en) * 1993-02-09 1996-05-14 Matsushita Electric Industrial Co., Ltd. Optical disk and optical disk recording and reproducing apparatus
US5517509A (en) * 1993-03-31 1996-05-14 Kabushiki Kaisha Toshiba Decoder for decoding ECC using Euclid's algorithm
US6038692A (en) * 1993-06-28 2000-03-14 Samsung Electronics Co., Ltd. Error correcting memory system
US5541937A (en) * 1993-12-27 1996-07-30 Canon Kabushiki Kaisha Apparatus for uniformly correcting erasure and error of received word by using a common polynomial
US5712861A (en) * 1994-07-12 1998-01-27 Mitsubishi Denki Kabushiki Kaisha Error correcting method and decoder with improved reliability
US5835509A (en) * 1994-10-24 1998-11-10 Sony Corporation Method of and apparatus for recording and reproducing data and transmitting data
US5680156A (en) * 1994-11-02 1997-10-21 Texas Instruments Incorporated Memory architecture for reformatting and storing display data in standard TV and HDTV systems
DE19733738B4 (de) * 1996-08-06 2004-09-30 Samsung Electronics Co., Ltd., Suwon Fehlerkorrekturvorrichtung und -Verfahren eines digitalen Verarbeitungssystems
US6584595B2 (en) * 1998-09-24 2003-06-24 Sun Microsystems, Inc. Technique for correcting single-bit errors in caches with sub-block parity bits
US6415411B1 (en) * 1998-12-28 2002-07-02 Nec Corporation Error correcting decoder
US20100083065A1 (en) * 1999-06-16 2010-04-01 Madrone Solutions, Inc. Method and apparatus for error detection and correction
US7644348B2 (en) * 1999-06-16 2010-01-05 Madrone Solutions, Inc. Method and apparatus for error detection and correction
US20070214403A1 (en) * 1999-06-16 2007-09-13 Madrone Solutions, Inc. Method and apparatus for error detection and correction
US7134069B1 (en) * 1999-06-16 2006-11-07 Madrone Solutions, Inc. Method and apparatus for error detection and correction
US20040250199A1 (en) * 1999-07-08 2004-12-09 Samsung Electronics Co., Ltd. Error correction method for high density disc
US7370267B2 (en) 1999-07-08 2008-05-06 Samsung Electronics Co., Ltd. Error correction method for high density disc
US6931586B1 (en) * 1999-07-08 2005-08-16 Samsung Electronics Co., Ltd. Error correction method for high density disc
US7739582B2 (en) 1999-07-08 2010-06-15 Samsung Electronics, Co., Ltd. Error correction method for high density disc
US7401285B2 (en) 1999-07-08 2008-07-15 Samsung Electronics Co., Ltd. Error correction method for high density disc
US20040250198A1 (en) * 1999-07-08 2004-12-09 Samsung Electronics Co., Ltd. Error correction method for high density disc
US7383491B2 (en) 1999-07-08 2008-06-03 Samsung Electronics Co., Ltd. Error correction method for high density disc
US7159164B1 (en) * 2000-06-05 2007-01-02 Qualcomm Incorporated Method and apparatus for recovery of particular bits of a frame
US7752522B2 (en) 2000-06-05 2010-07-06 Qualcomm Incorporated Method and apparatus for recovery of particular bits of a frame
US6631492B2 (en) * 2001-01-02 2003-10-07 Eastman Kodak Company Multitrack data recording and read out of recorded multitrack digital data for error correction
US8656246B2 (en) * 2001-04-16 2014-02-18 Qualcomm Incorporated Method and an apparatus for use of codes in multicast transmission
US20030007487A1 (en) * 2001-04-16 2003-01-09 Sindhushayana Nagabhushana T. Method and an apparatus for use of codes in multicast transmission
US20030061558A1 (en) * 2001-09-25 2003-03-27 Fackenthal Richard E. Double error correcting code system
US7100101B1 (en) * 2002-11-08 2006-08-29 Xilinx, Inc. Method and apparatus for concatenated and interleaved turbo product code encoding and decoding
US7181669B2 (en) * 2003-06-03 2007-02-20 Sunplus Technology Co., Ltd. Device and method for block code error correction
US20040249840A1 (en) * 2003-06-03 2004-12-09 Sunplus Technology Co., Ltd. Device and method for block code error correction
US7346829B2 (en) * 2004-03-30 2008-03-18 Elpida Memory, Inc. Semiconductor device and testing method for same
US20080133985A1 (en) * 2004-03-30 2008-06-05 Elpida Memory, Inc. Semiconductor device and testing method for same
US7529986B2 (en) 2004-03-30 2009-05-05 Elpida Memory, Inc. Semiconductor device and testing method for same
US20050229076A1 (en) * 2004-03-30 2005-10-13 Elpida Memory, Inc. Semiconductor device and testing method for same
US7689893B1 (en) 2004-04-13 2010-03-30 Marvell International Ltd. Iterative reed-solomon error-correction decoding
US7328395B1 (en) * 2004-04-13 2008-02-05 Marvell International Ltd. Iterative Reed-Solomon error-correction decoding
US8918701B2 (en) 2011-02-28 2014-12-23 SK Hynix Inc. Nested multiple erasure correcting codes for storage arrays
US9058291B2 (en) 2011-02-28 2015-06-16 International Business Machines Corporation Multiple erasure correcting codes for storage arrays
US20150006990A1 (en) * 2011-12-13 2015-01-01 Broadcom Corporation Encoding Methods and Systems For Binary Product Codes
US9231622B2 (en) * 2011-12-13 2016-01-05 Broadcom Corporation Encoding methods and systems for binary product codes
US8869006B2 (en) 2012-02-02 2014-10-21 International Business Machines Corporation Partial-maximum distance separable (PMDS) erasure correcting codes for storage arrays
US8874995B2 (en) * 2012-02-02 2014-10-28 International Business Machines Corporation Partial-maximum distance separable (PMDS) erasure correcting codes for storage arrays
US9252815B2 (en) 2013-12-16 2016-02-02 International Business Machines Corporation Extension of product codes with applications to tape and parallel channels
US10417090B2 (en) 2013-12-23 2019-09-17 Cnex Labs, Inc. Computing system with data protection mechanism and method of operation thereof
US20180219561A1 (en) * 2017-02-01 2018-08-02 Tsofun Algorithm Ltd. Device, system and method of implementing product error correction codes for fast encoding and decoding
WO2018142391A1 (en) * 2017-02-01 2018-08-09 Tsofun Algorithm Ltd. Device, system and method of implementing product error correction codes for fast encoding and decoding
US10547332B2 (en) * 2017-02-01 2020-01-28 Tsofun Algorithm Ltd. Device, system and method of implementing product error correction codes for fast encoding and decoding

Also Published As

Publication number Publication date
EP0167627A1 (de) 1986-01-15
DE3486471T2 (de) 1999-09-02
DE3486408T2 (de) 1996-03-14
EP0387924A3 (de) 1991-03-20
EP0387924A2 (de) 1990-09-19
EP0387924B1 (de) 1995-09-27
ATE128585T1 (de) 1995-10-15
ATE177570T1 (de) 1999-03-15
AU3781285A (en) 1985-07-12
KR850700196A (ko) 1985-10-25
WO1985002958A1 (en) 1985-07-04
AU581202B2 (en) 1989-02-16
HK118795A (en) 1995-07-28
DE3486200D1 (de) 1993-09-16
DE3486200T2 (de) 1993-12-02
EP0426657A3 (de) 1995-03-15
EP0426657A2 (de) 1991-05-08
KR930003997B1 (ko) 1993-05-19
BR8407228A (pt) 1985-11-26
EP0167627A4 (de) 1988-04-27
EP0167627B1 (de) 1993-08-11
DE3486471D1 (de) 1999-04-15
DE3486408D1 (de) 1995-11-02
EP0426657B1 (de) 1999-03-10

Similar Documents

Publication Publication Date Title
US4719628A (en) Method and apparatus for decoding error correction code
US4099160A (en) Error location apparatus and methods
US4142174A (en) High speed decoding of Reed-Solomon codes
US5027357A (en) ECC/CRC error detection and correction system
US4852099A (en) Error correction method using Reed-Solomon code
US5157669A (en) Comparison of an estimated CRC syndrome to a generated CRC syndrome in an ECC/CRC system to detect uncorrectable errors
US4567594A (en) Reed-Solomon error detecting and correcting system employing pipelined processors
US5680340A (en) Low order first bit serial finite field multiplier
US4597083A (en) Error detection and correction in digital communication systems
US5631914A (en) Error correcting apparatus
US5712861A (en) Error correcting method and decoder with improved reliability
US5020060A (en) Error code correction device having a galois arithmetic unit
US5715262A (en) Errors and erasures correcting reed-solomon decoder
US5068857A (en) Error correction circuit
US5226043A (en) Apparatus and method for data error detection and correction and address error detection in a memory system
US4646301A (en) Decoding method and system for doubly-encoded Reed-Solomon codes
US4677622A (en) Error correction method and system
US6024485A (en) Error correction coding and decoding method, and circuit using said method
US4951284A (en) Method and means for correcting random and burst errors
US4473902A (en) Error correcting code processing system
JPH084233B2 (ja) 誤り訂正符号の復号装置
US4841300A (en) Error correction encoder/decoder
US4593394A (en) Method capable of simultaneously decoding two reproduced sequences
JPS632370B2 (de)
JPS61281722A (ja) デジタル情報ワ−ドのブロツク伝送方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: SONY CORPORATION 7-35 KITASHINAGAWA-6, SHINAGAWA-K

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:OZAKI, SHINYA;ODAKA, KENTARO;FUKUMI, TADASHI;REEL/FRAME:004459/0870

Effective date: 19850722

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12