US4645546A - Semiconductor substrate - Google Patents

Semiconductor substrate Download PDF

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Publication number
US4645546A
US4645546A US06/754,298 US75429885A US4645546A US 4645546 A US4645546 A US 4645546A US 75429885 A US75429885 A US 75429885A US 4645546 A US4645546 A US 4645546A
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silicon
semiconductor substrate
layer
oxygen concentration
silicon layer
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US06/754,298
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Yoshiaki Matsushita
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Toshiba Corp
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA, A CORP OF JAPAN reassignment KABUSHIKI KAISHA TOSHIBA, A CORP OF JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: MATSUSHITA, YOSHIAKI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/06—Gettering

Definitions

  • This invention relates to a semiconductor substrate adapted for the manufacture of a semiconductor integrated circuit such as the LSI and VLSI types, and, more particularly, to a silicon semiconductor substrate.
  • the LSI type silicon substrate has been provided by a wafer cut out of a single crystal silicon ingot grown by the Czochralski (abbreviated as "CZ") method.
  • CZ Czochralski
  • the ordinary CZ method has the following drawback. Since a quartz crucible is applied, the quartz is melted into a molten mass of silicon. As a result, oxygen is carried into a single crystal silicon ingot to the extent of 1.0 ⁇ 10 18 cm -3 . Later, the semiconductor substrate cut out of said single crystal silicon ingot is subjected to heat treatment at a temperature of about 900° to 1000° C., applied in the LSI manufacturing process.
  • an intrinsic gettering (IG) wafer (hereinafter referred to as the "IG wafer") has been proposed.
  • This wafer is prepared by letting the oxygen content of the activated element region escape to the outside by applying high temperature heat treatment and by depositing crystallized substances (fine defects) capable of gettering harmful metals, in the interior of said wafer.
  • the IG wafer can, indeed, withstand the occurrence of dislocation or stacking fault near its surface.
  • the IG wafer cannot completely eliminate the defects of a thin oxidized membrane (gate oxidized membrane).
  • the Czochralski method involving the concurrent application of a magnetic field, (abbreviated as "MCZ method") has been developed.
  • This MCZ method can restrict the convection of a molten mass of silicon by the application of a magnetic field, thereby stabilizing the solid-liquid interface and controlling the oxygen concentration in the single crystal silicon ingot. Therefore, it is possible to ensure the growth of a single crystal silicon ingot containing less than 7 ⁇ 10 17 cm -3 .
  • the above-mentioned MCZ method prevents SiO 2 from being crystallized out, thereby preventing the occurrence of dislocation and stacking fault.
  • said MCZ wafer fails to obtain the intrinsic gettering effect which is generally ensured by the semiconductor substrate cut out of the single crystal silicon ingot grown by the ordinary CZ method.
  • the MCZ method has a very weak resistance to contamination occurring during the manufacture of LSI; presenting difficulties in the formation of a highly stable element.
  • heat treatment of 1000° C. is applied to a wafer cut out of a silicon ingot grown by the above-mentioned MCZ method, extremely fine defects (represented by black circles is FIG. 1) are produced in a region of low oxygen concentration (less than 6 ⁇ 10 17 cm -3 ), though oxidized crystallized masses and stacking faults, illustrated by blank squares in FIG. 1, do not appear.
  • the causes of the appearance of the above-mentioned extremely fine dot-like defects are not yet clearly defined. At any rate, this phenomenon is peculiar to the low-oxygen silicon crystal provided by the MCZ method.
  • This invention has been accomplished in view of the above-mentioned circumstances, and is intended to provide a semiconductor substrate which is saved from the occurrence of dislocation, stacking fault or warping resulting from heat treatment applied during the manufacture, a substrate capable of withstanding the unwanted production of extremely fine defects peculiar to a low-oxygen silicon crystal, and which further indicates a great resistance to various contaminations taking place during its manufacture.
  • this invention provides a silicon semiconductor substrate which has an oxygen concentration ranging between 3 ⁇ 10 17 cm -3 and 7 ⁇ 10 17 cm -3 , and is provided with a gettering layer on the backside.
  • oxygen concentration is defined to mean the value measured by the infrared ray method specified in ASTM (1984) according to the following formula:
  • a gettering layer deposited on the backside of a semiconductor substrate embodying this invention may be prepared from a nonsingle crystal silicon layer, namely, a polycrystalline silicon layer, amorphous silicon layer or a layer of high density and stacking fault.
  • FIG. 1 is a coordinate system showing the relationship between the oxygen concentration in a silicon wafer and the occurrence of extremely fine dot type defects appearing on the surface of a heated treated wafer as well as between said oxygen concentration and the stacking defect;
  • FIG. 2 is a coordinate system indicating the relationship between the frequency of heat treating the silicon substrate and the extent to which a wafer is warped;
  • FIG. 3 is a coordinate system illustrating the relationship between the oxygen concentration in the silicon substrate and the occurrence of extremely fine dot type defects appearing in a repeatedly heat-treated substrate;
  • FIG. 4 diagrammatically indicates the distribution of the withstand voltage of an oxide layer deposited on the surface of a silicon substrate having an oxygen concentration of 5.6 ⁇ 10 17 cm -3 ;
  • FIG. 5 diagrammatically shows the distribution of the withstand voltage of the oxidized surface of a silicon substrate provided with a polycrystalline silicon layer on the backside;
  • FIG. 6 diagrammatically sets forth the relationship between the extent of the stacking fault appearing on the backside of a silicon substrate and the extent of extremely fine dot type detects produced in a repeatedly heat-treated silicon substrate.
  • This invention provides a silicon semiconductor substrate manufactured by the MCZ method and capable of providing a stable solid-liquid interface containing oxygen ranging from 3 ⁇ 10 17 cm -3 to 7 ⁇ 10 17 cm -3 ; provided, on its rear surface, with a nonsingle crystal silicon layer or a stacking default used as a gettering source for adsorbing a harmful metal, and characterized by an ability to withstand the occurrence of dislocation and stacking default resulting from heat treatment; equally capable of preventing the generation of extremely fine dot-shaped defects peculiar to a low oxygen crystal as well as the warping arising from said heat treatment applied during the manufacture of said semiconductor substrate, and possessing the capacity to resist contamination occurring during said manufacture.
  • the nonsingle crystal silicon layer acts to generate stacking fault capable of performing a gettering action on the backside of the substrate during its heat treatment.
  • the nonsingle crystal silicon layer is defined to mean a polycrystalline silicon layer and amorphous silicon layer. However, the amorphous silicon layer is ultimately converted into a polycrystalline silicon layer in the subsequent heat treatment of the semiconductor substrate.
  • the stacking fault (the so-called soft damage) provided on the backside of the semiconductor substrate performs the gettering action in the heat treatment of the semiconductor substrate. It is preferred that the density of the stacking fault appearing on the backside of the semiconductor substrate be higher than 3 ⁇ 10 4 cm -2 . If the density of said stacking fault falls below said level, the gettering action cannot be fully obtained. It is further preferred that the density of said stacking fault be higher than 1 ⁇ 10 5 cm -2 .
  • the deposition of an amorphous silicon layer on the backside of the silicon semiconductor substrate may be carried out by any known process. It is generally sufficient if said amorphous silicon layer is deposited by the CVD process with a thickness of, for example, more than 1000 ⁇ . As far as the intended object of the present invention is concerned, no limitation is imposed on the upper limit of said specified thickness.
  • the aforementioned stacking default may be provided on the backside of the silicon semiconductor substrate by any optical process selected from among lapping, grinding, needle scribing or bombardment with particles of, for example, SiO 2 or Al 2 O 3 .
  • Curves a-e given in FIG. 2 represent the warpages of said substrate samples A-E.
  • FIG. 2 shows that a substrate A, having a smaller oxygen concentration than 3 ⁇ 10 17 cm -3 (curve a), and a substrate E, having a larger oxygen concentration than 7 ⁇ 10 17 cm -3 (curve e), indicate a more noticeable warpage as the heat treatment was repeated with increasing frequency, and, in contrast, that the substrates B-D, having an oxygen concentration ranging between 3 ⁇ 10 17 cm -3 and 7 ⁇ 10 17 cm -3 (curves b-d), were reduced in warpage.
  • FIG. 4 shows the withstand voltage property of the silicon substrate G.
  • FIG. 5 represents the withstand voltage property of the silicon substrate C. As seen from FIGS. 4 and 5, the deposition of a polycrystalline silicon layer on the backside of a semiconductor substrate noticeably improved the distribution of the withstand voltage property of an oxide layer.
  • a silicon wafer having an oxygen concentration of 5.6 ⁇ 10 17 cm -3 and crystal plane orientation (100) was cut out of a single crystal ingot grown by the MCZ process. Later, machining warpage was purposely produced by lapping on the backside of said wafer. Heat treatment was then applied. As a result, a silicon substrate was formed whose oxygen density ranged between 1 ⁇ 10 2 cm -2 -1 ⁇ 10 6 cm -2 and which was provided with a stacking fault.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
US06/754,298 1984-07-13 1985-07-12 Semiconductor substrate Expired - Lifetime US4645546A (en)

Applications Claiming Priority (2)

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JP59-145348 1984-07-13
JP59145348A JPS6124240A (ja) 1984-07-13 1984-07-13 半導体基板

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Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130260A (en) * 1990-07-13 1992-07-14 Mitsubishi Materials Corporation Method of gettering unintentional mobile impurities in silicon wafer by using a damaged layer exposed to the reverse surface thereof
US5332441A (en) * 1991-10-31 1994-07-26 International Business Machines Corporation Apparatus for gettering of particles during plasma processing
US5360748A (en) * 1992-01-24 1994-11-01 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US5389551A (en) * 1991-02-21 1995-02-14 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor substrate
EP0798771A3 (en) * 1996-03-28 1997-10-08 Shin-Etsu Handotai Company Limited Silicon wafer comprising an amorphous silicon layer and method of manufacturing the same by plasma enhanced chemical vapor deposition (PECVD)
US5894037A (en) * 1995-11-22 1999-04-13 Nec Corporation Silicon semiconductor substrate and method of fabricating the same
US6059887A (en) * 1997-04-03 2000-05-09 Purex Co., Ltd. Process for cleaning the interior of semiconductor substrate
DE10052411A1 (de) * 2000-10-23 2002-05-16 Mitsubishi Material Silicon Siliciumwafer und Wärmebehandlungsverfahren desselben und der wärmebehandelte Siliciumwafer
US6458672B1 (en) 1997-05-12 2002-10-01 Silicon Genesis Corporation Controlled cleavage process and resulting device using beta annealing
US6486041B2 (en) 1997-05-12 2002-11-26 Silicon Genesis Corporation Method and device for controlled cleaving process
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
US6513564B2 (en) 1999-08-10 2003-02-04 Silicon Genesis Corporation Nozzle for cleaving substrates
US6544862B1 (en) 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
US6548382B1 (en) 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US20030124815A1 (en) * 1999-08-10 2003-07-03 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
US20080003782A1 (en) * 2006-07-03 2008-01-03 Semiconductor Components Industries, Llc Multilayer gettering structure for semiconductor device and method
US20080038901A1 (en) * 1997-05-12 2008-02-14 Silicon Genesis Corporation Controlled Process and Resulting Device
US20080153220A1 (en) * 2003-11-18 2008-06-26 Silicon Genesis Corporation Method for fabricating semiconductor devices using strained silicon bearing material
US20080179547A1 (en) * 2006-09-08 2008-07-31 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
US20080290347A1 (en) * 2004-12-14 2008-11-27 Yong Jin Kim Gallium Nitride Semiconductor and Method of Manufacturing the Same
US20100044595A1 (en) * 2008-08-25 2010-02-25 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
US20100317140A1 (en) * 2009-05-13 2010-12-16 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
US8193039B2 (en) 2010-09-24 2012-06-05 Advanced Micro Devices, Inc. Semiconductor chip with reinforcing through-silicon-vias
CN102487072A (zh) * 2010-12-02 2012-06-06 合晶科技股份有限公司 硅晶片背面的封装结构
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
US9437561B2 (en) 2010-09-09 2016-09-06 Advanced Micro Devices, Inc. Semiconductor chip with redundant thru-silicon-vias
US10825692B2 (en) 2018-12-20 2020-11-03 Advanced Micro Devices, Inc. Semiconductor chip gettering

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JPH0633235B2 (ja) * 1989-04-05 1994-05-02 新日本製鐵株式会社 酸化膜耐圧特性の優れたシリコン単結晶及びその製造方法
JP5188673B2 (ja) * 2005-06-09 2013-04-24 株式会社Ｓｕｍｃｏ Ｉｇｂｔ用のシリコンウェーハ及びその製造方法
JP4760729B2 (ja) 2006-02-21 2011-08-31 株式会社Ｓｕｍｃｏ Ｉｇｂｔ用のシリコン単結晶ウェーハ及びｉｇｂｔ用のシリコン単結晶ウェーハの製造方法

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Cited By (63)

* Cited by examiner, † Cited by third party
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US5130260A (en) * 1990-07-13 1992-07-14 Mitsubishi Materials Corporation Method of gettering unintentional mobile impurities in silicon wafer by using a damaged layer exposed to the reverse surface thereof
US5389551A (en) * 1991-02-21 1995-02-14 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor substrate
US5332441A (en) * 1991-10-31 1994-07-26 International Business Machines Corporation Apparatus for gettering of particles during plasma processing
US5433258A (en) * 1991-10-31 1995-07-18 International Business Machines Corporation Gettering of particles during plasma processing
US5360748A (en) * 1992-01-24 1994-11-01 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
US5894037A (en) * 1995-11-22 1999-04-13 Nec Corporation Silicon semiconductor substrate and method of fabricating the same
EP0798771A3 (en) * 1996-03-28 1997-10-08 Shin-Etsu Handotai Company Limited Silicon wafer comprising an amorphous silicon layer and method of manufacturing the same by plasma enhanced chemical vapor deposition (PECVD)
US5970365A (en) * 1996-03-28 1999-10-19 Shin-Etsu Handotai., Ltd. Silicon wafer including amorphous silicon layer formed by PCVD and method of manufacturing wafer
US6059887A (en) * 1997-04-03 2000-05-09 Purex Co., Ltd. Process for cleaning the interior of semiconductor substrate
US7759217B2 (en) 1997-05-12 2010-07-20 Silicon Genesis Corporation Controlled process and resulting device
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US6486041B2 (en) 1997-05-12 2002-11-26 Silicon Genesis Corporation Method and device for controlled cleaving process
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US6511899B1 (en) 1997-05-12 2003-01-28 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
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US20080038901A1 (en) * 1997-05-12 2008-02-14 Silicon Genesis Corporation Controlled Process and Resulting Device
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US20030113983A1 (en) * 1997-05-12 2003-06-19 Silicon Genesis Corporation Method and device for controlled cleaving process
US6458672B1 (en) 1997-05-12 2002-10-01 Silicon Genesis Corporation Controlled cleavage process and resulting device using beta annealing
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US20050070071A1 (en) * 1997-05-12 2005-03-31 Silicon Genesis Corporation Method and device for controlled cleaving process
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US6890838B2 (en) 1997-07-18 2005-05-10 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
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US6513564B2 (en) 1999-08-10 2003-02-04 Silicon Genesis Corporation Nozzle for cleaving substrates
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US6544862B1 (en) 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
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US20080153220A1 (en) * 2003-11-18 2008-06-26 Silicon Genesis Corporation Method for fabricating semiconductor devices using strained silicon bearing material
US20080290347A1 (en) * 2004-12-14 2008-11-27 Yong Jin Kim Gallium Nitride Semiconductor and Method of Manufacturing the Same
US20080003782A1 (en) * 2006-07-03 2008-01-03 Semiconductor Components Industries, Llc Multilayer gettering structure for semiconductor device and method
US7737004B2 (en) 2006-07-03 2010-06-15 Semiconductor Components Industries Llc Multilayer gettering structure for semiconductor device and method
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US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
US20100317140A1 (en) * 2009-05-13 2010-12-16 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
US9437561B2 (en) 2010-09-09 2016-09-06 Advanced Micro Devices, Inc. Semiconductor chip with redundant thru-silicon-vias
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