US4498175A - Error correcting system - Google Patents

Error correcting system Download PDF

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US4498175A
US4498175A US06/430,002 US43000282A US4498175A US 4498175 A US4498175 A US 4498175A US 43000282 A US43000282 A US 43000282A US 4498175 A US4498175 A US 4498175A
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sup
error
multiplying
circuit
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Masahide Nagumo
Jun Inagawa
Tadashi Kojima
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Toshiba Corp
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Tokyo Shibaura Electric Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G06F7/726—Inversion; Reciprocal calculation; Division of elements of a finite field
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1806—Pulse code modulation systems for audio signals
    • G11B20/1809—Pulse code modulation systems for audio signals by interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

Definitions

  • the present invention relates to an improved system for correcting errors which can effectively conbined with, for example, a digital audio disk (DAD) device using a compact disk (CD).
  • DAD digital audio disk
  • CD compact disk
  • an optical DAD device having a CD uses cross interleaved Reed-Solomon codes (CIRC) to correct errors.
  • CIRC cross interleaved Reed-Solomon codes
  • a CIRC is obtained by submitting a Reed-Solomon code, which is a kind of BCH code and is generally regarded as the most effective random error correction code hitherto known to a signal process called "cross interleaving.”
  • the CIRC thus obtained is sensitive enough to correct burst errors.
  • a Reed-Solomon code can be decoded in the same way as other BCH codes, thereby correcting errors.
  • a typical Reed-Solomon code consisting of k data symbols and (n-k) inspection symbols, i.e., consisting of n symbols, is decoded in the following manner.
  • n symbols are represented by the 2 m elements of a finite field or a Galois field GF (2 m ) which represents m binary bits.
  • the generator polynomil g.sub.(x) representing the Reed-Solomon code used to correct an error a t number of times is given by the following two equations, where ⁇ is the origin element Galois field GF (2 m ):
  • C.sub.(x), R.sub.(x) and E.sub.(x) denote a transmitted code word, a received code word and an error polynomial, then:
  • the coefficients contained in polynomial E.sub.(x) are also contained in the Galois field GF (2 m ). Hence, the error polynomial E.sub.(x) contains only those terms which correspond to error locations and the value (i.e., size) of the error.
  • Error location polynomial ⁇ .sub.(x) is given by: ##EQU3## where e is the number of the errors.
  • a Reed-Solomon code as defined can be decoded as follows:
  • the Reed-Solomon code may then be decoded by following method A or by following method B.
  • Equation 9 The solution ⁇ 1 of Equation 9 can be expressed by: ##EQU4##
  • Equation 10 The solution ⁇ 1 and ⁇ 2 of Equation 10 is: ##EQU5##
  • the Reed-Solomon code used to correct an error twice can be used to correct an error four times in method B.
  • FIG. 1 is a block diagram of a known data correcting system which is designed to decode Reed-Solomon codes in the manner described above.
  • a data to be corrected by a Reed-Solomon code is supplied through an input terminal IN.
  • the data is stored into a data buffer 11 and is kept there until code decoding (described later) is completed.
  • the data is also supplied to a syndrome calculator 12.
  • the calculator 12 uses the input data, the calculator 12 calculates syndromes.
  • the syndromes are stored into a syndrome buffer 13.
  • An OR gate 14 is coupled to the output of the syndrome buffer 13.
  • the OR gate 14 generates two output signals which indicates whether or not an error exists in the syndromes supplied from the syndrome buffer 13.
  • An output signal from the OR gate is supplied to an error location polynomial calculator 15.
  • the calculator 15 finds the coefficients in the error location polynomial ⁇ .sub.(x). Data representing the coefficients is fed to an error location calculator 16.
  • the error location calculator 16 finds the root or roots of the error location. Data representing the root or roots is supplied from the calculator 16 to an error value calculator 17. From the input, the calculator 17 calculates the value of the error.
  • the data representing the root or roots, and the data representing the error value are used to correct the data from the data buffer 11.
  • the calculators 12, 15, 16 and 17 of the data correcting system can detect elements which have a value of "0", and can perform addition, multiplication or division.
  • the error location polynomial calculator 15 may have the structure shown in FIG. 2 which is disclosed in U.S. Pat. No. 4,142,174.
  • the error location polynomial calculator 16 comprises a syndrome buffer 21, a working buffer 22, a sequence controller 23, a logarithm buffer 24 and an antilogarithm buffer 25.
  • the syndrome buffer 21 is a random-access memory (RAM) for storing a syndrome Si which consists of m-bit data and which represents each element of a Galois field GF (2 m ).
  • the working buffer 22 is a RAM for storing the interim result of an algebraic operation performed to find the coefficients of the error location polynomial, and for storing the final result of the operation.
  • the working buffer 22 may store partial results which are used in the operations following the calculation of the coefficients of the error location polynomial.
  • the sequence controller 23 defines the order in which the algebraic operations will be performed.
  • the logarithm buffer 24 is a ROM (read-only memory) and stores a table of the logarithms of the elements of the Galois field GF (2 m ).
  • the antilogarithm buffer 25 is also a ROM and stores a table of the antilogarithms of the elements of Galois field GF (2 m ).
  • the address of the logarithm buffer 24 is a binary code of element ⁇ i . Its entry is the logarithm of ⁇ to the base ⁇ , that is, i.
  • the entry at address i of the antilogarithm buffer 25 is a binary code of ⁇ i .
  • the elements of the Galois field GF (2 8 ) other than the above can be represented as binary vectors.
  • the addresses (1-255) of the logarithm table are 8-bit binary vectors of elements ⁇ i .
  • Entries corresponding to the addresses are binary notations of the exponent i.
  • exponent i is used as an address, and the entries are binary vectors of ⁇ i .
  • the element In order to detect whether or not element ⁇ i is 0, the element is supplied from the H register 28 to an OR gate 29, which produces a logic sum. The logic sum is transferred via an M register 30 to the working buffer 22. The contents of the M register 30 are 0 only when element ⁇ i is 0.
  • the antilogarithm buffer 25 supplies an output ⁇ t .
  • the output ⁇ t is the product of elements ⁇ i and ⁇ j and is transferred to the working buffer 22 through a G register 37.
  • the error location polynomial calculator of the known error correcting system must be provided with a logarithm buffer and an antilogarithm buffer. Without the logarithm buffer and the antilogarithm buffer, the error location polynomial calculator could not perform multiplication or division. Both buffers, which are ROMs, need to have an enormously large memory capacity. This makes it difficult to manufacture the error location polynomial calculator in the form of an LSI. If the calculator may be made into an LSI, the logarithm buffer and the antilogarithm buffer are excluded from the calculator. In this case, the buffers of a large memory capacity have to be connected to the calculator.
  • the buffer must have a memory capacity of 2040 bits (255 ⁇ 8).
  • the known error location polynomial calculator is provided with two ROMs, the total memory capacity of which amounts to 4080 bits: one ROM storing a table of logarithms and the other ROM storing a table of antilogarithms.
  • the error location polynomial calculator has two ROMs of a large memory capacity, the error correcting system is inevitably complicated and is thus expensive.
  • Another object of the invention is to provide an error correcting system which can perform algebraic operations in a short time.
  • An error correcting system receives double correction BCH codes each consisting of M data symbols and four parity symbols, each consisting of m bits and represented by the following generated polynomial:
  • ⁇ is the origin element of Galois field GF (2 m ), and which find the roots of the following error location polynomial:
  • This system comprises:
  • syndrome generating means for generating four syndromes S 0 , S 1 , S 2 and S 3 from the double correction BCH codes
  • error location calculating means comprising:
  • a first multiplying/adding section for multiplying and adding the four syndromes S 0 , S 1 , S 2 and S 3 to obtain three syndromes S a , S b and S c which are given as follows:
  • a second multiplying/adding section for performing multiplication and addition by substituting ⁇ 0 - ⁇ M+3 for x in the following polynomial obtained by transforming said error location polynomial f.sub.(x) :
  • a third multiplying/adding section for adding ⁇ i and ⁇ j and multiplying ⁇ i by ⁇ j , thereby finding the coefficients ⁇ 1 , ⁇ 2 which define error locations;
  • error pattern calculating means comprising a fourth multiplying/adding means for obtaining an error pattern e i from ⁇ i and ⁇ j by performing the following multiplication:
  • the system need not be provided with a memory with a large capacity, and can have a simple structure and be inexpensive. Further, the system can process data at a high speed.
  • FIG. 1 is a block diagram of a known error data correcting system
  • FIG. 2 is a block diagram of an error location polynomial calculator used in the system shown in FIG. 1;
  • FIG. 3 is a block diagram of a DAD device to which the present invention is applied;
  • FIG. 4 is a block diagram of the main part of an error data correcting system according to the invention.
  • FIG. 5 is a timing chart illustrating the operation of the system shown in FIG. 4;
  • FIG. 6 is a block diagram of a multiplier used in the operation unit of the system shown in FIG. 4;
  • FIG. 7 is a timing chart illustrating the operation of the multiplier shown in FIG. 6;
  • FIG. 8 is a circuit diagram an ⁇ multiplier circuit used in the multiplier shown in FIG. 6;
  • FIG. 9 is a circuit diagram of ⁇ 2 multiplier circuits used in the multiplier shown in FIG. 6.
  • optical digital audio disk (DAD) device which uses compact disks (CD) will be described.
  • the DAD device comprises a disk motor 111 for rotating a turntable 112.
  • an optical disk 113 is mounted on the turntable 112 on the turntable 112 .
  • the disk 113 has pits which corresponds to digital audio signals (i.e., PCM codes) which have been EFM-modulated and interleaved.
  • An opitcal pickup 114 emits a laser beam from a semiconductor laser 114a.
  • the laser beam passes through a beam splitter 114b and is focused by an object lens 114c.
  • the beam illuminates the track of the optical disk 113.
  • the beam reflected from the pits passes through the objective lens 114c and the beam splitter 114b. It is then guided to a four-element photodetector 114d.
  • the photodetector 114d converts the laser beam into four signals.
  • the pickup 114 is moved by a pickup feed motor 115 in the radial direction of the optical disk 113.
  • the four signals from the photodetector 114d are supplied to a matrix circuit 116 and undergo a specific matrix operation.
  • the matrix circuit 116 generates a focus error signal F, a tracking error signal T, and a high-frequency signal RF.
  • the focus error signal F and a focus search signal from a focus search circuit 110 are used to drive a focus servo system of the optical pickup 114.
  • the tracking error signal T and the search control signal supplied from a system controller 117 are used to drive a tracking servo system of the optical pickup 114 and to control the pickup feed motor 115.
  • the high-frequency signal RF is supplied to a reproduced signal processing system 118 as a major reproduced signal component.
  • the signal RF is supplied to a waveform shaping circuit 120 which is controlled by a slice level (eye pattern) detector 119.
  • the waveform shaping circuit 120 divides the input signal into an unnecessary analog component and a necessary data component.
  • the necessary data component is supplied to a sync clock reproducing circuit 121 of a PLL type and also to an edge detector 122a of a first signal processing system 122.
  • a sync clock from the sync clock reproducing circuit 121 is supplied to a clock generating circuit 122b of the first signal processing system 122.
  • the clock generating circuit 122b In response to the sync clock, the clock generating circuit 122b generates a clock for dividing a sync signal into components.
  • the necessary data component from the edge detector 122a is supplied to a sync signal detector 122c.
  • the sync signal detector 122c divides the data components in response to a sync signal dividing clock from the clock generating circuit 122b.
  • the necessary data component from the edge detector 122a is supplied also to a demodulating circuit 122d and then is EFM-demodulated.
  • a sync signal from the sync signal detector 122c is supplied to a sync signal protecting circuit 122e and then to a timing signal generating circuit 122f.
  • a clock from the clock generating circuit 122b is supplied also to the timing signal generating circuit 122f.
  • the timing signal generating circuit 122f generates a timing signal for processing the input data.
  • An output signal from the demodulating circuit 122d is supplied through a data bus input/output control circuit 122g to an input/output control circuit 123a of a second signal processing system 123.
  • the output signal from the demodulating circuit 122d contains a subcode (i.e., a control signal) and a display signal component.
  • the display signal component is supplied to a control display processing circuit 122h and the subcode is supplied to a subcode processing circuit 122i.
  • the subcode processing circuit 122i detects an error, if any, from the subcode; and then corrects the error and generates subcode data.
  • the subcode data is supplied to the system controller 117 through an interface circuit 122q which is connected to the system controller 117.
  • the system controller 117 includes a microcomputer, an interface circuit, and a driver integrated circuit. In response to an instruction from a control switch 124 the system controller 117 controls the DAD device in a desired manner and causes a display device 125 to display the subcode (e.g., index data about a piece of music to be reproduced).
  • the subcode e.g., index data about a piece of music to be reproduced.
  • a timing signal from the timing generating circuit 122f is supplied through a data selecting circuit 122j to the data bus input/output control circuit 122g and controls the data bus input/output control circuit 122g.
  • the timing signal is also supplied to a frequency detector 122k, a phase detector 122l and further to a PWM modulator 122m.
  • the timing signal from the PWM modulator 122m then undergoes automatic frequency control (AFC) and automatic phase control (APC) so as to rotate the disk motor 111 at a constant linear velocity (CLV).
  • AFC automatic frequency control
  • API automatic phase control
  • the phase detector 122l is connected to receive a system clock from a system clock generating circuit 122p, which operates under the control of an output signal from a quartz crystal oscillator 122n.
  • the demodulated data from the input/output control circuit 123a of the second signal processing system 123 is supplied through a data output circuit 123e to a D/A (digital-to-analog) converter 126 after it has undergone the necessary error correction, deinterleaving and data supplementation at a syndrome detector 123b, at an error pointer control circuit 123c, and at an error correction circuit 123d.
  • the second signal processing system 123 includes an external memory control circuit 123f.
  • the control circuit 123f cooperates with the data selecting circuit 122j of the first signal processing system 122 to control an external memory 127 which stores the data necessary for correcting errors. Under the control of the circuits 123f and 122j, the data is read from the external memory 127 and is supplied to the input/output control circuit 123a.
  • the second signal processing system 123 further comprises a timing control circuit 123g and a muting control circuit 123h.
  • the timing control circuit 123g is so designed as to supply, in response to a system clock from the system clock generating circuit 122p, a timing control signal which is necessary in correcting errors, supplementing data and converting digital data into analog data.
  • the muting control circuit 123h in response to a control signal from the error pointer control circuit 123c or from the system controller 117, is designed to perform the specific muting control which is necessary in supplementing data, and in starting and ending DAD reproduction.
  • An audio signal, or an analog output signal from the D/A converter 126 is supplied through a low pass filter 128 and an amplifier 129 to a loudspeaker 130.
  • a double correction BCH code consists of symbols which are the elements of the Galois field GF(2 8 ) and which are:.
  • U 0 , - U M-1 are data symbols, each being an 8-bit symbol.
  • P 0 -P 3 are parity symbols. That is, M data symbols and four parity symbols make the double correction BCH code. Equation 12 implies that the parity symbols are regarded as being identical to the data symbols so far as error correction is concerned. Equation 12 may be changed to:
  • S 0 -S 3 are syndromes, each representing the value given in Equation 17 in case two symbols error of (M+4) symbols constitute the double correction BCH code.
  • Equation 20 ⁇ 1 and ⁇ 2 obtained are then substituted in Equation 20.
  • x in Equation 20 is substituted by ⁇ 0 , ⁇ 1 , ⁇ 2 . . . ⁇ M+3 , one after another.
  • the object of the present invention is to provide a system which can correct erroneous data, and which can perform multiplication and division on the elements of a Galois field without using a memory having a large memory capacity.
  • a memory of a large memory capacity it would be difficult to divide the elements of a Galois field with a generator polynomial g.sub.(x), though it is possible to perform relatively simple multiplication. It is therefore preferred that as liitle division as possible be done in order to obtain the error locations and the error patterns.
  • the error locations are generated in the following manner.
  • Equations 18 and 19 can be changed to: ##EQU16##
  • Equation 20 Substituting Equations 23 and 24 in Equation 20 will yield: ##EQU17##
  • the error patterns are generated in the following manner.
  • Equation 21A which represents the operation of division is: ##EQU18##
  • Equation 21A Equation 21A
  • Equation 26 is substituted in Equation 23:
  • Equation 27 In order to locate errors it is necessary to substitute x in Equation 27 with ⁇ 0 , ⁇ 1 , ⁇ 2 . . . ⁇ M+3 . While substituting x by ⁇ 0 , ⁇ 1 , ⁇ 2 . . . ⁇ M+3 one after another, the value for x which would satisfy the following Equation 28 is calculated.
  • Equation 28 x in Equation 28 must be substituted by ⁇ 0 to ⁇ 31 .
  • the greatest element of the Galois field GF(2 8 ) is:
  • ⁇ 255 is identical to ⁇ 0 .
  • ⁇ 255 is a cyclic code for elements ⁇ 0 - ⁇ 254 . It is therefore sufficient to substitute only ⁇ 0 - ⁇ 254 for x in Equation 28 in order to locate the errors.
  • Equation 28 is changed to the following:
  • the data processing time can be reduced if reciprocal data which is necessary for obtaining the error pattern is given while the errors are being located.
  • FIG. 4 is a block diagram of the error location (polynomial) calculating unit which is included chiefly in the correction circuit 123d of the second signal processing system 123 shown in FIG. 3.
  • the calculating unit performs various algebraic operations in order to decode a Reed-Solomon code (i.e., error correction code), which as was mentioned before is a kind of a BCH code used in correcting errors, and thereby to generate the error locations and the error patterns.
  • the only algebraic operations which need to be performed in order to generate the error locations and the error patterns are addition and multiplication; no division is necessary.
  • the error location calculating unit decodes a Reed-Solomon code as will be described below.
  • Reproduced symbols W M+3 , W M+2 , W M+1 . . . , W 0 from a input bus (I-BUS) 40 are supplied to a syndrome generator (SYNDROME GEN.) 41 which corresponds to the syndrome detector 123b shown in FIG. 3.
  • the syndrome generator 41 generates syndromes S 0 -S 3 which are given by Equations 16.
  • Syndromes S 0 -S 3 are stored into a memory (RAM) 43 through a transfer bus (A-BUS) 42A. Syndromes S 0 -S 3 are read out from the memory 43 whenever necessary.
  • Equation 22 S a , S b and S c which are represented by Equation 22.
  • the arithmetic logic unit 44 is so designed as to perform addition and multiplication on the elements of the Galois field. It includes a multiplier which will next be described.
  • S c , S b and S a are supplied to a latch circuit (LAT-S c ) 46C, a latch circuit (LAT-S b ) 46B and a latch circuit (LAT-S a ) 45A, respectively.
  • S c , S b and S a are supplied to a latch circuit (LAT-1) 46D, a ⁇ multiplying register (REG ⁇ ) 47A and an ⁇ 2 multiplying register (REG ⁇ 2 ) 47B, respectively, when a set pulse SP is supplied to the latch circuit 46D, the ⁇ multiplying register 47A and the ⁇ 2 multiplying register 47B.
  • 1 is supplied to a r4 register (REG r4) 47C.
  • the ⁇ multiplying register 47A multiplies its contents by ⁇ upon receipt of a clock pulse CP.
  • the ⁇ 2 multiplying register 47B multiplies its contents by ⁇ 2 upon receipt of a clock pulse CP.
  • the r4 register 47C is initially set to 1 and multiplies its contents by ⁇ every time it receives a clock pulse CP. In this embodiment, the r4 register 47C generates ⁇ 0 to ⁇ 31 .
  • x in quadratic Equation 26 is substituted by ⁇ 0 to ⁇ 31 as the 31 clock pulses CP are supplied.
  • the zero detector (0-DET) 49 When the zero detector (0-DET) 49 detects 0, it generates an output signal.
  • the contents of the r4 register (REG r4) 47C are then stored into a latch circuit (LAT ⁇ i ) 46E and a latch circuit (LAT ⁇ j ) 46F, whereby ⁇ i and ⁇ j which define the location of the error can be determined.
  • Data representing ⁇ i and ⁇ j are transferred to the arithmetic logic unit (ALU) 44 through the transfer bus (B-BUS) 42B.
  • the arithmetic logic unit (ALU) 44 multiplies ⁇ i by ⁇ j as indicated by Equation 19 and adds ⁇ i to ⁇ j as indicated by Equation 18, thus generating error locations ⁇ 1 and ⁇ 2 .
  • an output from the ⁇ multiplying register (REG ⁇ ) 47A is supplied to a gate circuit (GATE) 50.
  • the gate circuit (GATE) 50 generates an output which represents the reciprocal of the output from the register (REG ⁇ ) 47A (see the table given above). More specifically, when an output from the ⁇ multiplying register (REG ⁇ ) 47A represents any value shown in the right column of the table (i.e., ⁇ 32m column), the gate circuit (GATE) 50 generates a load pulse.
  • Data representing one of the values shown in the left column of the table i.e., the ⁇ -32m column
  • the gate circuit (GATE) 50 is then read from the gate circuit (GATE) 50 and stored into a latch circuit (LAT ⁇ -32m ) 46G.
  • the contents of the r4 register (REG r4) 47C i.e., data ⁇ q
  • LAT ⁇ q are stored into a latch circuit (LAT ⁇ q ) 46H.
  • the data representing ⁇ q and the data representing ⁇ -32m are transferred to the arithmetic logic unit (ALU) 44 through the transfer bus (B-BUS) 42B.
  • Data representing S a is transferred also to the arithmetic logic unit (ALU) 44 through the transfer bus (B-BUS) 42B.
  • the unit (ALU) 44 performs multiplication of S a ⁇ q ⁇ -32m as in Equation 30, thereby obtaining a reciprocal ( ⁇ i + ⁇ j ) -1 . Thereafter, the unit (ALU) 44 performs multiplication as given by Equation 21A' and addition as given by Equation 21B, thereby generating error patterns e 1 and e 2 .
  • the error can be corrected according to the method described above with reference to FIG. 1.
  • (a) is a set pulse SP
  • (b) is a clock pulse CP
  • (c) is the contents of the latch circuit (LAT 1)
  • (d) is the contents of the ⁇ multiplying register (REG ⁇ )
  • (e) is the contents of the ⁇ 2 multiplying register (REG ⁇ 2 )
  • (f) is an output from the adder circuit (ADR2)
  • (g) is an output from the zero detector (0-DET)
  • (h) is the contents of the r4 register (REG r4)
  • (i) is the contents of the latch circuit (LAT ⁇ i )
  • (j) is the contents of the latch circuit (LAT ⁇ j )
  • (k) is a load pulse from the gate circuit (GATE)
  • Equation 31 implies that the first term in the right side can be determined in one step and the second term in the right side can be determined in another step.
  • FIG. 6 is a block diagram of the multiplier which is included in the arithmetic logic unit (ALU) 44.
  • Multiplicand data B( ⁇ ) is latched by a latch circuit 51
  • multiplier data C( ⁇ ) is latched by a latch circuit 52.
  • An output from the latch circuit 51 is supplied to the first input terminal IN 11 of a selector circuit 54 and also to the second input teminal IN 12 of the circuit 54 through an ⁇ multiplying circuit 53.
  • From the latch circuit 52 the coefficients c 0 to c 7 of the multiplier data C( ⁇ ) are supplied at the same time to the seven input terminals of a selector circuit 55, respectively.
  • the selector circuits 54 and 55 are connected to receive a selector signal H/L.
  • a selector signal having a high level H is supplied to both selector circuits 54 and 55, the multiplier performs the multiplication given by the following Equation 32.
  • a selector signal having a low level L is supplied to both selector circuits 54 and 55, the multiplier performs the multiplication given by Equation 33:
  • the multiplier calculates Equation 32 in the following manner.
  • the selector circuit 54 Upon receipt of a selector signal of a high level H, the selector circuit 54 selects the input data [ ⁇ B( ⁇ )] supplied to its second input terminal IN 12 , and the selector circuit 55 supplies output c 1 , c 3 , c 5 and c 7 from its first, second, third and fourth output terminals, respectively.
  • Data [ ⁇ B( ⁇ )] is supplied to a selector circuit 56 and also to an ⁇ 2 multiplying circuit 57.
  • the selector circuit 56 has its gate controlled by output c 1 from the selector circuit 55. Upon receipt of output c 1 the selector circuit 56 supplies an output [ ⁇ B( ⁇ )] to one input terminal of an exclusive OR circuit 58.
  • the ⁇ 2 multiplying circuit 57 multiplies the input data [ ⁇ B( ⁇ )] by ⁇ 2 , thereby generating an output [ ⁇ 3 B( ⁇ )].
  • Output [ ⁇ 3 B( ⁇ )] from the ⁇ 2 multiplying circuit 57 is supplied to a selector circuit 59 and also to an ⁇ 2 multiplying circuit 60.
  • the selector circuit 59 has its gate controlled by output c 3 from the selector circuit 55. Upon receipt of output c 3 it supplies an output [ ⁇ 3 B( ⁇ )] to the other input terminal of the exclusive OR circuit 58. Output [ ⁇ B( ⁇ )+ ⁇ 3 B( ⁇ )] from the exclusive OR circuit 58 is supplied to one input terminal of an exclusive OR circuit 61.
  • the ⁇ 2 multiplying circuit 60 multiplies the input data [ ⁇ 2 B( ⁇ )] by ⁇ 2 , thereby generating an output [ ⁇ 5 B( ⁇ )].
  • Output [ ⁇ 5 B( ⁇ )] is supplied to a selector circuit 62 and also to an ⁇ 2 multiplying circuit 63.
  • the selector circuit 62 has its gate controlled by output c 5 from the selector circuit 55. Upon receipt of output c 5 it supplies an output [ ⁇ 5 B( ⁇ )] to the other input terminal of the exclusive OR circuit 61.
  • Output [ ⁇ B( ⁇ )+ ⁇ 3 B( ⁇ )+ ⁇ 5 B( ⁇ )] from the exclusive OR circuit 61 is supplied to one input terminal of an exclusive OR circuit 63.
  • Output [ ⁇ 7 B( ⁇ )] is supplied to a selector circuit 65.
  • the selector circuit 65 has its gate controlled by output c 7 from the selector circuit 55. Upon receipt of output c 7 it supplies an output [ ⁇ 7 B( ⁇ )] to the other input terminal of the exclusive OR circuit 63.
  • Output [ ⁇ B( ⁇ )+ ⁇ 3 B( ⁇ )+ ⁇ 5 B( ⁇ )+ ⁇ 7 B( ⁇ )] from the exclusive OR circuit 63 is supplied to a latch circuit 66 and also to one input terminal of an exclusive OR circuit 67.
  • the output from the latch circuit 66 is supplied to the other input terminal of the exclusive OR circuit 67.
  • the output from the exclusive OR circuit 67 is supplied to a latch circuit 68.
  • the latch circuit 66 will store data [ ⁇ B( ⁇ )](c 7 ⁇ 6 +c 5 ⁇ 4 +c 3 ⁇ 2 +c 1 ).
  • the latch circuits 51 and 52 are controlled by a latch signal LP 1 generated by a gate circuit 69 which is connected to receive 2-phase reference clocks CP 1 and CP 2 .
  • the latch circuit 66 is controlled by a latch signal LP 2 generated by the gate circuit 69.
  • the latch circuit 68 is controlled by a latch signal LP 3 generated by the gate circuit 69.
  • FIG. 7 is a timing chart illustrating how the multiplier operates which is included in the arithmetic logic unit (ALU) 44.
  • ALU arithmetic logic unit
  • (a) is a reference clock CP 1
  • (b) is a reference clock CP 2
  • (c) indicates when to input the multiplicand data B( ⁇ )
  • (d) indicates when to input the multiplier data C( ⁇ )
  • (e) is a latch signal LP 1
  • (f) is a selector signal H/L
  • (g) is a latch signal LP 2
  • (h) indicates the timing of latching data in the latch circuit 66
  • (i) is a latch signal LP 3
  • (j) indicates when data should be latched in the latch circuit 68.
  • ⁇ is the root of the generator polynomial g(x) of the Galois field GF(2 8 ), which is given by:
  • Equation 35 means that the ⁇ multiplying circuit 53 may be comprised of exclusive OR circuits (EX-OR 41 ) to (EX-OR 43 ) as shown in FIG. 8.
  • Equation 36 it is obvious from Equation 36 that the ⁇ 2 multiplying circuits 57, 60 and 64 can be comprised of exclusive OR circuits (EX-OR 51 ) to (EX-OR 55 ) as illustrated in FIG. 9.
  • the present invention is not limited to the embodiment described above. Variations are possible within the spirit of the invention, and the invention may be applied to devices other than a DAD device.
  • the error data correcting system of the invention can be used in combination with an apparatus for recording digital data such as PCM codes on a magnetic tape, for reproducing the data from the tape and for transmitting the data.
  • the error data correcting system can perform multiplication and addition on the elements of a Galois field thereby locating errors and generating error patterns without using a memory having a large capacity, such as a logarithm buffer or an antilogarithm buffer.
  • the system is therefore simple, inexpensive, and can process data at a high speed.

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US4637021A (en) * 1983-09-28 1987-01-13 Pioneer Electronic Corporation Multiple pass error correction
US4682333A (en) * 1984-06-28 1987-07-21 Mitsubishi Denki Kabushiki Kaisha Decoder for decoding a two-stage encoded code
US4694455A (en) * 1984-09-04 1987-09-15 Kokusai Denshin Denwa Co., Ltd. Decoding method for multiple bit error correction BCH codes
US4706248A (en) * 1984-04-13 1987-11-10 Sharp Kabushiki Kaisha Semiconductor integrated circuit with error correction function incorporated therein
US4747103A (en) * 1985-03-21 1988-05-24 Canon Kabushiki Kaisha Signal processing apparatus for correcting decoding errors
US4852098A (en) * 1986-10-22 1989-07-25 Thomson-Csf Polynomial operator in galois fields and a digital signal processor comprising an operator of this type
US4864573A (en) * 1986-09-25 1989-09-05 Robert Bosch Gmbh Apparatus for reproducing a pcm modulated signal, comprising a muting circuit
US4899341A (en) * 1987-01-28 1990-02-06 Nec Corporation Error correction circuit
US5107507A (en) * 1988-05-26 1992-04-21 International Business Machines Bidirectional buffer with latch and parity capability
GB2253975A (en) * 1991-03-20 1992-09-23 Samsung Electronics Co Ltd Processing images, sound or data encoded in error correcting code using Galois Field arithmetic
US5313474A (en) * 1991-07-26 1994-05-17 Qlogic Corporation Method and apparatus to determine the log of an element in GF(2m) with the help of a small adjustable size table
US5483236A (en) * 1993-12-20 1996-01-09 At&T Corp. Method and apparatus for a reduced iteration decoder
US5537429A (en) * 1992-02-17 1996-07-16 Mitsubishi Denki Kabushiki Kaisha Error-correcting method and decoder using the same
US5774648A (en) * 1996-10-02 1998-06-30 Mitsubishi Semiconductor Of America, Inc. Address generator for error control system
US5898708A (en) * 1994-06-16 1999-04-27 Kabushiki Kaisha Toshiba Error correction apparatus and method
WO1999039270A1 (en) * 1998-02-02 1999-08-05 Motorola Inc. Polynomial calculator device, and method therefor
US6023782A (en) * 1996-12-13 2000-02-08 International Business Machines Corporation RAM based key equation solver apparatus
EP1037148A1 (en) * 1999-03-15 2000-09-20 Texas Instruments Incorporated Error coding method
US20030151838A1 (en) * 2002-02-08 2003-08-14 Hideki Sawaguchi Data decoding method and circuit and information recording and reproducing apparatus using the same
RU2235424C2 (ru) * 1998-12-04 2004-08-27 Квэлкомм Инкорпорейтед Перемежитель турбокода, использующий линейные конгруэнтные последовательности
US20080016432A1 (en) * 2006-07-12 2008-01-17 Peter Lablans Error Correction in Multi-Valued (p,k) Codes
US20080082901A1 (en) * 2006-08-28 2008-04-03 Kabushiki Kaisha Toshiba Semiconductor memory device
US20090172501A1 (en) * 2006-03-03 2009-07-02 Ternarylogic Llc Multi-State Symbol Error Correction in Matrix Based Codes
US20100115383A1 (en) * 2008-10-31 2010-05-06 Kabushiki Kaisha Toshiba Memory device with an ecc system
US20100125771A1 (en) * 2008-11-18 2010-05-20 Fujitsu Limited Error judging circuit and shared memory system
US7962836B1 (en) * 2000-01-06 2011-06-14 Supertalent Electronics, Inc. Electronic data flash card with bose, ray-chaudhuri, hocquenghem (BCH) error detection/correction
US11016845B2 (en) * 2015-01-08 2021-05-25 Micron Technology, Inc. Semiconductor device having error correction code (ECC) circuit
CN113972917A (zh) * 2020-07-23 2022-01-25 中国科学院苏州纳米技术与纳米仿生研究所 面向puf的bch纠错码硬件电路实现方法及bch译码器

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JPH0728227B2 (ja) * 1985-06-07 1995-03-29 ソニー株式会社 Ｂｃｈ符号の復号装置
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KR970003979B1 (ko) * 1993-11-29 1997-03-24 삼성전자 주식회사 갈로이스 필드상의 승산기
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Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4618955A (en) * 1983-02-25 1986-10-21 U.S. Philips Corporation Digital data transmission system
US4608692A (en) * 1983-09-06 1986-08-26 Kabushiki Kaisha Toshiba Error correction circuit
US4637021A (en) * 1983-09-28 1987-01-13 Pioneer Electronic Corporation Multiple pass error correction
US4706248A (en) * 1984-04-13 1987-11-10 Sharp Kabushiki Kaisha Semiconductor integrated circuit with error correction function incorporated therein
US4682333A (en) * 1984-06-28 1987-07-21 Mitsubishi Denki Kabushiki Kaisha Decoder for decoding a two-stage encoded code
US4694455A (en) * 1984-09-04 1987-09-15 Kokusai Denshin Denwa Co., Ltd. Decoding method for multiple bit error correction BCH codes
US4747103A (en) * 1985-03-21 1988-05-24 Canon Kabushiki Kaisha Signal processing apparatus for correcting decoding errors
US4864573A (en) * 1986-09-25 1989-09-05 Robert Bosch Gmbh Apparatus for reproducing a pcm modulated signal, comprising a muting circuit
US4852098A (en) * 1986-10-22 1989-07-25 Thomson-Csf Polynomial operator in galois fields and a digital signal processor comprising an operator of this type
US4899341A (en) * 1987-01-28 1990-02-06 Nec Corporation Error correction circuit
US5107507A (en) * 1988-05-26 1992-04-21 International Business Machines Bidirectional buffer with latch and parity capability
GB2253975A (en) * 1991-03-20 1992-09-23 Samsung Electronics Co Ltd Processing images, sound or data encoded in error correcting code using Galois Field arithmetic
GB2253975B (en) * 1991-03-20 1994-05-25 Samsung Electronics Co Ltd An apparatus operating on a galois field over gf (2m)
US5313474A (en) * 1991-07-26 1994-05-17 Qlogic Corporation Method and apparatus to determine the log of an element in GF(2m) with the help of a small adjustable size table
US5537429A (en) * 1992-02-17 1996-07-16 Mitsubishi Denki Kabushiki Kaisha Error-correcting method and decoder using the same
US5483236A (en) * 1993-12-20 1996-01-09 At&T Corp. Method and apparatus for a reduced iteration decoder
US5898708A (en) * 1994-06-16 1999-04-27 Kabushiki Kaisha Toshiba Error correction apparatus and method
US5774648A (en) * 1996-10-02 1998-06-30 Mitsubishi Semiconductor Of America, Inc. Address generator for error control system
US6023782A (en) * 1996-12-13 2000-02-08 International Business Machines Corporation RAM based key equation solver apparatus
US5939693A (en) * 1998-02-02 1999-08-17 Motorola Inc. Polynomial calculator device, and method therefor
WO1999039270A1 (en) * 1998-02-02 1999-08-05 Motorola Inc. Polynomial calculator device, and method therefor
RU2235424C2 (ru) * 1998-12-04 2004-08-27 Квэлкомм Инкорпорейтед Перемежитель турбокода, использующий линейные конгруэнтные последовательности
EP1037148A1 (en) * 1999-03-15 2000-09-20 Texas Instruments Incorporated Error coding method
US7962836B1 (en) * 2000-01-06 2011-06-14 Supertalent Electronics, Inc. Electronic data flash card with bose, ray-chaudhuri, hocquenghem (BCH) error detection/correction
US7213195B2 (en) 2002-02-08 2007-05-01 Hitachi Global Storage Technologies Data decoding method and circuit and information recording and reproducing apparatus using the same
US7024617B2 (en) * 2002-02-08 2006-04-04 Hitachi, Ltd. Data decoding method and circuit and information recording and reproducing apparatus using the same
US20030151838A1 (en) * 2002-02-08 2003-08-14 Hideki Sawaguchi Data decoding method and circuit and information recording and reproducing apparatus using the same
US20090172501A1 (en) * 2006-03-03 2009-07-02 Ternarylogic Llc Multi-State Symbol Error Correction in Matrix Based Codes
US8832523B2 (en) * 2006-03-03 2014-09-09 Ternarylogic Llc Multi-state symbol error correction in matrix based codes
US20080016432A1 (en) * 2006-07-12 2008-01-17 Peter Lablans Error Correction in Multi-Valued (p,k) Codes
US9203436B2 (en) * 2006-07-12 2015-12-01 Ternarylogic Llc Error correction in multi-valued (p,k) codes
US8001448B2 (en) * 2006-08-28 2011-08-16 Kabushiki Kaisha Toshiba Semiconductor memory device
US20080082901A1 (en) * 2006-08-28 2008-04-03 Kabushiki Kaisha Toshiba Semiconductor memory device
US20100115383A1 (en) * 2008-10-31 2010-05-06 Kabushiki Kaisha Toshiba Memory device with an ecc system
US7962838B2 (en) * 2008-10-31 2011-06-14 Kabushiki Kaisha Toshiba Memory device with an ECC system
US8327236B2 (en) * 2008-11-18 2012-12-04 Fujitsu Limited Error judging circuit and shared memory system
US20100125771A1 (en) * 2008-11-18 2010-05-20 Fujitsu Limited Error judging circuit and shared memory system
US11016845B2 (en) * 2015-01-08 2021-05-25 Micron Technology, Inc. Semiconductor device having error correction code (ECC) circuit
US11436084B2 (en) 2015-01-08 2022-09-06 Micron Technology, Inc. Semiconductor device having error correction code (ECC) circuit
CN113972917A (zh) * 2020-07-23 2022-01-25 中国科学院苏州纳米技术与纳米仿生研究所 面向puf的bch纠错码硬件电路实现方法及bch译码器

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KR840004272A (ko) 1984-10-10
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