JPS54125901A - Error correction system - Google Patents
Error correction systemInfo
- Publication number
- JPS54125901A JPS54125901A JP3295578A JP3295578A JPS54125901A JP S54125901 A JPS54125901 A JP S54125901A JP 3295578 A JP3295578 A JP 3295578A JP 3295578 A JP3295578 A JP 3295578A JP S54125901 A JPS54125901 A JP S54125901A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- bits
- bit
- switch
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/17—Burst error correction, e.g. error trapping, Fire codes
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Abstract
PURPOSE:To enhance the correcting capacity for the continuos burst error up to the m-bit via the grown polynomial up to the m-ordered place regardless of the position of the information bit. CONSTITUTION:Switch 3 has a contact to contact (a) until the full bits 1-K are supplied for information bit input e1 and then connected to shift register 5. When switch 3 is changed to contact (b), the contact to (b) is kept up to the full bits k + 1-k + m of parity bit C2 which are the output of register 5 for input e1. And gate 1 opens for 1-k and closes for k + 1-k + m. While switch 4 has first a contact to (a) for input e1 and 1-k + m bits and then connected to register 6, and gate 2 opens for 1-k + m bits and closes for k + m + 1-k + 2m bits respectively. Thus, the continuous burst error up to the m-bit can be corrected via the grown polynomial up to the m-th order at any optional position of the information bit, enhancing the error correcting capacity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3295578A JPS54125901A (en) | 1978-03-24 | 1978-03-24 | Error correction system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3295578A JPS54125901A (en) | 1978-03-24 | 1978-03-24 | Error correction system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54125901A true JPS54125901A (en) | 1979-09-29 |
Family
ID=12373347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3295578A Pending JPS54125901A (en) | 1978-03-24 | 1978-03-24 | Error correction system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54125901A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58219852A (en) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | Correcting circuit of error |
JPS58219851A (en) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | Correcting circuit of error |
JPS58219849A (en) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | Correcting circuit of error |
JPS59131238A (en) * | 1982-09-13 | 1984-07-28 | シ−・アイ・アイ・ハネウエル・ブル | Encoding detecting and correcting system for transmission error in binary message |
JPH1011307A (en) * | 1996-06-27 | 1998-01-16 | Nec Corp | Main storage device |
-
1978
- 1978-03-24 JP JP3295578A patent/JPS54125901A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58219852A (en) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | Correcting circuit of error |
JPS58219851A (en) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | Correcting circuit of error |
JPS58219849A (en) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | Correcting circuit of error |
JPS638649B2 (en) * | 1982-06-15 | 1988-02-24 | Tokyo Shibaura Electric Co | |
JPS638651B2 (en) * | 1982-06-15 | 1988-02-24 | Tokyo Shibaura Electric Co | |
JPS638650B2 (en) * | 1982-06-15 | 1988-02-24 | Tokyo Shibaura Electric Co | |
JPS59131238A (en) * | 1982-09-13 | 1984-07-28 | シ−・アイ・アイ・ハネウエル・ブル | Encoding detecting and correcting system for transmission error in binary message |
JPH0126209B2 (en) * | 1982-09-13 | 1989-05-23 | Bull Sa | |
JPH1011307A (en) * | 1996-06-27 | 1998-01-16 | Nec Corp | Main storage device |
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