US4123779A - Turntable rotational speed and phase control system for a video disc play/record apparatus - Google Patents

Turntable rotational speed and phase control system for a video disc play/record apparatus Download PDF

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US4123779A
US4123779A US05/777,478 US77747877A US4123779A US 4123779 A US4123779 A US 4123779A US 77747877 A US77747877 A US 77747877A US 4123779 A US4123779 A US 4123779A
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turntable
signal
output
responsive
phase
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Arthur M. Goldschmidt
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Lockheed Martin Corp
RCA Corp
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RCA Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B19/00—Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
    • G11B19/20—Driving; Starting; Stopping; Control thereof
    • G11B19/24—Arrangements for providing constant relative speed between record carrier and head

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  • the present invention relates generally to control systems for a disc play/record apparatus, and particularly to novel and improved systems for control of turntable rotational speed and phase for recording and playback of high-density information records, such as video disc records of the type described in co-pending U.S. application Ser. No. 668,495 -- Spong filed Mar. 19, 1976.
  • the light output of a recording beam which is intensity modulated in accordance with a signal to be recorded, is focused upon the surface of the disc as the disc is rotated.
  • an information track is formed as a succession of pits in the absorptive layer.
  • a photodetector positioned to receive light reflected from the information track which is modulated in intensity by the pits passage through the path of light, develops a signal representative of the recorded information.
  • the rotational velocity of a motor driven turntable supporting the disc record is controlled by means of a speed loop which synchronizes the speed of the motor with synchronizing information accompanying the information to be recorded and which synchronization information may be available from an external source during information recovery operations (e.g., a sync generator).
  • a speed loop which synchronizes the speed of the motor with synchronizing information accompanying the information to be recorded and which synchronization information may be available from an external source during information recovery operations (e.g., a sync generator).
  • a novel arrangement for the speed loop includes a motor driven tachometer and a phase locked loop for stabilizing the output of the tachometer about a frequency which is a multiple of the rate of a synchronization signal.
  • the synchronization signal may be the horizontal sync pulse.
  • the phase locked loop allows for a smooth transformation for a tachometer output bearing no harmonic relationship to the synchronization signal into an output bearing such a relationship.
  • this novel arrangement provides the system with a source of highly stable and accurate timing pulses, representative of increments of a horizontal line for the illustrative video recordings.
  • the output of a first detector responsive to the frequency and phase differences between the output of the phase locked loop and the output of a source of reference horizontal sync signals, is utilized to provide a driving signal for controlling the speed of a turntable motor.
  • This driving signal is applied through a compensation network to power amplifiers which are coupled to the motor input terminals to complete the speed control loop.
  • one output of the first detector is utilized to control a flip-flop.
  • the output of the initially reset flip-flop provides, through an FET switch, a direct driving signal to the power amplifiers.
  • the one output of the detector triggers the flip-flop into a set state thereby discontinuing the direct drive signal.
  • the acceleration and deceleration of the motor is adjusted to assure the desired phase relationship between the start of a frame of recorded information and the synchronization frame signal.
  • a position loop in an illustrative implementation of these principles in use for video recordings, includes a phase tachometer providing an output in response to the rotation of the turntable and means, cooperating with the speed loop for altering the phase of rotation of the turntable.
  • the position loop further includes means for rendering the phase altering means responsive to the phase difference between frame synchronization signals and the output of the phase tachometer.
  • discrepancies between the original mounting position during a previous recording, of a partially recorded disc and its current mounting position on the turntable are illustratively compensated for by means of two time delay circuits respectively provided in the speed and position loops.
  • the position loop incorporates a delay circuit which subjects the output of the play/record delay circuit to a time delay which varies, in increments of a whole horizontal line, correspondingly to the magnitude of the detected mounting error.
  • the speed loop incorporates a delay circuit which subjects the output of the phase locked loop to a time delay which varies, in increments of 1/80th of a horizontal line, corresponding to the magnitude of the remaining detected mounting error after error compensation in the position loop.
  • a novel arrangement is provided for control of the energization of a relay coupling the power amplifiers and the motor, with a user actuated run/stop switch and a detector for the output of the phase tachometer in an interrelationship that provides fast stop for the motor as well as overspeed protection.
  • a motor stop switch In an illustrative implementation of the aforementioned feature, user activation of a motor stop switch results in the development in logic circuits of signals which inhibit the power amplifiers and which energize the relay to a position where a source of reverse potential is coupled to the motor. These logic circuits are also responsive to an overspeed condition and momentarily effect an energization of the relay.
  • FIG. 1 provides a representation, in block diagram form, of a turntable rotational speed and phase control system in accordance with principles of the present invention
  • FIGS. 2-5 provide representations, in schematic diagram form showing circuit details of the system of FIG. 1.
  • a disc 11 is shown supported on a turntable 13 driven by a uni-directional DC motor 15.
  • a disc 13 may be of a type suitable for effecting information recording in a spiral track or a plurality of circular tracks on a major surface of the disc.
  • disc 11 and the associated information recording and recovery system 16 may be of a type suitable for the aforementioned ablative recording methods so that playback of the recorded information may be effected immediately after the recording thereof without need for any intermediate processing steps.
  • a motor speed loop (type 2 servo) includes a motor driven tachometer 17 which supplies a 2,000 pulse per motor revolution signal (Ts) to a phase locked loop circuit (PLL) 19.
  • the output of the tachometer 17 is processed in the PLL 19 to produce an output signal having a variable frequency falling within a band of frequencies defined between 500 KHz and 2.5 MHz, and which output signal exhibits long-term stability about an examplary frequency of 1.26 MHz in the specific embodiment under consideration.
  • the output of the PLL 19 is applied to a divider circuit 21 so as to be counted down to the horizontal video sweep rate of 15,734.2 Hz.
  • the counted down PLL 19 output is, in turn, applied to a disc mounting error fine compensation circuit 23, to be subsequently described, which subjects the counted down PLL 19 output to a time delay varying responsively to the magnitude of a detected disc mounting error.
  • the output of the fine compensation circuit 23 and the output of an external source 25 of inverted reference horizontal signals (RH) are respectively applied to two inputs of a motor drive signal generator 27 which produces an output in accordance with the difference in frequency and phase between the two applied signals.
  • the output of the drive signal generator 27 is coupled to a compensation network 29, which provides the speed loop with the desired characteristics for the given type 2 servo.
  • the output of compensation network 29 is applied through an isolation amplfier 30, to power amplifiers 31 which supply, through a relay 33, an energization potential to the motor 15 to thereby close the speed loop.
  • the speed loop is satisfactory in maintaining the motor 15 at a desired operational speed, it is further desirable, when the turntable is rotating, to have a particular location on the turntable 13, and hence a corresponding particular location on the disc 11 carried thereon, rotating in phase with a frame synchronization signal (i.e., inverted reference frame signal RF) available from an external source 34 (e.g., means responsive to the equalizing pulses of the composite video signals during video recording, or a sync generator during playback).
  • a frame synchronization signal i.e., inverted reference frame signal RF
  • an external source 34 e.g., means responsive to the equalizing pulses of the composite video signals during video recording, or a sync generator during playback.
  • a position loop for controlling the turntable phase of rotation includes a phase tachometer (phase tach) 35 which provides an inverted train of pulses PT1 respectively representative of the procession of a particular turntable location past a stationary position.
  • the phase tach 35 may be a photoelectric detector which is responsive to brightness modulation produced by a marker, carried by the turntable, as it passes through a light path to the detector.
  • the output of the phase tach 35 is filtered and inverted in a network 36 and subsequently applied through another inverter to a play/record delay circuit 37 which provides a 3 horizontal line delay to the modified (i.e., filtered and twice inverted) phase tach output (PT3) during information recovery operations.
  • the play/record delay circuit 37 is responsive to the output of a user activated play/record command signal (REC) generator 39, which, illustratively may be a simple two position switch providing a low potential signal during record and a high potential signal during playback.
  • REC play/record command signal
  • the net effect of the delay imposed during information recovery is a 3 line advance in the particular turntable location relative to the RF signal (assuming that sync is established between the modified phase tach signal and the RF signal).
  • This advance provides compensation for an equal amount of delay to which the information recovered from the disc 11 is subjected to during processing in information recording and recovery system 16.
  • the output of the play/record delay circuit 37 is applied to a disc mounting error coarse compensation circuit 41 whereat it may be subjected to a time delay varying responsively with the magnitude of the detected disc mounting error.
  • the disc mounting fine and coarse compensation circuits 23, 41 may be instructive at this point to describe the operation of the respective disc mounting fine and coarse compensation circuits 23, 41.
  • a disc blank which is partially recorded, is mounted on the turntable 13 for further information recording, it is desirable, for the sake of playback continuity of the recorded information segments, to synchronize the previously recorded frames with the RF signal.
  • the disc blank 11 is to be positioned on the turntable 13 so that a pre-determined radial segment of the disc is aligned with a predetermined segment on the periphery of the turntable 11. Compensation for a disc mounting error, due to the relatively large mechanical tolerances inherent in the disc positioning process, is electronically provided for by means of the respective fine and coarse compensation circuits 23, 41.
  • the disc mounting error (i.e., the discrepancy between the RF signal and the previously recorded frames) is detected during playback of the previously recorded information on a suitable monitor.
  • Fine compensation circuit 23 subjects the counted down PLL 19 output to a time delay in increments of 1/80th of a horizontal line for a possible total delay of ⁇ 0.625 line (i.e., ⁇ 39.6 ⁇ sec).
  • Coarse compensation circuit 41 subjects the output of the play/record delay circuit 37 to a time delay in increments of a whole horizontal line for a possible total delay of ⁇ 5 lines (i.e., ⁇ 317 ⁇ sec).
  • the output of the coarse error compensation circuit 41 is applied to a turntable positioning circuit 43 including a detector for comparing that signal with the RF signal and an inverted reference vertical sync signal (RV) provided by an external source 44 (e.g., a sync separator operating on the composite video signal to be recorded or sync generator).
  • a turntable positioning circuit 43 including a detector for comparing that signal with the RF signal and an inverted reference vertical sync signal (RV) provided by an external source 44 (e.g., a sync separator operating on the composite video signal to be recorded or sync generator).
  • RV vertical sync signal
  • the output of the turntable positioning circuit 43 is in accordance with the difference in phase between the output of the coarse error compensation circuit 41 and the RF signal, and is utilized to incrementally modify the speed control loop by either driving the power amplifiers 31 through an electronic switch 45 or by inhibiting the power amplifiers 31 by means of another output applied through an inhibit logic circuit 47 which is further employed to prevent additional positioning of the turntable 13 once coincidence between the coarse compensation circuit 41 output (PT4) and the RF signal is established.
  • the position loop is completed through relay 33, motor 15 and turntable 13 back to the phase tach 35.
  • a bypass circuit 49 is employed to provide rapid motor acceleration to operational speed and is removed from the speed control loop, when the motor 15 reaches operational speed, responsively to one output of the drive signal generator 27.
  • Bypass circuit 49 applies a maximum driving potential to the amplifiers 31, through compensation network 29, and isolation amplifier 30, during motor start-up operations while also applying a command signal, to inhibit logic circuit 47 to disable the positioning loop from affecting motor start-up operations.
  • a command logic circuit 51 detects turntable rotational conditions (i.e., no motion and overspeed) responsively to the output of the phase tach 35. Upon detecting an overspeed condition or absence of a run condition (RUN) from a generator 53 (e.g., a switch), command logic circuit 51 produces an output which is applied to the inhibit logic circuit 47 to provide an inhibit condition for the power amplifiers 31 and which output is further utilized to energize the relay 33 to a position where a reverse voltage potential (e.g., -13.5 VDC) is coupled to the motor 15. To prevent reverse motor rotation, the energization of the relay 13 is ceased upon the detection of a no-motion condition of the turntable.
  • a reverse voltage potential e.g., -13.5 VDC
  • a bus circuit 55 responsive to outputs of command logic circuit 51, a lamp test signal generator 57 and inhibit logic circuit 47, provides driving voltages to various indicators and user systems external of the speed and position loops.
  • the output of the 2,000 line tachometer 17 is shown to be applied to an input terminal of an inverter 59 which forms part of the PLL 19.
  • the output of the inverter 59 is fed to an resistive-capacitive differentiator 61 to produce a series of sharply defined pulses still having the frequency and phase characteristics of the output of the 2,000 line tachometer 17.
  • the output of the differentiator 61 is, in turn, applied to both the left shift clock input terminal and, after a slight delay, to the mode control input terminal of a right/left shift register 63.
  • the right shift clock input terminal of register 63 also receives, via a feedback path, including counters of 21 65, 67 a counted down output of the PLL 19.
  • Register 63 operates as a frequency/phase detector and the output thereof is a positive DC voltage (approximately five volts) when the frequency of the 2,000 line tachometer 17 output is lower than the frequency of the counted down PLL 19 output.
  • the output of register 63 is a low voltage potential (approximately zero).
  • the output of the register 63 is a square wave having a duty cycle which varies dependently upon the relative phase of the two inputs and which output ultimately stabilizes at approximately 50 percent duty cycle.
  • the output of register 63 is applied, through a filtering stage 69 in series with a voltage follower 71, to an amplifier and compensation network 73 which provides the gain and loop phase characteristics required.
  • the output of network 73 is attenuated and level shifted to drive a voltage controlled multivibrator (VCM) 75 which provides the PLL 19 output.
  • VCM voltage controlled multivibrator
  • Divider circuit 21, including counters of 80 77, 79 receives the output of PLL 19 and counts it down to horizontal rate.
  • Bistable multivibrators 81, 83, in PLL 19 provide timing pulses and delay to reload counters 65, 67 while the PT3 signal provides timing pulses and delay to reload counters 77, 79.
  • the output of divider circuit 21 is applied to the trigger terminal of a flip-flop 85 to switch it to a set mode.
  • the output of flip-flop 85 switches a pair of serially coupled counters 87, 89, from a load mode to a count mode, wherein the PLL 19 output is counted from an initial setting preset by respective module mounted thumbwheel switches 91, 93, which may be selectively varied to compensate for the observed disc mounting error.
  • one output of counter 89 triggers a one-shot 95 whose output (TH) resets flip-flop 85; this output switches counters 87, 89 to the load mode and the respective count values of switches 91, 93 are reloaded into the counters to begin another count. Therefore, the output of one-shot 95 (TH) will correspond to the counted down PLL 19 output with a given time delay.
  • the output (TH) of the fine compensation circuit 23 is shown applied to one input terminal of a detector 97 included in the drive signal generator 27.
  • Detector 97 also receives as input the RH signal and produces an error signal which varies with the frequency and phase difference between the two inputs.
  • Detector 97 develops one output, at a terminal "a" thereof, having a duty cycle which varies in a nonlinear manner when the frequency of the TH signal is less than the frequency of the RH signal. This nonlinear variation causes the motor to fail to readily reach operational speed.
  • the output of the detector is a positive DC potential (greater than 2.5V) which output inhibits motor drive.
  • the output of the detector 97 is a signal having a duty cycle proportional to the phase difference between the two input signals which output exhibits long term stability at approximately 50% duty cycle.
  • the output of the detector 97 is coupled to compensation network 29 including a filter stage 99 and an isolation amplifier 101.
  • the output of amplifier 101 is applied through a first compensation stage 103 to a second isolation amplifier 105.
  • the gain of the output of second isolation amplifier 105 is increased in amplifier 107 and is thereafter applied to a second compensation stage 109 providing, along with the first compensation stage 103, an initial 6 db/octave gain slope which changes to 0 db/octave gain slope at approximately the same frequency as the mechanical corner frequency of the motor 15.
  • the output of the second compensation stage 109 is applied through a resistor 111 to the isolation amplifier 30 (not shown).
  • Bypass circuit 49 includes a flip-flop 115 whose output (N) is coupled, through a blocking diode 117, to the input of isolation amplifier 101.
  • the output of flip-flop 115 goes low, thereby effectively providing a dump path for the output of the detector 97 and therefore applying a maximum drive signal to the compensation network 29.
  • the low output of flip-flop 115 is applied to inhibit logic current 47 (see FIG. 5) to insure that electronic switch 45 is in a non-conducting stage and that no inhibiting of the amplifiers 31 may occur.
  • Flip-flop 115 is removed from the speed control loop, when the motor 15 is up to operational speed, by means of a varying duty cycle signal developed at terminal "b" of detector 97.
  • This signal sets the output of flip-flop 115 high, thereby applying a reverse bias across the blocking diode and effectively removing the input of isolation amplifier 101 from the output of the flip-flop 115.
  • Reset of flip-flop 115 is by means of a no-motion one-shot 119 which is controlled by the filtered and inverted output (PT2) of the phase tach.
  • the output of one-shot 119 remains high as long as the period of the input PT2 pulse is shorter than the width of the output pulse of the one-shot 119.
  • the output changes to a low to reset flip-flop 115.
  • the turntable positioning loop includes the play/record delay circuit 37, shown schematically in FIG. 4, which receives as input the PT3 signal. This input signal triggers a flip-flop 121 whose output is supplied to two signal paths. The first path being exclusively activated during information recovery operations to provide a 3 horizontal line delay to the PT3 signal. The second path, which provides no delay, being exclusively activated during information recording operations.
  • the first path comprises a counter 123 which is enabled by the output of flip-flop 121.
  • Counter 123 is incremented by the one-shot 95 output (TH) and provides the needed delay.
  • the output of counter 123 is applied to one input of a NAND gate 125 while the REC signal is applied to another input of the NAND gate 125.
  • the REC signal will be high, thereby enabling the gate 125, while during information record operations the REC signal will be low leading to a constant high output of the gate 125.
  • the second path comprises a first NAND gate 127, one input of which receives the output of flip-flop 121 while the other input receives the TH signal.
  • the output of the first gate 127 is applied to one input of a second NAND gate 129 whose other input is the inverted REC signal.
  • the inverted REC signal will be high enabling the second NAND gate 129, while during information recovery operations the inverted REC signal will be low leading to a constant high output for the second gate 129.
  • the outputs of the first and second signal paths are thereafter combined by being applied to respective input terminals of a negated-input OR gate 131 whose output triggers flip-flop 133.
  • the output of flip-flop 133 switches a counter 135, in the coarse compensation circuit 41, from a load mode to a count mode.
  • Counter 135, provides a time delay by counting the TH signal from an initial setting preset by a module thumbwheel switch 137 whose initial setting may be selectively varied to thereby compensate for an observed disc mounting error.
  • the output of counter 135 goes low triggering a one-shot 139 whose output (PT4) is utilized to reset flip-flop 121 and flip-flop 133.
  • the turntable positioning circuit 43 comprises a flip-flop 141 which is triggered to the set position by the RV signal.
  • a shaped RF signal from a flip-flop 143 is employed to reset flip-flop 141. Therefore the Q and Q outputs of the flip-flop 141 will vary at the turntable once around rate in synchronism with the RF signal.
  • the Q and Q outputs of flip-flop 141 are applied to respective terminals of a bistable multivibrator 145 also receiving the PT4 signal.
  • the Q and Q outputs of flip-flop 141 are utilized to determine the state of bistable multivibrator 145 when it is triggered by the PT4 signal.
  • the Q output of flip-flop 145 will be a high DC potential when the PT4 signal lags the RF signal and a low DC potential (approximately zero) when it leads the RF signal.
  • the Q output of flip-flop 145 is voltage converted and then applied, through an isolation stage, to drive the power amplifiers 31 through the electronic switch 45.
  • a flip-flop 147 triggered on by the shaped RF signal and reset by the PT4 signal, provides an output (T) which is applied to the inhibit logic circuit 47.
  • Electronic switch 45 comprises an FET 149 which is rendered conductive upon the application, to associated drive circuitry 151, of a signal (TM) generated by the inhibit logic circuit 47, to be subsequently discussed, which signal is characterized by having a low potential (approximately zero).
  • TM signal generated by the inhibit logic circuit 47
  • inhibit logic circuit 47 is shown to include a coincidence detector 153 which receives at respective input terminals thereof the shaped RF output (F2) of flip-flop 143 and the PT4 signal.
  • Detector 153 triggers only on coincidence of the shaped RF signal and the PT4 signal and when triggered, produces an output having a pulse width slightly longer than a frame interval. Therefore, when the position control loop finally settles, coincidence occurs on every revolution of the turntable 13 retriggering the detector 153 and holding its Q output high.
  • the Q output of the detector 153 is applied to one terminal of a first negated-input OR gate 155 whose output is applied to one terminal of a second negated-input OR gate 157, whose output is thus maintained high and therefore FET 149 is rendered non-conductive to prevent further positioning of the turntable 13.
  • the inverted output of gate 157 is applied to one input terminal of a NAND gate 159.
  • the other input terminal of the gate 159 receives the output (T) of flip-flop 147 from the turntable positioning circuit 43.
  • T the output of flip-flop 147
  • the Q output of detector 153 will be high, enabling first gate 155.
  • the other input to the first gate 155 is the high output of a divider of eight counter 161, enabled by the Q output DR of flip-flop 145 and is incremented by the Q output (shaped RF) of flip-flop 143.
  • divider of eight counter 161 is incremented by the RF signal and therefore the output of counter 161 will become periodically high (i.e., the output will alternate between a high for the duration of eight pulses and a low for the duration of the succeeding eight pulses).
  • NAND gate 159 will also be enabled in the absence of coincidence between the PT4 signal and the RF signal, and the output (T) of flip-flop 147 applied therethrough is utilized to induce an inhibit condition in the power amplifiers 31, when the PT4 signal leads the RF signal in a manner to be subsequently discussed.
  • Command logic circuit 51 includes a one-shot 163 triggered by the PT2 signal and the output of which is applied to one input terminal of a NAND gate 165.
  • the other input to the gate 165 being the inverted PT2 signal (PT3).
  • the one-shot 163 output pulse width is set so that both inputs to the gate 165 go high at approximately 33% overspeed leading to a low output for the gate 165.
  • This output applied to one input terminal of a negated-input OR gate 167, results in a high output for gate 167.
  • the inverted output of gate 167 is applied to trigger a flip-flop 169.
  • Flip-flop 169 may also be triggered by a stopping command (RUN signal high) applied via an inverter to the other input terminal of gate 167.
  • the Q output of flip-flop 169 is applied to one input terminal of NAND gate 171 which also receives at another input terminal thereof the output of gate 167.
  • NAND gate 171 which also receives at another input terminal thereof the output of gate 167.
  • the Q output of the flip-flop 169 goes low thereby providing a high output for gate 171 which holds an external NO MOTION bus high.
  • the inverted Q output (SR) of flip-flop 169 is applied to relay 33 to control the energization thereof.
  • SR high, the relay will be energized to a state where the motor input terminals are coupled to source of reverse potential to power down the motor.
  • Reset of flip-flops 169 and 115, to prevent reverse motor rotation is by means of the one-shot 119 (no motion sensor) output X (in bypass circuit 49) changing from a high to a low.
  • flip-flop 115 When flip-flop 115 is reset its Q output goes low and it results in a resetting of detector 153.
  • Detector 153 is held in a reset state until the motor 15 is again up to speed.
  • Resetting flip-flop 169 returns the relay 33 to its de-energized state.
  • the output of gate 171 is high so that a low output of gate 159 applied through gate 173, inhibits the power amplifiers 31 (this occurs when PT4 signal is leading the RF signal).
  • Bus circuit 55 includes a one-shot 177 which is triggered by the Q output of coincidence detector 153.
  • the width of the output pulse of one-shot 177 is greater than the width of two video frames, and that output is applied to one input terminal of a NAND gate 179.
  • the other input terminal of gate 179 receives the delayed Q output of coincidence detector 153 and the output of gate 179 produces a DISC LOCKED bus.
  • An inverted-input OR gate 181 receives the output of gate 179 and the Q output (X) of one-shot 119 (from bypass circuit 49) at respective input terminals thereof.
  • the inverted output of gate 181 is applied to one input terminal of a NOR gate 183 whose output drives a DISC LOCK LAMP bus coupled to an indicator lamp (not shown).
  • the other input to NOR gate 183 being the lamp test signal from generator 57.
  • the inverted Q output of the flip-flop 169 is applied to a STOPPING bus terminal (which may be utilized, for example, in a safety latch logic circuit).
  • the output of NAND gate 171 (in command logic circuit 51) is applied through a blocking diode to a NO MOTION bus.

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US05/777,478 1976-03-19 1977-03-14 Turntable rotational speed and phase control system for a video disc play/record apparatus Expired - Lifetime US4123779A (en)

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GB11105/76 1976-03-19
GB11105/76A GB1572346A (en) 1976-03-19 1976-03-19 Velocity and phase control for a disc recording and reproducing apparatus

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JP (1) JPS52126201A (nl)
AU (1) AU510555B2 (nl)
DE (1) DE2711920C2 (nl)
FR (1) FR2344909A1 (nl)
GB (1) GB1572346A (nl)
NL (1) NL7703003A (nl)

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US4622499A (en) * 1985-02-27 1986-11-11 Miniscribe Corporation Method and apparatus for controlling a motor
EP0220466A1 (en) * 1985-09-27 1987-05-06 Fuji Photo Film Co., Ltd. Apparatus for recording video signals on rotary recording medium with appropriate angular phase in rapid response to start of rotation
USRE32431E (en) * 1978-11-16 1987-06-02 Discovision Associates System for rotating an information storage disc at a variable angular velocity to recover information therefrom at a prescribed constant rate
US4706005A (en) * 1985-04-09 1987-11-10 Citizen Watch Co., Ltd. Control circuit of direct current servomotor for floppy disk drive
US4763205A (en) * 1984-08-21 1988-08-09 Pioneer Electronic Corporation Method of time axis control in an information recording system for compensation of tracking error caused by track jumping
US4816937A (en) * 1985-10-17 1989-03-28 Canon Kabushiki Kaisha Recording and/or reproduction apparatus capable of retaining start up information
US4819221A (en) * 1987-04-08 1989-04-04 U.S. Philips Corporation Apparatus for reading record carriers having substantially concentric or spiral tracks
US4914725A (en) * 1989-07-10 1990-04-03 International Business Machines Corporation Transducer positioning servo mechanisms employing digital and analog circuits
US5055950A (en) * 1988-08-24 1991-10-08 Nikon Corporation Floppy disk driver with protective rotation control apparatus
US5469425A (en) * 1991-07-04 1995-11-21 Matsushita Electric Industrial Co. Method of manufacturing an index apparatus
US5557184A (en) * 1992-10-01 1996-09-17 Samsung Electronics Co., Ltd. Spindle motor controlling circuit of an optical disk system
US6477116B1 (en) 1997-09-30 2002-11-05 Seiko Epson Corporation Rotation controller and rotation control method
US8918236B2 (en) 2011-06-24 2014-12-23 Honeywell International Inc. Methods and systems for adjusting attitude using reaction wheels
WO2020001900A1 (fr) * 2018-06-28 2020-01-02 Valeo Equipements Electriques Moteur Système de commande d'un interrupteur et bras de commutation

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JPS57162110A (en) * 1981-03-26 1982-10-05 Sony Corp Disk reproducing device
JPS57162890A (en) * 1981-03-31 1982-10-06 Teac Co Information signal recorder
JPS5883365A (ja) * 1981-11-10 1983-05-19 Sony Corp デイスク・プレ−ヤ
JPS6116075A (ja) * 1984-07-02 1986-01-24 Fuji Photo Film Co Ltd 回転磁気記録体トラツキング装置
JPS6486327A (en) * 1988-08-19 1989-03-31 Teac Corp Information signal recorder
KR920003426B1 (ko) * 1989-10-13 1992-04-30 삼성전자 주식회사 스핀들 모터의 과회전 방지장치
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US4318144A (en) * 1977-03-04 1982-03-02 Ing. C. Olivetti & C., S.P.A. Flexible magnetic disk recording apparatus
US4223359A (en) * 1977-03-04 1980-09-16 Ing. C. Olivetti & C., S.P.A. Flexible magnetic disk recording apparatus
US4199149A (en) * 1977-04-28 1980-04-22 Sony Corporation Record player
US4439848A (en) * 1978-03-27 1984-03-27 Discovision Associates Focusing system for video disc player
EP0035803A2 (en) * 1978-03-27 1981-09-16 Discovision Associates Disc spindle servo system
EP0035803A3 (en) * 1978-03-27 1982-02-24 Discovision Associates Disc spindle servo system
US4358796A (en) * 1978-03-27 1982-11-09 Discovision Associates Spindle servo system for videodisc player
US4236050A (en) * 1978-06-30 1980-11-25 Mca Discovision, Inc. System for recovering information from a movable information storage medium having a pilot signal with an aligned phase angle in adjacent tracks
US4228326A (en) * 1978-11-16 1980-10-14 Mca Discovision Inc. System for recording information on a rotatable storage disc, in a substantially uniform recording density
USRE32431E (en) * 1978-11-16 1987-06-02 Discovision Associates System for rotating an information storage disc at a variable angular velocity to recover information therefrom at a prescribed constant rate
US4223349A (en) * 1978-11-16 1980-09-16 Mca Discovision, Inc. System for rotating an information storage disc at a variable angular velocity to recover information therefrom at a prescribed constant rate
US4416006A (en) * 1979-07-21 1983-11-15 Masatsugu Kitamura Record disc playing apparatus having the function for correcting rotational irregularities due to record disc eccentricity
US4296446A (en) * 1979-11-15 1981-10-20 Rca Corporation Motor speed control circuit
US4445143A (en) * 1980-05-10 1984-04-24 Victor Company Of Japan, Ltd. Means for compatibly reproducing video discs recorded according to different broadcast standards
USRE32194E (en) * 1980-05-10 1986-06-24 Victor Company Of Japan, Ltd. Means for compatibly reproducing video discs recorded according to different broadcast standards
US4513406A (en) * 1981-05-01 1985-04-23 Tokyo Shibaura Denki Kabushiki Kaisha Positioning servo circuit for a disk system
US4409626A (en) * 1981-10-06 1983-10-11 Rca Corporation Video disc player having vertical timing signal generator
US4613799A (en) * 1982-03-18 1986-09-23 Sanyo Electric Co., Ltd. Motor velocity control circuit
US4600867A (en) * 1983-11-01 1986-07-15 Nippon Soken, Inc. Motor speed controlling device
US4763205A (en) * 1984-08-21 1988-08-09 Pioneer Electronic Corporation Method of time axis control in an information recording system for compensation of tracking error caused by track jumping
EP0193125A1 (en) * 1985-02-21 1986-09-03 Fuji Photo Film Co., Ltd. Synchronization control system in video signal reproducing device
US4622499A (en) * 1985-02-27 1986-11-11 Miniscribe Corporation Method and apparatus for controlling a motor
US4706005A (en) * 1985-04-09 1987-11-10 Citizen Watch Co., Ltd. Control circuit of direct current servomotor for floppy disk drive
EP0220466A1 (en) * 1985-09-27 1987-05-06 Fuji Photo Film Co., Ltd. Apparatus for recording video signals on rotary recording medium with appropriate angular phase in rapid response to start of rotation
US5087994A (en) * 1985-10-17 1992-02-11 Canon Kabushiki Kaisha Recording and/or reproduction apparatus capable of retaining start up information
US4816937A (en) * 1985-10-17 1989-03-28 Canon Kabushiki Kaisha Recording and/or reproduction apparatus capable of retaining start up information
US4819221A (en) * 1987-04-08 1989-04-04 U.S. Philips Corporation Apparatus for reading record carriers having substantially concentric or spiral tracks
US5055950A (en) * 1988-08-24 1991-10-08 Nikon Corporation Floppy disk driver with protective rotation control apparatus
US4914725A (en) * 1989-07-10 1990-04-03 International Business Machines Corporation Transducer positioning servo mechanisms employing digital and analog circuits
US5469425A (en) * 1991-07-04 1995-11-21 Matsushita Electric Industrial Co. Method of manufacturing an index apparatus
US5557184A (en) * 1992-10-01 1996-09-17 Samsung Electronics Co., Ltd. Spindle motor controlling circuit of an optical disk system
US6477116B1 (en) 1997-09-30 2002-11-05 Seiko Epson Corporation Rotation controller and rotation control method
US8918236B2 (en) 2011-06-24 2014-12-23 Honeywell International Inc. Methods and systems for adjusting attitude using reaction wheels
WO2020001900A1 (fr) * 2018-06-28 2020-01-02 Valeo Equipements Electriques Moteur Système de commande d'un interrupteur et bras de commutation
FR3083397A1 (fr) * 2018-06-28 2020-01-03 Valeo Equipements Electriques Moteur Systeme de commande d'un interrupteur et bras de commutation
US11502635B2 (en) 2018-06-28 2022-11-15 Valeo Equipements Electriques Moteur System for controlling a switch and switching arm

Also Published As

Publication number Publication date
AU2338577A (en) 1978-09-21
NL7703003A (nl) 1977-09-21
DE2711920C2 (de) 1982-10-21
DE2711920A1 (de) 1977-10-06
FR2344909A1 (fr) 1977-10-14
AU510555B2 (en) 1980-07-03
FR2344909B1 (nl) 1982-11-12
JPS52126201A (en) 1977-10-22
GB1572346A (en) 1980-07-30

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