US3916430A - System for eliminating substrate bias effect in field effect transistor circuits - Google Patents

System for eliminating substrate bias effect in field effect transistor circuits Download PDF

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Publication number
US3916430A
US3916430A US341058A US34105873A US3916430A US 3916430 A US3916430 A US 3916430A US 341058 A US341058 A US 341058A US 34105873 A US34105873 A US 34105873A US 3916430 A US3916430 A US 3916430A
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conductivity type
source
transistor
substrate
transistors
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US341058A
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Robert Charles Heuner
David Keith Morgan
Goetz Wolfgang Steudel
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RCA Corp
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RCA Corp
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Priority to US341058A priority Critical patent/US3916430A/en
Priority to CA194,217A priority patent/CA1010577A/en
Priority to GB1023274A priority patent/GB1452160A/en
Priority to DE2411839A priority patent/DE2411839C3/de
Priority to FR7408466A priority patent/FR2221818B1/fr
Priority to JP2958474A priority patent/JPS563676B2/ja
Priority to BE141983A priority patent/BE812270A/xx
Application granted granted Critical
Publication of US3916430A publication Critical patent/US3916430A/en
Priority to HK703/79A priority patent/HK70379A/xx
Priority to MY140/80A priority patent/MY8000140A/xx
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H10D89/213—Design considerations for internal polarisation in field-effect devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/038—Diffusions-staged

Definitions

  • ABSTRACT An integrated circuit, formed on a common substrate, having one portion operated from a first source of operating potential and another portion operated from a second source of operating potential. Separate wells are diffused in said substrate for the connection thereto of the different voltages and a reference potential common to the two sources of operating potential is applied to the commonsubstrate. Transistors having a given potential applied to their source electrodes are formed in the common substrate or in a well having the same given potential connected thereto for eliminating potential differences between the source and the substrate of the transistors.
  • FIG. 1 shows a typical integrated complementary metal oxide semiconductor (CMOS) circuit.
  • CMOS complementary metal oxide semiconductor
  • FIG. 1 the output of a first logic circuit 120 operated from a 3 volt power supply is coupled to a second logic circuit 140 operated from a voltpower supply by means of a circuit comprised of inverters 11, 12 and 13.
  • the operating potential for interter I1 is the same 3 volt source as for circuit 120.
  • Inverter I1 inverts the output from circuit 120 and applies it to the input of in verter I2 (gate of transistor N2).
  • the operating potential for inverters I2 and I3 is the same 15 volt source as for circuit 140.
  • Inverters 12 and 13 are cross-coupled and supply a signal varying between ground and 15 volts to circuit 140 in response to the complementary 3 volt level signals applied to their inputs (gates of transistors N2 and N3).
  • FIG. 1 shows schematically that all the P-type transistors (P1, P2 and P3) share the same substrate, 150, to which is applied the highest system potential (15 volts) and that the substrates of all the N-type transistors (N1, N2 and N3) are returned to the lowest system potential (ground). Note, however, that the sources of the transistors may be operated at different potentials than their substrate region. Specifically, transistor P1 has its source connected to 3 volts while its substrate is at 15 volts.
  • the threshold voltage (V of a field effect transistors is defined as the gate to source potential which must be exceeded to turn the transistor on.
  • the V is dependent on the potential applied between the source and the substrate of the transistor.
  • a reverse bias applied between the source and the substrate increases the V of the transis- -,tor.
  • the V may increase above its nominal value at zero source to substrate bias by an amount varying from 0.2 volts per volt of reverse bias to 1 volt per volt of reverse bias.
  • the V of transistor P1 may be, for example 2 volts when the source and the substrate are connected in common (i.e. zero reverse bias). However, with a reverse bias of 12.0 volts applied between the source and the substrate, as in FIG. 1, the V increases to a value which may range from 4 volts to more than 10 volts. Clearly, if the V of transistor P1 is 4 volts the gate to source potential necessary to turn it on must be equal to or greater than 4 volts. However, transistor P1 is part of a circuit operated from the 3 volt power supply. Also, the signals applied to the gate of transistor P1 are derived from circuits operated from the 3 volt power supply and will also vary from zero volts to a maximum of 3 volts. Accordingly, transistor P1 cannot be turned on and the circuit is thereby rendered partly or wholly inoperative.
  • Circuits embodying the invention are formed on a common substrate and a different well region is provided for each different operating potential applied to the circuit.
  • Transistors having their source electrodes connected to a given potential are formed in a well or in the common substrate having the same given potential applied thereto. Circuits can thereby be formed in which all the active components have zero reverse bias between their source and substrate.
  • FIG. 1 is a schematic diagram of a prior art circuit
  • FIG. 2 is a schematic diagram of a circuit embodying the invention.
  • FIG. 3 is a cross section of a portion of the circuit of FIG. 2.
  • circuit 12 is connected across a first power supply of V1 volts and produces output signals at terminal 19 which vary between Vl volts and V volts.
  • Circuit 12 may be any one of a number of known logic or analog circuits whose output signals are to be coupled to another circuit 14 which may also be a logic or analog circuit or a display device or any other type of load device.
  • Circuit 14 is connected across a second power supply of V2 volts and requires input signals of an amplitude varying betweenV volts and V2 volts.
  • V volts is ground potential
  • V1 volts is l.5 volts
  • V2 volts is -20 volts.
  • the output of circuit 12 is level shifted by means of inverters 10, 20 and 30 for producing signals suitable to drive circuit 14.
  • Each inverter includes a P-type transistor and an N-type transistor denoted by a P and an N, respectively, with a numerical subscript corresponding to its associated inverter.
  • the gates of transistors P10 and N10 are connected to terminal 19 to which the output of circuit 12 is applied.
  • the substrate and the source of transistor P10 are connected to a terminal 13 to which is applied a potential of +V volts.
  • the drain of transistor P10 is connected to the drain of transistor N10 at terminal 14.
  • the source and substrate, 67, of transistor N10 are connected to a terminal 15 to which is applied a potential of V1 volts.
  • the sources and the substrate, 60, of transistors P20 and P30 are connected to terminal 13.
  • the gates of transistors P20 and P30 are connected to terminals 14 and 19, respectively.
  • the drains of transistors P20 and N20 are connected to the gate of the transistor N30 at output terminal 16 and the drains of transistors P30 and N30 are connected to the gate of transistor N20 at output terminal 18.
  • the sources and the substrate, 70, of transistors N20 and N30 are connected to terminal 17 to which is applied a potential of V2 volts.
  • Output terminal 18 is connected to circuit 14. Obviously output 16 could, similarly to terminal 18, be used to drive an output circuit.
  • the circuit of FIG. 2 may be formed as shown, in
  • the common substrate, 60 is a body of semiconductor of N-conductivity type material in which are diffused regions (61, 62, 63, 64, 67 and 70) of P-conductivity type.
  • P-regions 61 and 62 form the source and drain regions of P-conductivity type transistor
  • P and P-regions 63 and 64 form the source and drain regions of P-conductivity type transistor P20.
  • the N-conductivity type transistors are formed in P-regions 67 and 70, denoted P-well No. 1 and No. 2, respectively.
  • N-regions 65 and 66 diffused in P-region 67 form the source and drain regions of transistor N10, and N regions 68 and 69 form the source and drain regions of transistor N20.
  • Transistor N30 (not shown in FIG. 3) would preferably have its source and drain formed in the same P-well as transistor N20.
  • insulator layer such as silicon dioxide over which is formed a gate electrode.
  • the potential applied to the gate electrode controls the conductivity of the channel region.
  • the gate region of transistor N10 is shown connected to the gate of transistor P10; the two gates being connected in common to terminal 19.
  • Region 65 defined as the source of transistor N10 is connected to P-region 67 (which is the local substrate of transistor N10) and to the source of potential V1.
  • the drain 61 of transistor P10 is connected to the drain 66 of transistor N10 and to the gate of transistor P at terminal 14.
  • the source 68 of transistor N20 is connected to P-region 70 (which is the local substrate of transistor N20) to the potential V2.
  • the gate electrode of transistor N20 is connected to terminal 18.
  • Drain region 69 of transistor N20 is connected to drain region 63 of transistor P20 at terminal 16.
  • the source regions 62 and 64 of transistors P10 and P20 are connected to the semiconductor body 60 (which is the local substrate of these transistors) to the potential V As indicated in FIGS.
  • all the P-type transistors (P10, P20, P) have their sources and their common substrate 60 connected to -a common point of potential (V Transistor N10 has its source and its local substrate, P-well region 67, connected to a potential (V1) and transistors N20 and N30 have their sources and their local substrate, P-well region 70, connected to a potential V2.
  • V Transistor N10 has its source and its local substrate, P-well region 67, connected to a potential (V1)
  • transistors N20 and N30 have their sources and their local substrate, P-well region 70, connected to a potential V2.
  • each transistor has its source connected to the same potential as its well or substrate.
  • Operating the transistors with zero volts between their sources and substrates ensures that the threshold voltage of the devices is not increased above its nominal value at zero reverse bias. This permits the design of circuits and their reliable operation at values of operating potential which are nearly equal to the value of the threshold voltage.
  • a device with a V of 1 volt can be operated from a 1.3 volt or 1.5 volt supply. It also permits the design of interface circuits between circuits operating at widely different potentials. This technique is also extremely valuable for use in conjunction with circuits operating at extremely low voltages (e.g. 1.5 volts) where a small increase in V may render the circuit inoperable or marginally operable.
  • each transistor in circuits embodying the invention, has its source connected to the same potential as its substrate. Also in contrast to the prior art, the common substrate is maintained at a fixed potential and the well-regions are designed to receive the different voltage levels applied to the circuit.
  • the sources of the transistors are at the same potential as their substrate and regions at different potentials are isolated from each other. As a result, there cannot be a condition of forward bias between a source region and a substrate. Accordingly, the possible destruct condition present in the prior art is eliminated.
  • a signal of zero volts applied to terminal 19 turns off transistor P30 while causing transistor N10 to conduct thereby clamping terminal 14 to l .5 volts. Under this condition, 1 .5 volts is applied to the gate of transistor P20 while zero volts is applied to the gate of transistor P30. Transistor P20, with 1.5 volts between its gate and source, conducts causing terminal 16 to rise in potential towards zero volts. The rising potential at terminal 16 turns on transistor N30 which clamps terminals 18 to 20 volts. Thus, the zero volt level signal present at terminal 19 results in the production of a zero volt level signal at terminal 16 and a signal level of 20 volts at terminal 18.
  • transistor P10 In response to the presence of a l .5 volt level signal at terminal 19, transistor P10 is turned on and transistor N10 is turned off. In the circuit of FIG. 2 the V, of P10 remains at its low value of 1.0 volts since the source and the substrate are tied in common to 0 volts. Therefore, when l.5 volts is applied to its gate, transistor P10 is turned fully on. With transistor P10 turned on, zero volts is applied to terminal 14 which cuts off transistor P20. Concurrently, the l.5 volts applied to input terminal 19 turns on transistor P30. Transistor P30 when turned on applies zero volts to terminal 18 which turns on transistor N20 which clamps terminal 16 to 20 volts. With output terminal 16 clamped to 20 volts, transistor N30 is cut off. Therefore, terminal 16 is at -20 volts while terminal 18 is at zero volts in response to the l.5 volt level at terminal 19.
  • The; signals at terminals 16 and 18 are thus volts and 0 volts, respectively, when-the signal at terminal 19 is -l.5 volts and the signals at terminals 16 and 18 are zero volts and 20 volts, respectively, when the signal at terminal 19 is 0 volts.
  • a low level input signal may be level shifted to produce a much larger output signal with little power dissipation and with a minimum number of components.
  • the low power dissipation results both from the type of circuit (complementary symmetry) and from the fact that the input signals may be low level signals obtained from a low power circuit.
  • a field effect integrated circuit which in response to signals varying between a first voltage level and a reference potential produces signals varying between said reference potential and a second voltage level comprisa semiconductor body of first conductivity type having embedded therein regions of second conductivity type for-formingthe'sources and the-drains of transistors of second conductivity type and at least two well-regions of said second conductivity type also embedded within said semiconductor body with regions of first conductivity type embedded within said well-regions for forming the sources and the drains of transistors of first conductivity W means for applying said reference potential to said substrate;
  • transistors are insulated-gate field-effect transistors; wherein said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity; and
  • said second voltage level is of same polarity as but of greater magnitude than said first voltage level.
  • the combination as claimed in claim 1 including means connecting the drain region of one transistor of first conductivity type from said one well region to the drain region of one transistor of said second conductivity type for forming a first complementary inverter, and means connecting the drain region of one transistor of first conductivity type from said second well region to the drain region of one transistor of said second conductivity type for forming a second complementary inverter, means for applying to said first complementary inverter signals varying between said first voltage level and said reference potential for producing output signals applied to said second inverter, said output signals varying between said firstvoltage level and said reference potential and said second complementary inverter producing in response to the output signals of said first complementary inverter signals varying between said second voltage level and said reference potential.
  • a complementary field-effect integrated circuit having various portions operated at different operating potentials relative to a reference potential, with at least two of the portions operated at said different potentials being coupled to each other comprising:
  • a semiconductor body of first conductivity type having embedded therein regions of second conductivity type for forming the sources and the drains of transistors of second conductivity type with a control electrode formed over the region between the source and drain of each transistor, said semiconductor body being the substrate of the transistors formed therein; g at least one well region per each said different operating potential, each one of said well regions being of second conductivity type and being embedded within said semiconductor body with regions of first conductivity type embedded within said well regions for forming the sources and the drains of transistors of first conductivity type, said well regions being the substrates of the transistors formed therein; means for applying each said different operating potential to a different one of the well regions, and the reference potential to the semiconductor body;
  • means coupling one portion of the circuit operated at one potential to another portion operated at a different potential including means coupling said one portion to the control electrodes of the transistors in said another portion formed in said semiconductor body which serves as the point of reference potential.
  • An integrated field effect transistor circuit for translating signals produced by a first circuit operated from a first source of operating potential to a second circuit operated from a second source of different operating potential, comprising:
  • each inverter comprising a first transistor of first conductivity type and a second transistor of second conductivity type; each transistor having a substrate and source and drain region defining the ends of a conduction path within its substrate and a control electrode for varying the conductivity of its conduction path, said transistors of first conductivity type sharing the same substrate region; said transistors of said second conductivity type having different substrate regions, electrically isolated from each other; means connecting the gate electrodes of the two transistors of said first inverter in common to said first circuit; means connecting the source and substrate of said first transistor of said first inverter to a first node; means connecting the source and substrate of said second transistor of said first inverter to a second node; and means connecting the drains of the two transistors in common at a first output point; means connecting said first source of operating potential across said first and second nodes; means connecting the gate electrode of at least one of said two transistors of said second inverter to said first output point; means connecting the source and substrate of said first transistor of said second in
  • a substrate of one conductivity type having therein source and drain regions of opposite conductivity type forming transistors of said opposite conductivity type, said source regions being connected to said substrate; at least two semiconductor wells in said substrate second voltage level.

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  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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US341058A 1973-03-14 1973-03-14 System for eliminating substrate bias effect in field effect transistor circuits Expired - Lifetime US3916430A (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
US341058A US3916430A (en) 1973-03-14 1973-03-14 System for eliminating substrate bias effect in field effect transistor circuits
CA194,217A CA1010577A (en) 1973-03-14 1974-03-06 System for eliminating substrate bias effect in field effect transistor circuits
GB1023274A GB1452160A (en) 1973-03-14 1974-03-07 System for eliminating substrate bias effect in field effect transistor circuits
DE2411839A DE2411839C3 (de) 1973-03-14 1974-03-12 Integrierte Feldeffekttransistor-Schaltung
FR7408466A FR2221818B1 (enrdf_load_stackoverflow) 1973-03-14 1974-03-13
JP2958474A JPS563676B2 (enrdf_load_stackoverflow) 1973-03-14 1974-03-13
BE141983A BE812270A (fr) 1973-03-14 1974-03-13 Perfectionnements aux circuits integres
HK703/79A HK70379A (en) 1973-03-14 1979-10-04 System for eliminating substrate bias effect in field effect transistor circuits
MY140/80A MY8000140A (en) 1973-03-14 1980-12-30 System for eliminating substrate bias effect in field effect transistor circuits

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US341058A US3916430A (en) 1973-03-14 1973-03-14 System for eliminating substrate bias effect in field effect transistor circuits

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US (1) US3916430A (enrdf_load_stackoverflow)
JP (1) JPS563676B2 (enrdf_load_stackoverflow)
BE (1) BE812270A (enrdf_load_stackoverflow)
CA (1) CA1010577A (enrdf_load_stackoverflow)
DE (1) DE2411839C3 (enrdf_load_stackoverflow)
FR (1) FR2221818B1 (enrdf_load_stackoverflow)
GB (1) GB1452160A (enrdf_load_stackoverflow)
HK (1) HK70379A (enrdf_load_stackoverflow)
MY (1) MY8000140A (enrdf_load_stackoverflow)

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Also Published As

Publication number Publication date
DE2411839C3 (de) 1979-01-18
BE812270A (fr) 1974-07-01
FR2221818A1 (enrdf_load_stackoverflow) 1974-10-11
CA1010577A (en) 1977-05-17
HK70379A (en) 1979-10-12
FR2221818B1 (enrdf_load_stackoverflow) 1977-09-30
GB1452160A (en) 1976-10-13
JPS563676B2 (enrdf_load_stackoverflow) 1981-01-26
JPS49128684A (enrdf_load_stackoverflow) 1974-12-10
DE2411839A1 (de) 1974-09-26
DE2411839B2 (de) 1978-05-18
MY8000140A (en) 1980-12-31

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