US20220199656A1 - Display substrate, manufacturing method thereof and display device - Google Patents

Display substrate, manufacturing method thereof and display device Download PDF

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Publication number
US20220199656A1
US20220199656A1 US17/280,797 US202017280797A US2022199656A1 US 20220199656 A1 US20220199656 A1 US 20220199656A1 US 202017280797 A US202017280797 A US 202017280797A US 2022199656 A1 US2022199656 A1 US 2022199656A1
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Prior art keywords
electrode
coupled
subpixel
transistor
base substrate
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US17/280,797
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English (en)
Inventor
Mengqi WANG
Siyu Wang
Huijun Li
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Assigned to BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment BOE TECHNOLOGY GROUP CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LI, HUIJUN, WANG, MENGQI, WANG, Siyu
Publication of US20220199656A1 publication Critical patent/US20220199656A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • H01L27/3246—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof and a display device.
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • An object of the present disclosure is to provide a display substrate, a manufacturing method thereof and a display device, so as to ensure the brightness uniformity of the subpixels of the display panel.
  • the present disclosure provides in some embodiments a display substrate, including a base substrate and a plurality of subpixels arranged in an array form on the base substrate.
  • the plurality of subpixels is arranged in rows, and each row of subpixels includes N subpixels arranged in sequence along a first direction, where N is a positive integer.
  • Each subpixel includes a subpixel driving circuitry
  • the subpixel driving circuitry includes a driving transistor and a first transistor
  • a first electrode of the first transistor is coupled to a second electrode of the driving transistor
  • a second electrode of the first transistor is coupled to a gate electrode of the driving transistor
  • an active layer of the first transistor includes a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to the first semiconductor portion and the second semiconductor portion.
  • Each of first to (N ⁇ 1) th subpixels in the first direction further includes a voltage stabilizing electrode.
  • Each row of subpixels includes a plurality of first subpixels, the first subpixels of N th subpixels in the first direction are target subpixels, the target subpixel is arranged closest to a first boundary of the display substrate in the row of subpixels, and an orthogonal projection of the conductor portion of the first transistor of the target subpixel onto the base substrate overlaps an orthogonal projection of the voltage stabilizing electrode of the (N ⁇ 1) th subpixel in the row onto the base substrate.
  • each subpixel further includes a power source signal line, at least a part of the power source signal line extends in a second direction, and the voltage stabilizing electrode is coupled to the power source signal line.
  • the voltage stabilizing electrode includes a first portion and a second portion coupled to each other, an orthogonal projection of the first portion onto the base substrate overlaps an orthogonal projection of the power source signal line onto the base substrate at an overlapping region where the first portion is coupled to the power source signal line, at least a part of the second portion extends along the first direction to a next subpixel in the first direction, and an orthogonal projection of the conductor portion onto the base substrate overlaps an orthogonal projection of a second portion of a previous subpixel of the subpixel to which the conductor portion belongs in the first direction onto the substrate.
  • each subpixel further includes a data line, at least a part of the data line extends in a second direction intersecting the first direction
  • the subpixel driving circuitry further includes a first conductive connection member, the first conductive connection member extends along the second direction, an orthogonal projection of the second electrode of the first transistor onto the base substrate overlaps an orthogonal projection of a first end of the first conductive connection member onto the base substrate at a first overlapping region
  • the second electrode of the first transistor is coupled to the first end of the first conductive connection member at the first overlapping region
  • a second end of the first conductive connection member is coupled to the gate electrode of the driving transistor
  • the orthogonal projection of the first portion onto the base substrate is located between an orthogonal projection of the first overlapping region onto the base substrate and an orthogonal projection of the data line onto the base substrate.
  • each subpixel further includes a data line, and at least a part of the data line extends in a second direction intersecting the first direction.
  • the subpixel driving circuitry further includes a data write-in transistor, a gate electrode of which is coupled to the gate line, a first electrode of which is coupled to the data line, and a second electrode of which is coupled to the first electrode of the driving transistor.
  • the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the first electrode of the data write-in transistor onto the base substrate, and the orthogonal projection of the second portion onto the base substrate overlaps an orthogonal projection of the data line onto the base substrate.
  • the orthogonal projection of the data line onto the base substrate is located between an orthogonal projection of a channel portion of the data write-in transistor onto the base substrate and the orthogonal projection of the conductor portion of the first transistor of a next subpixel onto the base substrate.
  • each subpixel further includes a data line, and at least a part of the data line extends in a second direction intersecting the first direction.
  • the subpixel driving circuitry further includes: a second conductive connection member, at least a part of the second conductive connection member extending along the second direction; a second transistor, a gate electrode of which is coupled to a resetting signal line, a first electrode of which is coupled to an initialization signal line, and a second electrode of which is coupled to the second electrode of the first transistor; and a seventh transistor, a gate electrode of which is coupled to a resetting signal line of a next subpixel in the second direction, and a first electrode of which is coupled to an initialization signal line of the next subpixel in the second direction, and a second electrode of which is coupled to an anode of a corresponding light-emitting element.
  • An orthogonal projection of a channel portion of the second transistor onto the base substrate is located between the orthogonal projection of the data line onto the base substrate and an orthogonal projection of the second conductive connection member onto the base substrate, and an orthogonal projection of a channel portion of the seventh transistor onto the base substrate is located between the orthogonal projection of the second conductive connection member coupled to the seventh transistor onto the base substrate and an orthogonal projection of the data line of a previous subpixel of the subpixel to which the seventh transistor belongs in the first direction onto the base substrate.
  • each subpixel further includes a data line, and at least a part of the data line extends in a second direction intersecting the first direction.
  • the subpixel driving circuitry further includes: a fifth transistor, a gate electrode of which is coupled to a light-emission control signal line, a first electrode of which is coupled to the power source signal line, and a second electrode of which is coupled to the first electrode of the driving transistor; and a sixth transistor, a gate electrode of which is coupled to the light-emission control signal line, a first electrode of which is coupled to the second electrode of the driving transistor, and a second electrode of which is coupled to an anode of a light-emitting element.
  • An orthogonal projection of a channel portion of the fifth transistor onto the base substrate is located between the orthogonal projection of the data line onto the base substrate and an orthogonal projection of the power source signal line onto the base substrate
  • an orthogonal projection of a channel portion of the sixth transistor onto the base substrate is located between the orthogonal projection of the second conductive connection member coupled to the sixth transistor onto the base substrate and an orthogonal projection of the data line of a previous subpixel of the subpixel to which the sixth transistor belongs in the first direction onto the base substrate.
  • each subpixel further includes a data line, at least a part of the data line extends in a second direction intersecting the first direction, an orthogonal projection of the first electrode of the driving transistor onto the base substrate is located between an orthogonal projection of the gate electrode of the driving transistor onto the base substrate and the orthogonal projection of the data line onto the base substrate, and an orthogonal projection of the second electrode of the driving transistor onto the base substrate is located between the orthogonal projection of the gate electrode of the driving transistor onto the base substrate and an orthogonal projection of the data line of a previous subpixel of the subpixel to which the driving transistor belongs in the first direction onto the base substrate.
  • the subpixel driving circuitry further includes a storage capacitor, a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor, a second electrode plate of the storage capacitor is coupled to the power source signal line, and the voltage stabilizing electrode and the second electrode plate of the storage capacitor are arranged at a same layer and made of a same material.
  • each subpixel further includes: a data line, at least a part of the data line extending in a second direction intersecting the first direction; and a power source signal line. At least a part of the power source signal line extends in the second direction, an orthogonal projection of the second electrode plate of the storage capacitor onto the base substrate overlaps the orthogonal projection of the power source signal line onto the base substrate at a second overlapping region where the second electrode of the storage capacitor is coupled to the power source signal line, and the orthogonal projection of the data line onto the base substrate is located between an orthogonal projection of the first overlapping region onto the base substrate and an orthogonal projection of the gate electrode of the driving transistor of a next subpixel of the subpixel to which data line belongs in the first direction onto the base substrate.
  • the first subpixel includes a green subpixel.
  • the target subpixel includes a green subpixel.
  • the plurality of subpixels further includes red subpixels and blue subpixels.
  • each row of subpixels includes a plurality of groups of subpixels arranged along the first direction, and each group of subpixels includes red subpixels, green subpixels, blue subpixels, and green subpixels cyclically arranged along the first direction.
  • a subpixel closest to the first boundary is the green subpixel.
  • the subpixel driving circuitry includes: a first transistor, a gate electrode of which is coupled to the gate line; a second transistor, a gate electrode of which is coupled to a resetting signal line, a first electrode of which is coupled to an initialization signal line, and a second electrode of which is coupled to the second electrode of the first transistor; a data write-in transistor, a gate electrode of which is coupled to the gate line, a first electrode of which is coupled to the data line, and a second electrode of which is coupled to the first electrode of the driving transistor; a fifth transistor, a gate electrode of the which is coupled to a light-emission control signal line, a first electrode of which is coupled to the power source signal line, and a second electrode of which is coupled to the first electrode of the driving transistor; a sixth transistor, a gate electrode of which is coupled to the light-emission control signal line, a first electrode of which is coupled to the second electrode of the driving transistor, and a second electrode of which is coupled to an anode
  • the present disclosure provides in some embodiments a display device, including the above-mentioned display substrate.
  • the present disclosure provides in some embodiments a method for manufacturing a display substrate, including forming a plurality of subpixels arranged in an array form on a base substrate.
  • the plurality of subpixels is arranged in rows, and each row of subpixels includes a plurality of subpixels arranged in sequence along a first direction.
  • Each subpixel includes a voltage stabilizing electrode, and a subpixel driving circuitry.
  • the subpixel driving circuitry includes a driving transistor and a first transistor, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor is coupled to a gate electrode of the driving transistor, and an active layer of the first transistor includes a first semiconductor portion and a second semiconductor portion spaced apart from each other, and a conductor portion coupled to the first semiconductor portion and the second semiconductor portion.
  • An orthogonal projection of the conductor portion onto the base substrate overlaps an orthogonal projection of the second portion of a previous subpixel of the subpixel to which the conductor portion belongs in the first direction onto the base substrate.
  • Each row of subpixels includes a plurality of first subpixels, the plurality of first subpixels includes target subpixels, and each target subpixel is arranged closest to a first boundary of the display substrate in the row of subpixels.
  • the subpixel driving circuitry includes a storage capacitor, a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor, and a second electrode plate of the storage capacitor is coupled to the power source signal line.
  • the forming the plurality of subpixels arranged in an array form on the base substrate includes forming the voltage stabilizing electrode and the second electrode plate of the storage capacitor simultaneously through a single patterning process.
  • the active layer of the first transistor may include the first semiconductor portion and the second semiconductor portion spaced apart from each other, and the conductor portion coupled to the first semiconductor portion and the second semiconductor portion.
  • the orthogonal projection of the conductor portion onto the base substrate may overlap the orthogonal projection of the voltage stabilizing electrode of the previous subpixel of the subpixel to which the semiconductor portion belongs in the first direction onto the base substrate.
  • the voltage stabilizing electrode and the conductor portion may form a voltage stabilizing capacitor.
  • FIG. 1 is a circuit diagram of a subpixel driving circuitry according to one embodiment of the present disclosure
  • FIG. 2A is a schematic view showing an intermediate manufacturing process of a display substrate according to one embodiment of the present disclosure
  • FIG. 2B is another schematic view showing the intermediate manufacturing process of the display substrate according to one embodiment of the present disclosure.
  • FIG. 2C is yet another schematic view showing the intermediate manufacturing process of the display substrate according to one embodiment of the present disclosure.
  • FIG. 2D is still yet another schematic view showing the intermediate manufacturing process of the display substrate according to one embodiment of the present disclosure.
  • FIG. 2E is still yet another schematic view showing the intermediate manufacturing process of the display substrate according to one embodiment of the present disclosure.
  • FIG. 2F is still yet another schematic view showing the intermediate manufacturing process of the display substrate according to one embodiment of the present disclosure.
  • FIG. 2G is still yet another schematic view showing the intermediate manufacturing process of the display substrate according to one embodiment of the present disclosure.
  • FIG. 3 is a schematic view showing a voltage stabilizing electrode of the display substrate according to one embodiment of the present disclosure.
  • the present disclosure provides in some embodiments a display substrate, which includes a base substrate and a plurality of subpixels arranged in an array form on the base substrate.
  • the plurality of subpixels is arranged in rows, and each row of subpixels includes N subpixels arranged in sequence along a first direction, where N is a positive integer.
  • Each subpixel may include a subpixel driving circuitry.
  • the subpixel driving circuitry may include a driving transistor T 3 and a first transistor T 1 , a first electrode of the first transistor T 1 may be coupled to a second electrode of the driving transistor T 3 , and a second electrode of the first transistor T 1 may be coupled to a gate electrode of the driving transistor T 3 .
  • an active layer of the first transistor T 1 may include a first semiconductor portion 211 and a second semiconductor portion 212 spaced apart from each other, and a conductor portion 213 coupled to the first semiconductor portion 211 and the second semiconductor portion 212 .
  • Each of first to (N ⁇ 1) th subpixels along the first direction may further include a voltage stabilizing electrode
  • each row of subpixels may include a plurality of first subpixels
  • the first subpixels of N th subpixels in the first direction may be target subpixels
  • the target subpixel in the row of subpixels may be arranged closest to a first boundary of the display substrate
  • an orthogonal projection of the conductor portion of the first transistor of the target subpixel onto the base substrate may overlap an orthogonal projection of the voltage stabilizing electrode of the (N ⁇ 1) th subpixel in the row onto the base substrate.
  • an orthogonal projection of the conductor portion 213 onto the base substrate may overlap an orthogonal projection of the voltage stabilizing electrode of a previous subpixel of the subpixel to which the conductor portion belongs in the first direction onto the base substrate.
  • the first transistor T 1 of each subpixel at the boundary of the display substrate may be more sensitive to a voltage change, so the scheme in the embodiments of the present disclosure is more suitable for the subpixels arranged closest to the boundary of the display substrate.
  • the voltage stabilizing electrode 24 and the conductor portion 213 may be electrode plates of a capacitor respectively, and they may form a voltage stabilizing capacitor.
  • the voltage stabilizing capacitor When on and off states of the first transistor T 1 change, it is able for the voltage stabilizing capacitor to stabilize a voltage of the first transistor T 1 , thereby to improve the brightness uniformity of the subpixels of the display substrate.
  • each subpixel may further include a power source signal line 11 , at least a part of the power source signal line 11 may extend in a second direction, and the voltage stabilizing electrode 24 may be coupled to the power source signal line 11 .
  • the first direction refers to a lateral direction in FIGS. 2A to 2G
  • the second direction refers to a longitudinal direction in FIGS. 2A to 2G .
  • the voltage stabilizing electrode 24 may be coupled to the power source signal line 11 to apply a stable voltage to the voltage stabilizing electrode 24 through the power source signal line 11 . In this way, when the voltage stabilizing electrode 24 and the conductor portion 213 form a capacitor, it is able to stabilize the voltage of the first transistor T 1 .
  • the voltage stabilizing electrode 24 may include a first portion 241 and a second portion 242 coupled to each other, an orthogonal projection of the first portion 241 onto the base substrate may overlap an orthogonal projection of the power source signal line 11 onto the base substrate at an overlapping region where the first portion 241 is coupled to the power source signal line 11 , and at least a part of the second portion 242 may extend along the first direction.
  • the orthogonal projection of the conductor portion 213 onto the base substrate may overlap an orthogonal projection of the second portion 242 of a previous subpixel of the subpixel to which the conductor portion belongs in the first direction onto the base substrate.
  • the voltage stabilizing electrode 24 in the embodiments of the present disclosure may be approximately L-shaped. As shown in FIG. 2C , through controlling an extension position and an extension direction of an end portion, the voltage stabilizing electrode 24 may overlap the conductor portion 213 of the next subpixel in the first direction to form a voltage stabilizing capacitor for stabilizing the voltage.
  • each subpixel may further include a data line 16 , and at least a part of the data line 16 may extend in a second direction intersecting the first direction.
  • the subpixel driving circuitry may further include a first conductive connection member 29 extending along the second direction.
  • the second direction may be the longitudinal direction shown in FIG. 1 .
  • an orthogonal projection of the second electrode of the first transistor T 1 onto the base substrate may overlap an orthogonal projection of a first end of the first conductive connection member 29 onto the base substrate at a first overlapping region 291 where the second electrode of the first transistor T 1 is coupled to the first end of the first conductive connection member 29 , and a second end of the first conductive connection member 29 may be coupled to the gate electrode of the driving transistor T 3 .
  • the orthogonal projection of the first portion 241 onto the base substrate may be located between an orthogonal projection of the first overlapping region 291 onto the base substrate and an orthogonal projection of the data line 16 onto the base substrate.
  • a potential at the gate electrode of the driving transistor may be affected by a signal jump across the data line 16 , and brightness of a pixel may be affected by the stability of the potential at the gate electrode.
  • the orthogonal projection of the first portion 241 onto the base substrate is located between the orthogonal projection of the first overlapping region 291 onto the base substrate and the orthogonal projection of the data line 16 onto the base substrate, it is able to improve the stability of the potential at the gate electrode of the driving transistor T 3 .
  • each subpixel may further include a data line 16 , and at least a part of the data line 16 may extend in a second direction intersecting the first direction.
  • the subpixel driving circuitry may further include a data write-in transistor T 4 , a gate electrode of which is coupled to the gate line 12 , a first electrode of which is coupled to the data line 16 , and a second electrode of which is coupled to the first electrode of the driving transistor T 3 .
  • the orthogonal projection of the second portion 242 onto the base substrate may overlap an orthogonal projection of the first electrode of the data write-in transistor T 4 onto the base substrate, and the orthogonal projection of the second portion 242 onto the base substrate may overlap the orthogonal projection of the data line 16 onto the base substrate.
  • the orthogonal projection of the data line 16 onto the base substrate may be located between an orthogonal projection of a channel portion of the data write-in transistor T 4 onto the base substrate and an orthogonal projection of the conductor portion of the first transistor T 1 of a next subpixel onto the base substrate.
  • each subpixel may further include a data line 16 , and at least a part of the data line 16 may extend in a second direction intersecting the first direction.
  • the subpixel driving circuitry may further include a second conductive connection member 3030 , a second transistor T 2 and a seventh transistor T 7 , and at least a part of the second conductive connection member 30 may extend along the second direction.
  • a gate electrode of the second transistor T 2 may be coupled to a resetting signal line 15
  • a first electrode of the second transistor T 2 may be coupled to an initialization signal line 14
  • a second electrode of the second transistor T 2 may be coupled to the second electrode of the first transistor T 1 .
  • a gate electrode of the seventh transistor T 7 may be coupled to a resetting signal line 15 ′ of a next subpixel in the second direction, and a first electrode of the seventh transistor T 7 may be coupled to an initialization signal line 14 ′ of the next subpixel along the second direction, and a second electrode of the seventh transistor T 7 may be coupled to an anode 27 of a corresponding light-emitting element EL.
  • an orthogonal projection of a channel portion of the second transistor T 2 onto the base substrate may be located between the orthogonal projection of the data line 16 onto the base substrate and an orthogonal projection of the second conductive connection member 30 onto the base substrate.
  • an orthogonal projection of a channel portion of the seventh transistor T 7 onto the base substrate may be located between the orthogonal projection of the second conductive connection member 30 coupled to the seventh transistor onto the base substrate and the orthogonal projection of the data line 16 of a previous subpixel of the subpixel to which the seventh transistor belongs in the first direction onto the base substrate.
  • each subpixel may further include a data line 16 , and at least a part of the data line 16 may extend in the second direction intersecting the first direction.
  • the subpixel driving circuitry may further include a fifth transistor T 5 and a sixth transistor T 6 , a gate electrode of the fifth transistor T 5 may be coupled to a light-emission control signal line 13 , a first electrode of the fifth transistor T 5 may be coupled to the power source signal line 11 , and a second electrode of the fifth transistor T 5 may be coupled to the first electrode of the driving transistor T 3 .
  • a gate electrode of the sixth transistor T 6 may be coupled to the light-emission control signal line 13 , a first electrode of the sixth transistor T 6 may be coupled to the second electrode of the driving transistor T 3 , and a second electrode of the sixth transistor T 6 may be coupled to an anode 27 of a light-emitting element EL.
  • An orthogonal projection of a channel portion of the fifth transistor T 5 onto the base substrate may be located between the orthogonal projection of the data line 16 onto the base substrate and the orthogonal projection of the power source signal line 11 onto the base substrate.
  • An orthogonal projection of a channel portion of the sixth transistor T 6 onto the base substrate may be located between the orthogonal projection of the second conductive connection member 30 coupled to the sixth transistor onto the base substrate and the orthogonal projection of the data line 16 of a previous subpixel of the subpixel to which the sixth transistor belongs in the first direction onto the base substrate.
  • each subpixel may further include a data line 16 , and at least a part of the data line 16 may extends in a second direction intersecting the first direction.
  • An orthogonal projection of the first electrode of the driving transistor T 3 onto the base substrate may be located between an orthogonal projection of the gate electrode of the driving transistor T 3 onto the base substrate and the orthogonal projection of the data line 16 onto the base substrate, and an orthogonal projection of the second electrode of the driving transistor T 3 onto the base substrate may be located between the orthogonal projection of the gate electrode of the driving transistor T 3 onto the base substrate and the orthogonal projection of the data line 16 of a previous subpixel of the subpixel to which the driving transistor belongs in the first direction onto the base substrate.
  • the subpixel driving circuitry may further include a storage capacitor Cst, a first electrode plate of the storage capacitor Cst may be coupled to the gate electrode of the driving transistor T 3 , a second electrode plate of the storage capacitor Cst may be coupled to the power source signal line 11 , and the voltage stabilizing electrode 24 and the second electrode plate of the storage capacitor Cst may be arranged at a same layer and made of a same material.
  • the voltage stabilizing electrode 24 and the storage capacitor Cst may be formed through a single patterning process, so as to reduce the quantity of processes as well as the manufacture cost.
  • each subpixel may further include a data line 16 and a power source signal line 11 . At least a part of the data line 16 may extend in a second direction intersecting the first direction. At least a part of the power source signal line 11 may extend in the second direction.
  • An orthogonal projection of the second electrode plate of the storage capacitor Cst onto the base substrate may overlap an orthogonal projection of the power source signal line 11 onto the base substrate at a second overlapping region where the second electrode plate of the storage capacitor Cst is coupled to the power source signal line, and the orthogonal projection of the data line 16 onto the base substrate may be located between an orthogonal projection of the first overlapping region onto the base substrate and the orthogonal projection of the gate electrode of the driving transistor T 3 of a next subpixel of the subpixel to which the data line belongs in the first direction onto the base substrate.
  • the first subpixel may include a green subpixel G.
  • the target subpixel may include a green subpixel G.
  • the first transistor T 1 of the green subpixel G may be more sensitive to the voltage change, so in the embodiments of the present disclosure, mainly the green subpixel G may be compensated.
  • the plurality of subpixels may further include red subpixels and blue subpixels.
  • each row of subpixels may include a plurality of groups of subpixels arranged along the first direction, and each group of subpixels may include red subpixels R, green subpixels G, blue subpixels B, and green subpixels G that are cyclically arranged along the first direction.
  • a subpixel closest to the first boundary may be the green subpixel G.
  • the subpixels in different colors may be arranged in a diamond shape.
  • the red subpixel R, the green subpixel G, the blue subpixel B, and the green subpixel G may be arranged sequentially.
  • a subpixel at an initial position may be a red subpixel R or a blue subpixel B, so that the subpixel at the end may be a green subpixel G.
  • all the subpixels close to one side of the boundary may be red subpixels R or blue subpixels, and all the subpixels close to the other side of the boundary may be green subpixels G.
  • the first boundary may be a boundary where the green subpixels G are located.
  • the subpixel driving circuitry may include: a first transistor T 1 , a gate electrode of which is coupled to the gate line 12 ; a second transistor T 2 , a gate electrode of which is coupled to the resetting signal line 15 , a first electrode of which is coupled to the initialization signal line 14 , and a second electrode of which is coupled to a second electrode of the first transistor T 1 ; a driving transistor T 3 ; a data write-in transistor T 4 , a gate electrode of which is coupled to the gate line 12 , a first electrode of which is coupled to the data line 16 , and a second electrode of which is coupled to a first electrode of the driving transistor T 3 ; a fifth transistor T 5 , a gate electrode of which is coupled to the light-emission control signal line 13 , a first electrode of which is coupled to the power source signal line 11 , and a second electrode of which is coupled to the first electrode of the driving transistor T 3 ; a sixth
  • the present disclosure further provides in some embodiments a display device including the above-mentioned display substrate.
  • the display device includes the above-mentioned display substrate, so it is able for the display device to achieve at least the above-mentioned technical effect, which will not be particularly defined herein.
  • the present disclosure further provides in some embodiments a method for manufacturing a display substrate, which includes forming a plurality of subpixels arranged in an array form on a base substrate.
  • an active layer 21 may be formed onto the base substrate at first.
  • a first gate layer 22 may be formed.
  • a second gate layer 23 and the voltage stabilizing electrode 24 may be formed.
  • an interlayer dielectric layer 25 may be formed.
  • a source/drain electrode layer including the power source signal line 11 and the data line 16 , may be formed.
  • a PLN via hole 26 may be formed.
  • the anode 27 of the light-emitting element EL and a pixel definition layer 28 may be formed.
  • the manufactured display substrate may be that mentioned hereinabove, and thus will not be particularly defined herein.
  • the subpixel driving circuitry may further include a storage capacitor Cst, a first electrode plate of which is coupled to the gate electrode of the driving transistor T 3 , and a second electrode plate of which is coupled to the power source signal line 11 .
  • the forming the plurality of subpixels arranged in an array form onto the base substrate may include forming the voltage stabilizing electrode and the second electrode plate of the storage capacitor simultaneously through a single patterning process.
  • the voltage stabilizing electrode 24 and the second electrode plate of the storage capacitor Cst may be formed through a single patterning process, so as to reduce the quantity of processes as well as the manufacture cost.

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