US20220012394A1 - Electronic signal verification using a translated simulated waveform - Google Patents

Electronic signal verification using a translated simulated waveform Download PDF

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Publication number
US20220012394A1
US20220012394A1 US17/370,930 US202117370930A US2022012394A1 US 20220012394 A1 US20220012394 A1 US 20220012394A1 US 202117370930 A US202117370930 A US 202117370930A US 2022012394 A1 US2022012394 A1 US 2022012394A1
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United States
Prior art keywords
waveform
circuit
simulated
translated
node
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Pending
Application number
US17/370,930
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English (en)
Inventor
David Everett Burgess
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
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Tektronix Inc
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Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Priority to JP2023501454A priority Critical patent/JP2023535138A/ja
Priority to CN202180049023.XA priority patent/CN115803640A/zh
Priority to PCT/US2021/040963 priority patent/WO2022011190A1/en
Priority to DE112021003675.0T priority patent/DE112021003675T5/de
Priority to US17/370,930 priority patent/US20220012394A1/en
Assigned to TEKTRONIX, INC reassignment TEKTRONIX, INC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Burgess, David Everett
Publication of US20220012394A1 publication Critical patent/US20220012394A1/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/31835—Analysis of test coverage or failure detectability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/323—Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
US17/370,930 2020-07-09 2021-07-08 Electronic signal verification using a translated simulated waveform Pending US20220012394A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2023501454A JP2023535138A (ja) 2020-07-09 2021-07-08 変換されたシミュレーション波形を用いた電子信号の検証
CN202180049023.XA CN115803640A (zh) 2020-07-09 2021-07-08 使用转换仿真波形的电子信号验证
PCT/US2021/040963 WO2022011190A1 (en) 2020-07-09 2021-07-08 Electronic signal verification using a translated simulated waveform
DE112021003675.0T DE112021003675T5 (de) 2020-07-09 2021-07-08 Elektronische signalüberprüfung mit einer übersetzten simulierten wellenform
US17/370,930 US20220012394A1 (en) 2020-07-09 2021-07-08 Electronic signal verification using a translated simulated waveform

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202063050053P 2020-07-09 2020-07-09
US17/370,930 US20220012394A1 (en) 2020-07-09 2021-07-08 Electronic signal verification using a translated simulated waveform

Publications (1)

Publication Number Publication Date
US20220012394A1 true US20220012394A1 (en) 2022-01-13

Family

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Family Applications (2)

Application Number Title Priority Date Filing Date
US17/370,930 Pending US20220012394A1 (en) 2020-07-09 2021-07-08 Electronic signal verification using a translated simulated waveform
US17/370,976 Active US11520966B2 (en) 2020-07-09 2021-07-08 Automated assisted circuit validation

Family Applications After (1)

Application Number Title Priority Date Filing Date
US17/370,976 Active US11520966B2 (en) 2020-07-09 2021-07-08 Automated assisted circuit validation

Country Status (5)

Country Link
US (2) US20220012394A1 (de)
JP (2) JP2023535138A (de)
CN (3) CN115803640A (de)
DE (2) DE112021003675T5 (de)
WO (2) WO2022011192A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114510902A (zh) * 2022-04-20 2022-05-17 北京芯愿景软件技术股份有限公司 仿真结果的验证方法、装置、设备及计算机存储介质

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117115364B (zh) * 2023-10-24 2024-01-19 芯火微测(成都)科技有限公司 微处理器sip电路测试状态监控方法、系统及存储介质

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US20020129326A1 (en) * 2001-03-08 2002-09-12 Nuber Paul D. Method for inserting repeaters in hierarchical chip design
US20040025136A1 (en) * 2002-07-30 2004-02-05 Carelli John A. Method for designing a custom ASIC library
US20050024057A1 (en) * 2003-06-20 2005-02-03 Romain Desplats Methods of using measured time resolved photon emission data and simulated time resolved photon emission data for fault localization
US6996068B1 (en) * 2000-03-31 2006-02-07 Intel Corporation Audio testing in a packet switched network
US20170147736A1 (en) * 2015-11-19 2017-05-25 International Business Machines Corporation Automated scan chain diagnostics using emission
US20180365370A1 (en) * 2017-06-18 2018-12-20 Coventor, Inc. System and method for key parameter identification, process model calibration and variability analysis in a virtual semiconductor device fabrication environment
US20220221411A1 (en) * 2019-05-31 2022-07-14 Hamamatsu Photonics K.K. Semiconductor apparatus examination method and semiconductor apparatus examination apparatus

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US5325309A (en) * 1991-04-30 1994-06-28 Lsi Logic Corporation Method and apparatus for integrated circuit diagnosis
US6671846B1 (en) * 2000-06-20 2003-12-30 Lsi Logic Corporation Method of automatically generating schematic and waveform diagrams for isolating faults from multiple failing paths in a circuit using input signal predictors and transition times
US7089517B2 (en) * 2000-09-29 2006-08-08 Advantest Corp. Method for design validation of complex IC
US7408336B2 (en) * 2005-10-26 2008-08-05 International Business Machines Corporation Importation of virtual signals into electronic test equipment to facilitate testing of an electronic component
KR100858651B1 (ko) * 2006-11-01 2008-09-16 주식회사 유니테스트 순차적 반도체 테스트 장치
US8463587B2 (en) * 2009-07-28 2013-06-11 Synopsys, Inc. Hierarchical order ranked simulation of electronic circuits
US8769360B2 (en) * 2010-10-14 2014-07-01 International Business Machines Corporation Dynamic detection and identification of the functional state of multi-processor cores
US9304163B2 (en) * 2013-11-07 2016-04-05 Qualcomm Incorporated Methodology for testing integrated circuits
US9990455B1 (en) * 2017-12-13 2018-06-05 Tactotek Oy Arrangement and method for facilitating electronics design in connection with 3D structures
US11113444B2 (en) * 2018-06-27 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Machine-learning based scan design enablement platform
KR102565184B1 (ko) * 2018-07-09 2023-08-08 에스케이하이닉스 주식회사 디지털 회로를 모델링하는 회로 모듈 및 이를 포함하는 시뮬레이션 장치

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6996068B1 (en) * 2000-03-31 2006-02-07 Intel Corporation Audio testing in a packet switched network
US20020120922A1 (en) * 2000-12-05 2002-08-29 International Business Machines Corporation Embedded hardware description language instrumentation
US20020129326A1 (en) * 2001-03-08 2002-09-12 Nuber Paul D. Method for inserting repeaters in hierarchical chip design
US20040025136A1 (en) * 2002-07-30 2004-02-05 Carelli John A. Method for designing a custom ASIC library
US20050024057A1 (en) * 2003-06-20 2005-02-03 Romain Desplats Methods of using measured time resolved photon emission data and simulated time resolved photon emission data for fault localization
US20170147736A1 (en) * 2015-11-19 2017-05-25 International Business Machines Corporation Automated scan chain diagnostics using emission
US20180365370A1 (en) * 2017-06-18 2018-12-20 Coventor, Inc. System and method for key parameter identification, process model calibration and variability analysis in a virtual semiconductor device fabrication environment
US20220221411A1 (en) * 2019-05-31 2022-07-14 Hamamatsu Photonics K.K. Semiconductor apparatus examination method and semiconductor apparatus examination apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114510902A (zh) * 2022-04-20 2022-05-17 北京芯愿景软件技术股份有限公司 仿真结果的验证方法、装置、设备及计算机存储介质

Also Published As

Publication number Publication date
DE112021003675T5 (de) 2023-05-04
CN115803642A (zh) 2023-03-14
US20220012397A1 (en) 2022-01-13
JP2023534200A (ja) 2023-08-08
JP2023535138A (ja) 2023-08-16
WO2022011192A1 (en) 2022-01-13
CN115803640A (zh) 2023-03-14
US11520966B2 (en) 2022-12-06
WO2022011190A1 (en) 2022-01-13
CN115843466A (zh) 2023-03-24
DE112021003677T5 (de) 2023-05-04

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