US20210083089A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20210083089A1
US20210083089A1 US16/702,790 US201916702790A US2021083089A1 US 20210083089 A1 US20210083089 A1 US 20210083089A1 US 201916702790 A US201916702790 A US 201916702790A US 2021083089 A1 US2021083089 A1 US 2021083089A1
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Prior art keywords
insulating member
semiconductor substrate
portions
region
layer
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Abandoned
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US16/702,790
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English (en)
Inventor
Kanako Komatsu
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOMATSU, KANAKO
Publication of US20210083089A1 publication Critical patent/US20210083089A1/en
Priority to US17/677,578 priority Critical patent/US12356657B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H01L29/7802—
    • H01L29/0649—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • Embodiments relate to a semiconductor device.
  • DMOS Double-Diffused MOSFET
  • STI Shallow Trench Isolation; an element separation insulator
  • the ON-resistance increases due to the existence of the STI.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment
  • FIG. 2 is a partially enlarged plan view showing the semiconductor device according to the first embodiment
  • FIG. 3A is a cross-sectional view along line A-A′ shown in FIG. 2 ;
  • FIG. 3B is a cross-sectional view along line B-B′ shown in FIG. 2 ;
  • FIG. 4 is a perspective cross-sectional view showing the semiconductor device according to the first embodiment
  • FIG. 5 is a partially enlarged plan view showing a semiconductor device according to a second embodiment
  • FIG. 6A is a cross-sectional view along line A-A′ shown in FIG. 5 ; and FIG. 6B is a cross-sectional view along line B-B′ shown in FIG. 5 ;
  • FIG. 7 is a perspective cross-sectional view showing the semiconductor device according to the second embodiment.
  • FIGS. 8A and 8B are cross-sectional views showing a semiconductor device according to a third embodiment
  • FIG. 9 is a perspective cross-sectional view showing the semiconductor device according to the third embodiment.
  • FIGS. 10A and 10B are cross-sectional views showing a semiconductor device according to a fourth embodiment
  • FIG. 11 is a perspective cross-sectional view showing the semiconductor device according to the fourth embodiment.
  • FIGS. 12A and 12B are cross-sectional views showing a semiconductor device according to a fifth embodiment
  • FIG. 13 is a perspective cross-sectional view showing the semiconductor device according to the fifth embodiment.
  • FIGS. 14A and 14B are cross-sectional views showing a semiconductor device according to a sixth embodiment.
  • FIG. 15 is a perspective cross-sectional view showing the semiconductor device according to the sixth embodiment.
  • a semiconductor device in general, includes a semiconductor substrate, an insulating member provided on the semiconductor substrate and an electrode disposed on the semiconductor substrate and on the insulating member.
  • the insulating member includes a plurality of first portions and a plurality of second portions thinner than the first portions. The first portions and the second portions are arranged alternately along a first direction, the first direction being parallel to a region of an upper surface of the semiconductor substrate not contacting the insulating member.
  • FIG. 1 is a plan view showing a semiconductor device according to the embodiment.
  • FIG. 2 is a partially enlarged plan view showing the semiconductor device according to the embodiment.
  • FIG. 3A is a cross-sectional view along line A-A′ shown in FIG. 2 ; and FIG. 3B is a cross-sectional view along line B-B′ shown in FIG. 2 .
  • FIG. 4 is a perspective cross-sectional view showing the semiconductor device according to the embodiment.
  • FIGS. 3A and 3B only a silicon substrate 10 , a first portion 33 and a second portion 34 of an insulating member 32 , and a gate electrode 42 described below are shown for easier viewing of the drawing. This is similar for FIGS. 6A and 6B , FIGS. 8A and 8B , FIGS. 10A and 10B , FIGS. 12A and 12B , and FIGS. 14A and 14B as well.
  • the vertical-horizontal ratios of the components do not always match between the drawings.
  • the silicon substrate 10 is provided as a semiconductor substrate.
  • the silicon substrate 10 is made of single-crystal silicon (Si).
  • a deep n-well 11 which is of an n-conductivity type is provided in a portion of the upper layer portion of the silicon substrate 10 .
  • the conductivity type of the portion of the silicon substrate 10 surrounding the deep n-well 11 may be a p-type.
  • an XYZ orthogonal coordinate system is employed for convenience of description, Two mutually-orthogonal directions parallel to an upper surface 10 a of the silicon substrate 10 are taken as an “X-direction” and a “Y-direction”; and a direction perpendicular to the upper surface 10 a is taken as a “Z-direction.”
  • the Z-direction also is called the “vertical direction.”
  • the direction away from the silicon substrate 10 as referenced to the upper surface 10 a also is called “up”; and the direction into the silicon substrate 10 as referenced to the upper surface 10 a also is called “down.”
  • a drift layer 12 of the p-conductivity type and a p-well 13 of the p-conductivity type are provided in a central portion on the deep n-well 11 .
  • the impurity concentration of the p-well 13 is higher than the impurity concentration of the drift layer 12 .
  • the “impurity concentration” is the concentration of an impurity used as carriers inside the silicon.
  • the drift layer 12 and the p-well 13 have rectangular configurations extending in the Y-direction. In the example shown in FIG. 4 , the p-well 13 pierces the central portion of the drift layer 12 ; and the lower surface of the p-well 13 is positioned lower than the lower surface of the drift layer 12 .
  • the lower surface of the p-well 13 may be positioned higher than the lower surface of the drift layer 12 .
  • a drain contact layer 14 of the p-conductivity type is provided on the p-well 13 .
  • the impurity concentration of the drain contact layer 14 is higher than the impurity concentration of the p-well 13 .
  • the drain contact layer 14 also extends in the Y-direction parallel to the upper surface 10 a of the silicon substrate 10 .
  • n-well 15 of the n-conductivity type is provided in a peripheral portion on the deep n-well 11 .
  • the n-well 15 has a rectangular frame-shaped configuration surrounding the drift layer 12 and the p-well 13 .
  • the n-well 15 is separated from the drift layer 12 and separated from the outer surface of the deep n-well 11 .
  • a portion 11 a of the deep n-well 11 is disposed between the drift layer 12 and the n-well 15 .
  • a source layer 16 of the p-conductivity type is provided at a portion on the n-well 15 .
  • a source contact layer 17 of the p-conductivity type is provided at a portion on the source layer 16 .
  • the impurity concentration of the source contact layer 17 is higher than the impurity concentration of the source layer 16 .
  • the source contact layer 17 extends in the Y-direction parallel to the upper surface 10 a of the silicon substrate 10 .
  • a body layer 18 of the n-conductivity type is provided in another portion on the n-well 15 .
  • the impurity concentration of the body layer 18 is higher than the impurity concentration of the n-well 15 .
  • the body layer 18 contacts the source layer 16 .
  • a body contact layer 19 of the n-conductivity type is provided at a portion on the body layer 18 .
  • the impurity concentration of the body contact layer 19 is higher than the impurity concentration of the body layer 18 .
  • the body contact layer 19 contacts the source contact layer 17 .
  • the source layer 16 , the source contact layer 17 , the body layer 18 , and the body contact layer 19 have frame-shaped configurations surrounded with the n-well 15 .
  • the deep n-well 11 , the drift layer 12 , the p-well 13 , the drain contact layer 14 , the n-well 15 , the source layer 16 , the source contact layer 17 , the body layer 18 , and the body contact layer 19 are portions of the silicon substrate 10 .
  • STI 31 is provided as an element separation insulator on the silicon substrate 10 .
  • the STI 31 is formed of silicon oxide (SiO).
  • SiO silicon oxide
  • the STI 31 has a rectangular frame-shaped configuration and is disposed along the outer edge of the deep n-well 11 .
  • the outer edge of the deep n-well 11 contacts the bottom surface of the STI 31 .
  • the region that is surrounded with the STI 31 is called an “element region.”
  • the insulating member 32 is provided on the silicon substrate 10 .
  • the insulating member 32 is formed of silicon oxide, Multiple first portions 33 and multiple second portions 34 are provided in the insulating member 32 .
  • the insulating member 32 is disposed between the drain contact layer 14 and the source contact layer 17 or in the region directly above the region between the drain contact layer 14 and the source contact layer 17 ; for example, the insulating member 32 is disposed between the drain contact layer 14 and the portion 11 a of the deep n-well 11 or in the region directly above the region between the drain contact layer 14 and the portion 11 a of the deep n-well 11 .
  • the mutually-adjacent first portion 33 and second portion 34 contact each other.
  • not less than half of the first portion 33 is disposed inside the silicon substrate 10 .
  • substantially the entire first portion 33 is disposed inside the silicon substrate 10 .
  • a region of an upper surface 33 a of the first portion 33 exists where the upper surface 33 a is not covered with the silicon substrate 10 .
  • the entire upper surface 33 a is not covered with the silicon substrate 10 .
  • the first portion 33 is formed in the same process as the STI 31 .
  • not less than half of the second portion 34 is positioned higher than a region of the upper surface 10 a of the silicon substrate 10 not contacting the insulating member 32 .
  • substantially the entire second portion 34 is positioned higher than the region of the upper surface 10 a not contacting the insulating member 32 . Therefore, the upper surface 33 a of the first portion 33 is positioned lower than an upper surface 34 a of the second portion 34 ; and a lower surface 33 b of the first portion 33 is positioned lower than a lower surface 34 b of the second portion 34 .
  • the position of the upper surface 33 a of the first portion 33 is substantially the same as the position of the lower surface 34 b of the second portion 34 .
  • the second portion 34 is, for example, a stepped oxide (STO) and is formed in a process different from that of the STI 31 .
  • the first portion 33 and the second portion 34 are arranged alternately along the Y-direction.
  • the first portion 33 and the second portion 34 are arranged alternately along the Y-direction (the first direction) parallel to the region of the upper surface 10 a of the silicon substrate 10 (the semiconductor substrate) not contacting the insulating member 32 .
  • the first portion 33 and the second portion 34 are arranged periodically.
  • the mutually-adjacent first portion 33 and second portion 34 contact each other.
  • a thickness t 2 of the second portion 34 is thinner than a thickness t 1 of the first portion 33 . In other words, t 2 ⁇ t 1 .
  • the “thickness” means the length in the Z-direction.
  • a gate insulating film 41 which is made of, for example, silicon oxide is provided on the silicon substrate 10 ; and the gate electrode 42 is provided on the gate insulating film 41 and on the insulating member 32 .
  • the gate electrode 42 is disposed over at least a region directly above the n-well 15 , a region directly above the portion 11 a of the deep n-well 11 , a region directly above the drift layer 12 , a region directly above the first portion 33 of the insulating member 32 , and a region directly above the second portion 34 of the insulating member 32 .
  • the gate insulating film 41 is thinner than the second portion 34 of the insulating member 32 .
  • a sidewall is provided on the side surface of the gate electrode 42 and on the side surface of the second portion 34 of the insulating member 32 .
  • the sidewall is not illustrated for easier viewing of the drawings. This is similar for the other embodiments described below.
  • the sidewall is made of an insulating material and is, for example, a stacked body of a silicon oxide layer and a silicon nitride layer.
  • the gate insulating film 41 is disposed between the silicon substrate 10 and the gate electrode 42 , between the silicon substrate 10 and the sidewall, and between the silicon substrate 10 and the second portion 34 .
  • the gate insulating film 41 is not disposed between the silicon substrate 10 and the first portion 33 , The gate insulating film 41 may be disposed between the silicon substrate 10 and the first portion 33 .
  • the gate electrode 42 has a generally frame-shaped configuration including the region directly above the outer edge of the insulating member 32 .
  • a pair of X-side portions that extend in the X-direction and a pair of Y-side portions that extend in the Y-direction are provided in the gate electrode 42 .
  • the Y-side portions each have comb-shaped configurations. More specifically, a base portion 42 a which has a band configuration extending in the Y-direction and multiple tooth portions 42 b which extend in the X-direction from the base portion 42 a toward the p-well 13 side (the drain side) are provided in each of the Y-side portions of the gate electrode 42 .
  • the multiple tooth portions 42 b are separated from each other along the Y-direction and are, for example, arranged periodically.
  • the portion of the base portion 42 a of the gate electrode 42 on the drain side overlaps both the first portion 33 and the second portion 34 of the insulating member 32 .
  • the tooth portion 42 b overlaps the first portion 33 ; and the second portion 34 is positioned between the tooth portions 42 b .
  • a protruding portion 42 c that reflects the configuration of the second portion 34 may be formed at the portion of the base portion 42 a covering the second portion 34 of the insulating member 32 .
  • the protruding portion 42 c may not be formed.
  • An inter-layer insulating film (not illustrated) is provided on the silicon substrate 10 to cover the gate electrode 42 .
  • Multiple contacts (not illustrated) and multiple interconnects (not illustrated) are provided inside the inter-layer insulating film.
  • the interconnects are connected to the drain contact layer 14 , the source contact layer 17 , the body contact layer 19 , the gate electrode 42 , etc., via the contacts.
  • a p-channel DMOS 61 is formed in the semiconductor device 1 inside the element region partitioned by the STI 31 .
  • the DMOS 61 includes the insulating member 32 , A channel region is formed of the n-well 15 and the portion 11 a of the deep n-well 11 in the DMOS 61 .
  • the source side of the DMOS 61 is marked with the reference numeral “5”; and the drain side of the DMOS 61 is marked with the reference numeral “D.”
  • the direction from the source contact layer 17 toward the drain contact layer 14 is the X-direction.
  • the drain-gate distance is long; and the breakdown voltage is high.
  • the tooth portions 42 b of the gate electrode 42 are disposed on the first portions 33 , the gate-drain distance can be ensured while relaxing the concentration of the electric field inside the drift layer 12 by the field plate effect; and the breakdown voltage can be increased.
  • Another portion of the ON-current flows through the region directly under the second portion 34 of the insulating member 32 and is not impeded by the first portion 33 . Therefore, the ON-resistance of the DMOS 61 can be reduced. In this current path, the concentration of the electric field inside the drift layer 12 can be relaxed because the portion of the base portion 42 a of the gate electrode 42 on the drain side is disposed on the second portion 34 of the insulating member 32 .
  • the concentration of the electric field can be relaxed not only in the XZ plane but also in three-dimensional space including the Y-direction; and a DMOS that has excellent balance between the breakdown voltage and the ON-resistance can be realized.
  • FIG. 5 is a partially enlarged plan view showing a semiconductor device according to the embodiment.
  • FIG. 6A is a cross-sectional view along line A-A′ shown in FIG. 5 ; and FIG. 6B is a cross-sectional view along line B-B′ shown in FIG. 5 .
  • FIG. 7 is a perspective cross-sectional view showing the semiconductor device according to the embodiment.
  • the semiconductor device 2 according to the embodiment differs from the semiconductor device 1 according to the first embodiment (referring to FIG. 1 to FIG. 4 ) in that a gate electrode 43 is provided instead of the gate electrode 42 .
  • the gate electrode 43 has a frame-shaped configuration.
  • a band-shaped portion 43 a is provided as a Y-side portion extending in the Y-direction.
  • Two side surfaces 43 b of the band-shaped portion 43 a extend in linear configurations in the Y-direction.
  • tooth portions such as those of the gate electrode 42 are not provided at the band-shaped portion 43 a .
  • a protruding portion 43 c that reflects the configuration of the second portion 34 may be formed at the portion of the band-shaped portion 43 a covering the second portion 34 of the insulating member 32 .
  • the protruding portion 43 c may not be formed.
  • the thickness t 2 of the second portion 34 of the insulating member 32 is sufficiently thick, the necessary breakdown voltage can be ensured even without providing the tooth portions in the gate electrode 43 . Otherwise, the configuration, the operations, and the effects of the embodiment are similar to those of the first embodiment.
  • the thickness t 2 of the second portion 34 is thinner than the thickness t 1 of the first portion 33 . In other words, t 2 ⁇ t 1 .
  • the thickness t 2 of the second portion 34 may be thick and may be the same as the thickness t 1 of the first portion 33 . In other words, t 2 ⁇ t 1 is possible.
  • FIGS. 8A and 8B are cross-sectional views showing a semiconductor device according to the embodiment.
  • FIG. 9 is a perspective cross-sectional view showing the semiconductor device according to the embodiment.
  • the position of the cross section shown in FIG. 8A corresponds to line A-A′ shown in FIG. 5 ; and the position of the cross section shown in FIG. 8B corresponds to line B-B′ shown in FIG. 5 .
  • the semiconductor device 3 according to the embodiment differs from the semiconductor device 2 according to the second embodiment (referring to FIG. 5 , FIGS. 6A and 6B , and FIG. 7 ) in that an insulating member 35 is provided instead of the insulating member 32 .
  • the multiple first portions 33 and multiple second portions 36 are provided in the insulating member 35 .
  • not less than half of the second portion 36 is disposed inside the silicon substrate 10 .
  • substantially the entire second portion 36 is disposed inside the silicon substrate 10 .
  • a region of an upper surface 36 a of the second portion 36 may exist where the upper surface 36 a is not covered with the silicon substrate 10 .
  • the entire upper surface 36 a is not covered with the silicon substrate 10 .
  • the position and the configuration of the first portion 33 are similar to those of the second embodiment.
  • the second portion 36 is formed in the same process as one of the STIs provided in the semiconductor device 3 .
  • the multiple first portions 33 and the multiple second portions 36 are arranged alternately in the Y-direction.
  • the mutually-adjacent first portion 33 and second portion 36 contact each other.
  • a thickness t 3 of the second portion 36 is thinner than the thickness t 1 of the first portion 33 . In other words, t 3 ⁇ t 1
  • the gate insulating film 41 is thinner than the second portion 36 .
  • the band-shaped portion 43 a that extends in the Y-direction is provided in the gate electrode 43 .
  • the two side surfaces 43 b of the band-shaped portion 43 a extend in linear configurations in the Y-direction.
  • the protruding portion 43 c (referring to FIG. 7 ) is not formed at the band-shaped portion 43 a . Otherwise, the configuration, the operations, and the effects of the embodiment are similar to those of the first embodiment.
  • FIGS. 10A and 10B are cross-sectional views showing a semiconductor device according to the embodiment.
  • FIG. 11 is a perspective cross-sectional view showing the semiconductor device according to the embodiment.
  • the position of the cross section shown in FIG. 10A corresponds to line A-A′ shown in FIG. 2 ; and the position of the cross section shown in FIG. 10B corresponds to line B-B′ shown in FIG. 2 .
  • the semiconductor device 4 according to the embodiment differs from the semiconductor device 1 according to the first embodiment (referring to FIG. 1 to FIG. 4 ) in that an insulating member 37 is provided instead of the insulating member 32 .
  • an insulating member 37 is provided instead of the insulating member 32 .
  • not less than half of the insulating member 37 e.g., substantially the entirety, is positioned higher than a region of the upper surface 10 a of the silicon substrate 10 not contacting the insulating member 37 .
  • the insulating member 37 is formed of, for example, silicon oxide.
  • first portions 38 and multiple second portions 39 are arranged alternately and, for example, periodically along the Y-direction.
  • the mutually-adjacent first portion 38 and second portion 39 contact each other.
  • the first portion 38 and the second portion 39 of the insulating member 37 each is, for example, a stepped oxide.
  • a thickness t 5 of the second portion 39 is thinner than a thickness t 4 of the first portion 38 . In other words, t 5 ⁇ t 4 .
  • the gate insulating film 41 is thinner than the second portion 39 .
  • An upper surface 38 a of the first portion 38 is positioned higher than an upper surface 39 a of the second portion 39 . In the Z-direction, the position of a lower surface 38 b of the first portion 38 is substantially the same as the position of a lower surface 39 b of the second portion 39 .
  • the gate electrode 42 is provided in the semiconductor device 4 .
  • the configuration of the gate electrode 42 is similar to the configuration of the gate electrode 42 of the semiconductor device 1 according to the first embodiment.
  • the Y-side portion of the gate electrode 42 has a comb-shaped configuration; and one base portion 42 a extending in the Y-direction and multiple tooth portions 42 b extending from the base portion 42 a toward the X-direction drain side are provided.
  • the portion of the base portion 42 a on the side opposite to the tooth portions 42 b is disposed on the silicon substrate 10 with the gate insulating film 41 interposed.
  • the portion of the base portion 42 a at the tooth portion 42 b side extends onto both the first portion 38 and the second portion 39 of the insulating member 37 .
  • the tooth portion 42 b is disposed on the first portion 38 of the insulating member 37 . Therefore, in the vertical direction, the tooth portion 42 b overlaps the first portion 38 ; and the second portion 39 is positioned between the tooth portions 42 b .
  • An unevenness that reflects the configuration of the insulating member 37 may be formed in the upper surface of the gate electrode 42 .
  • the concentration of the electric field inside the silicon substrate 10 can be suppressed because the tooth portion 42 b of the gate electrode 42 extends toward the drain side. Also, the drain-gate breakdown voltage can be ensured because the tooth portion 42 b is disposed on the first portion 38 of the insulating member 37 . Also, because the portion of the base portion 42 a of the gate electrode 42 at the tooth portion 42 b side is disposed on the first portion 38 and on the second portion 39 of the insulating member 37 , the concentration of the electric field inside the silicon substrate 10 can be suppressed; and the breakdown voltage can be ensured.
  • the electric field distribution inside the silicon substrate 10 can be controlled three-dimensionally. Otherwise, the configuration, the operations, and the effects of the embodiment are similar to those of the first embodiment.
  • FIGS. 12A and 12B are cross-sectional views showing a semiconductor device according to the embodiment.
  • FIG. 13 is a perspective cross-sectional view showing the semiconductor device according to the embodiment.
  • the position of the cross section shown in FIG. 12A corresponds to line A-A′ shown in FIG. 5 ; and the position of the cross section shown in FIG. 12B corresponds to line B-B′ shown in FIG. 5 .
  • the embodiment is an example in which the second embodiment and the fourth embodiment described above are combined.
  • the insulating member 37 described in the fourth embodiment and the gate electrode 43 described in the second embodiment are provided.
  • first portion 38 and the second portion 39 which is thinner than the first portion 38 , are arranged alternately along the Y-direction in the insulating member 37 .
  • first portion 38 and the second portion 39 are arranged alternately along the Y-direction in the insulating member 37 .
  • not less than half in the Z-direction e.g., substantially the entirety, is disposed higher than the region of the upper surface 10 a of the silicon substrate 10 not contacting the insulating member 37 .
  • the band-shaped portion 43 a that extends in the Y-direction is provided in the gate electrode 43 .
  • the portion of the band-shaped portion 43 a at the source side is disposed on the silicon substrate 10 with the gate insulating film 41 interposed.
  • the portion of the band-shaped portion 43 a at the drain side extends onto the first portion 38 and onto the second portion 39 of the insulating member 37 .
  • An unevenness that reflects the configuration of the insulating member 37 may be formed in the upper surface of the gate electrode 43 . Otherwise, the configuration, the operations, and the effects of the embodiment are similar to those of the first embodiment.
  • FIGS. 14A and 14B are cross-sectional views showing a semiconductor device according to the embodiment.
  • FIG. 15 is a perspective cross-sectional view showing the semiconductor device according to the embodiment.
  • the position of the cross section shown in FIG. 14A corresponds to line A-A′ shown in FIG. 2 ; and the position of the cross section shown in FIG. 14B corresponds to line B-B′ shown in FIG. 2 .
  • the semiconductor device 6 according to the embodiment differs from the semiconductor device 4 according to the fourth embodiment (referring to FIGS. 10A and 10B and FIG. 11 ) in that the second portion 39 of the insulating member 37 is not provided.
  • the semiconductor device 4 only the first portions 38 of the insulating member 37 are arranged to be separated from each other along the Y-direction.
  • the gate insulating film 41 is provided between the silicon substrate 10 and the first portion 38 .
  • the gate insulating film 41 is provided between the silicon substrate 10 and the gate electrode 42 in the region between the first portions 38 .
  • the silicon substrate 10 , multiple insulating members (the first portions 38 ) provided on the silicon substrate 10 and arranged to be separated from each other along the Y-direction, and the gate electrode 42 disposed on the silicon substrate 10 and on the multiple insulating members (the first portions 38 ) are provided in the semiconductor device 6 .
  • the base portion 42 a that extends in the Y-direction and the multiple tooth portions 42 b that extend from the base portion 42 a toward the X-direction drain side are provided at the Y-side portion of the gate electrode 42 .
  • the first portion 38 overlaps the tooth portion 42 b ; and the region between the first portions 38 overlaps the region between the tooth portions 42 b.
  • the necessary breakdown voltage of the semiconductor device 6 the necessary ON-resistance and breakdown voltage can be realized even without providing the second portion 39 of the insulating member 37 . Otherwise, the configuration, the operations, and the effects of the embodiment are similar to those of the first embodiment.
  • a semiconductor device that has excellent balance between the breakdown voltage and the ON-resistance can be realized.
  • a DMOS is provided in the semiconductor device, this is not limited thereto.
  • a LDMOS Longterally Diffused MOS
  • a DEMOS Drain Extended MOS
  • EDMOS Extended Drain MOS
  • an orthogonal gate extended drain MOS an orthogonal gate extended drain MOS
  • a high breakdown-voltage MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • the semiconductor substrate may be, for example, a SiC substrate, a SiGe substrate, or a compound semiconductor substrate. Also, the conductivity types of the components may be reversed.
  • the invention includes the following aspects.
  • a semiconductor device comprising:
  • the first insulating members and the second insulating members being arranged alternately along a first direction parallel to the upper surface of the semiconductor substrate.
  • a semiconductor device comprising:
  • the insulating member including
  • the first portions and the second portions being arranged alternately along a first direction parallel to the upper surface of the semiconductor substrate.
  • a semiconductor device comprising:
  • the insulating member including
  • the first portions and the second portions being arranged alternately along a first direction parallel to an upper surface of the semiconductor substrate.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
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