US20190157432A1 - Manufacturing method of display substrate, display substrate and display device - Google Patents

Manufacturing method of display substrate, display substrate and display device Download PDF

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Publication number
US20190157432A1
US20190157432A1 US15/983,055 US201815983055A US2019157432A1 US 20190157432 A1 US20190157432 A1 US 20190157432A1 US 201815983055 A US201815983055 A US 201815983055A US 2019157432 A1 US2019157432 A1 US 2019157432A1
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Prior art keywords
base substrate
via hole
manufacturing
layer
film layer
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US15/983,055
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English (en)
Inventor
Jun Liu
Luke Ding
Jiangang Fang
Bin Zhou
Leilei CHENG
Wei Li
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Assigned to HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD. reassignment HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHENG, Leilei, DING, Luke, FANG, Jingang, LI, WEI, LIU, JUN, ZHOU, BIN
Publication of US20190157432A1 publication Critical patent/US20190157432A1/en
Priority to US17/449,607 priority Critical patent/US20220020867A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and in particular, to a manufacturing method of a display substrate, a display substrate, and a display device.
  • An Organic Light-Emitting Diode (OLED) display device has advantages such as thinness, lightness, wide viewing angle, active light emission, continuously adjustable light color, low cost, fast response speed, low energy consumption, low driving voltage, wide operating temperature range, simple production process, high luminous efficiency, flexible display and the like, therefore it is considered as a next-generation display technology with promising development.
  • Embodiments of the present disclosure provide a manufacturing method of a display substrate, a display substrate and a display device to at least partially improve threshold voltage characteristic of a TFT and improve product quality of the display device.
  • An embodiment of the present disclosure provides a manufacturing method of a display substrate, comprising manufacturing a top-gate type thin film transistor on a side of a base substrate, wherein the manufacturing the top-gate type thin film transistor on the side of the base substrate comprises following steps:
  • an orthographic projection of the gate electrode on the base substrate being located within a region of an orthographic projection of the developed photoresist film layer on the base substrate;
  • the exposing the photoresist film layer to the light comprises: without exposing a region of the photoresist film layer corresponding to the gate electrode to be formed, fully exposing a region corresponding to an etched region of the gate film layer to the light.
  • the gate insulation film layer is over-etched for an over-etching time of (20% ⁇ 30%)*t by the gaseous corrosion method, where t is a normal time period during which the gate insulation film layer is etched to a predetermined depth.
  • a gas atmosphere of the gaseous corrosion comprises carbon tetrafluoride (CF 4 ) at a flow rate of 2000 to 2500 Standard Cubic Centimeters per Minute (SCCM) and oxygen (O 2 ) at a flow rate of 200 to 650 SCCM.
  • SCCM Standard Cubic Centimeters per Minute
  • O 2 oxygen
  • an edge of the orthographic projection of the gate electrode on the base substrate is spaced apart from an edge of the orthographic projection of the developed photoresist film layer on the base substrate by 1 to 1.5 ⁇ m.
  • the manufacturing method before the step of forming the active layer, the manufacturing method further comprises:
  • the manufacturing method further comprises:
  • the manufacturing method further comprises:
  • first via hole and a second via hole communicated to the active layer which has been performed by the conductive treatment orthographic projections of the first via hole and the second via hole on the base substrate being respectively located at two sides of the orthographic projection of the gate electrode on the base substrate.
  • the manufacturing method further comprises:
  • a source electrode and a drain electrode on a side of the second insulation layer away from the base substrate, the source electrode and the drain electrode being connected to the active layer which has been performed by the conductive treatment respectively through the first via hole and the second via hole.
  • the manufacturing method further comprises:
  • the manufacturing method further comprises:
  • the fourth via hole, the first via hole and the second via hole are formed by one patterning process.
  • the manufacturing method further comprises:
  • the manufacturing method further comprises:
  • a source electrode and a drain electrode on a side of the second insulation layer away from the base substrate, the source electrode and the drain electrode being connected to the active layer which has been performed by the conductive treatment respectively through the first via hole and the second via hole.
  • the manufacturing method further comprises:
  • the manufacturing method further comprises:
  • An embodiment of the present disclosure further provides a display substrate manufactured by the manufacturing method of the display substrate according to any one of the foregoing embodiments.
  • An embodiment of the present disclosure further provides a display device, comprising the display substrate according to any one of the foregoing embodiments.
  • FIG. 1 is a flow chart of a manufacturing method of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic view showing a manufacturing process of a display substrate according to an embodiment of the present disclosure.
  • FIG. 3 is another schematic view showing a manufacturing process of a display substrate according to an embodiment of the present disclosure.
  • a Thin Film Transistor (TFT) on a display substrate of an OLED display device may be classified into two types, i.e., top-gate type and bottom-gate type.
  • the top-gate type TFT includes: a light shielding layer, a first insulation layer, an active layer, a gate insulation layer, a gate electrode, a second insulation layer, and a source and drain layer, which are sequentially disposed on a base substrate, and a source electrode is arranged opposite to a drain electrode in the source and drain layer.
  • the gate insulation layer needs to be partially etched so that the active layer under the gate insulation layer can be partially exposed, then the exposed portion of the active layer is subjected to a conductive treatment, and finally the source electrode and the drain electrode are connected to the treated active layer through via holes.
  • embodiments of the present disclosure provide a manufacturing method of a display substrate, a display substrate, and a display device.
  • a manufacturing method of a display substrate includes manufacturing a top-gate type thin film transistor on a side of a base substrate 100 , wherein the manufacturing the top-gate type thin film transistor on the side of the base substrate 100 comprises following steps:
  • a gate insulation film layer 20 forming a gate insulation film layer 20 , a gate film layer 30 and a photoresist film layer 40 sequentially on a side of the active layer 10 away from the base substrate 100 ;
  • the region of the photoresist film layer 40 corresponding to the gate electrode to be formed refers to a region directly above the gate electrode to be formed in the photoresist film layer 40
  • the region of the photoresist film layer 40 corresponding to the etched region of the gate film layer 30 refers to a region directly above the etched region of the gate film layer 30 in the photoresist film layer 40 ;
  • the slope angle of the photoresist film layer may be defined as an included angle between a side surface and a bottom surface of the photoresist film layer;
  • Over-etching may refer to an etching process in which the etching time is greater than a normal etching time, where the normal etching time refers to a time period that it takes for a film with a thickness of h to be etched to an etching depth of h;
  • a gaseous corrosion method to form a gate insulation layer 21 using the developed photoresist film layer 40 as a protection mask
  • a gas atmosphere of the gaseous corrosion comprises carbon tetrafluoride (CF 4 ) at a flow rate of 2000 to 2500 SCCM and oxygen (O 2 ) at a flow rate of 200 to 650 SCCM; where t is a normal time period during which the gate insulation film layer 20 is etched to a predetermined depth;
  • SCCM is a unit of volumetric flow, which means milliliter per minute under a standard condition.
  • the carbon tetrafluoride (CF 4 ) at the flow rate of 2000 to 2500 SCCM represents carbon tetrafluoride at a flow rate of 2000 to 2500 ml/min under the standard condition.
  • the oxygen (O 2 ) at the flow rate of 200 to 650 SCCM represents oxygen at a flow rate of 200 to 650 ml/min under the standard condition.
  • the specific material of the active layer 10 is not limited, and it may be selected from indium tin oxide (ITO) or IGZO with a thickness of 0.05 to 0.09 ⁇ m.
  • the specific material of the gate insulation layer 21 is not limited, and it may be selected from a silicon oxide material with a thickness of 0.1 to 0.2 ⁇ m.
  • the specific material of the gate electrode 31 is not limited, and it may be selected from copper or aluminum and other metal materials with a thickness of 0.4 to 0.6 ⁇ m.
  • the gate film layer 30 may be etched by a wet etching method. When the gate film layer 30 is made from a copper material, the etching solvent may be hydrogen peroxide; when the gate film layer 30 is made from an aluminum material, the etching solvent may be mixed acid.
  • a pre-bake process is required before exposing the photoresist film layer 40 to the light.
  • a post-bake process is omitted and a development process is directly performed. In this way, it facilitates obtaining the photoresist film layer 40 with the above ideal thickness and slope angle.
  • the purpose of over-etching the gate film layer 30 and the gate insulation film layer 20 is to prevent etching residue.
  • the thickness of the gate insulation film layer 20 is h
  • the normal time period during which the gate insulation film layer 20 is etched is a time period during which the etching depth reaches h.
  • a thin film transistor is formed on the base substrate 100 by using the manufacturing method provided by the embodiment of the present disclosure.
  • a photoresist film layer with a desired thickness and slope angle and by controlling the etching amount, a good morphology of the gate insulation layer 21 can be obtained without etching residue, thus the length of the channel region which is located under the gate insulation layer 21 will not be adversely affected when the active layer 10 is subsequently subjected to the conductive treatment, thereby improving the threshold voltage characteristic of the TFT and improving the product quality of the display device.
  • an edge of the orthographic projection of the gate electrode 31 on the base substrate 100 is spaced apart from an edge of the orthographic projection of the developed photoresist film layer 40 on the base substrate 100 by 1 to 1.5 ⁇ m.
  • the orthographic projection of the gate insulation layer 21 on the base substrate 100 can be located within a region of the orthographic projection of the developed photoresist film layer 40 on the base substrate 100 , and the edge of the side of the gate insulation layer 21 close to the gate electrode 31 exceeds the edge of the gate electrode 31 , so that a good morphology of gate insulation layer 21 can be obtained and the length of the channel region which is located under the gate insulation layer 21 will not be adversely affected, thereby improving the threshold voltage characteristic of the TFT.
  • the manufacturing method before the step of forming the active layer 10 , the manufacturing method further comprises:
  • first insulation layer 70 covering the light shielding layer 60 on a side of the light shielding layer 60 away from the base substrate 100 .
  • the specific material of the light shielding layer 60 is not limited, and it may be selected from a metal material such as molybdenum or molybdenum-niobium alloy, with a thickness of 0.15 ⁇ m.
  • the specific material of the first insulation layer 70 is not limited, and it may be selected from a silicon oxide material with a thickness of 0.3 to 0.5 ⁇ m.
  • the manufacturing method of the display substrate further comprises:
  • orthographic projections of the first via hole 81 and the second via hole 82 on the base substrate 100 are respectively located at two sides of an orthographic projection of the gate electrode 31 on the base substrate 100 ;
  • a source electrode 11 and a drain electrode 12 on a side of the second insulation layer 80 away from the base substrate 100 , the source electrode 11 and the drain electrode 12 being connected to the active layer 10 which has been performed by the conductive treatment respectively through the first via hole 81 and the second via hole 82 .
  • the specific material of the second insulation layer 80 is not limited, and it may be selected from a silicon oxide material with a thickness of 0.3 to 0.5 ⁇ m.
  • the specific materials of the source electrode 11 and the drain electrode 12 are not limited, and they may be selected from copper or aluminum and other metal materials with a thickness of 0.5 to 0.7 ⁇ m.
  • the manufacturing method of the display substrate further comprises:
  • an orthographic projection of the third via hole 83 on the base substrate 100 is spaced apart from an orthographic projection of the active layer 10 on the base substrate 100 ;
  • a fourth via hole 84 communicated to the light shielding layer 60 , an orthographic projection of the fourth via hole 84 on the base substrate 100 coinciding with the orthographic projection of the third via hole 83 on the base substrate 100 , and the light shielding layer 60 being connected to the source electrode 11 or the drain electrode 12 through the fourth via hole 84 and the third via hole 83 .
  • the light shielding layer 60 is generally made of metal, thus in the solution according to this embodiment, by connecting the light shielding layer 60 with the source electrode 11 or the drain electrode 12 , cross-over resistance between the layers is reduced, thereby improving the performance of the TFT.
  • the fourth via hole 84 , the first via hole 81 and the second via hole 82 are formed by one patterning process. That is to say, after the second insulation layer 80 is formed on the side of the gate electrode 31 away from the base substrate 100 , the third via hole 83 communicated to the first insulation layer 70 is formed by one patterning process, and then the fourth via hole 84 , the first via hole 81 and the second via hole 82 are simultaneously formed by one patterning process, which can greatly simplify the manufacturing process of the display substrate.
  • the manufacturing method further comprises:
  • a passivation layer 90 on a side of the source electrode 11 and the drain electrode 12 away from the base substrate 100 .
  • the specific material of the passivation layer 90 is not limited, and it may be selected from silicon oxide, a combination of silicon oxide and silicon nitride, with a thickness of 0.3 to 0.4 ⁇ m.
  • An embodiment of the present disclosure also provides a display substrate manufactured by the manufacturing method of the display substrate according to any one of the foregoing technical solutions.
  • the threshold voltage characteristic of the TFT of the display substrate is improved.
  • An embodiment of the present disclosure also provides a display device comprising the display substrate according to any one of the foregoing technical solutions. Since the threshold voltage characteristic of the TFT of the display substrate is improved, the display device also has better product quality.
  • the specific product type of the display device is not limited, and it may be, for example, a display, a display screen, a flat panel TV, or the like.

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