US20180323295A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
US20180323295A1
US20180323295A1 US16/031,493 US201816031493A US2018323295A1 US 20180323295 A1 US20180323295 A1 US 20180323295A1 US 201816031493 A US201816031493 A US 201816031493A US 2018323295 A1 US2018323295 A1 US 2018323295A1
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epitaxial substrate
substrate
semiconductor device
via hole
layer
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Jun'ichi OKAYASU
Yoshiaki Abe
Takuya OIZUMI
Takahiro Yashiro
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Advantest Corp
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Advantest Corp
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Publication of US20180323295A1 publication Critical patent/US20180323295A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02378—Silicon carbide
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
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    • H01L21/02458—Nitrides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04—Cleaning involving contact with liquid
    • B08B3/10—Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration
    • B08B3/12—Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration by sonic or ultrasonic vibrations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Definitions

  • the present invention relates to a semiconductor device.
  • FIG. 1 is a cross-sectional diagram showing a conventional nitride semiconductor device.
  • a semiconductor device 100 R includes an epitaxial substrate 102 , interlayer dielectrics 104 and 106 , and wiring layers 110 , 112 , and 114 .
  • the semiconductor device 100 R is provided with a HEMT (High Electron Mobility Transistor) 200 , a thin-film resistor 202 , a MIM (Metal-Insulator-Metal) capacitor 204 , a GND terminal (pad) 206 , and VSS wiring 208 in an integrated manner, which are configured as a high-frequency circuit (MMIC: Monolithic Microwave Integrated Circuit).
  • HEMT High Electron Mobility Transistor
  • MIM Metal-Insulator-Metal capacitor
  • a back-face metal layer 120 is formed on the back face of the epitaxial substrate 102 .
  • the wiring layer 110 to be grounded is coupled to the back-face metal layer 120 via a via hole (through hole) 122 .
  • a SiC substrate has high etching resistance.
  • an epitaxial substrate 102 having a thickness of 100 ⁇ m is etched, this involves an increase of the substrate temperature up to 300° C. to 400° C.
  • the interlayer dielectrics 104 and 106 there is a need to employ an inorganic material that is not readily damaged due to an increase in the substrate temperature, e.g., a SiN (silicon nitride) film.
  • such an interlayer dielectric is formed as a combination of an air-bridge structure and a SiN film.
  • Such a SiN film has a relatively high relative dielectric constant on the order of 7.0. This leads to a difficulty in high-frequency operation in a millimeter-wave region, which is a higher-frequency operation than that in a microwave region. In a case of employing such a SiN film, this leads to a difficulty in forming a multi-layer wiring structure.
  • the present invention has been made in order to solve such a problem. Accordingly, it is an exemplary purpose of an embodiment of the present invention to provide a semiconductor device that is capable of performing a high-speed operation.
  • An embodiment of the present invention relates to a semiconductor device.
  • the semiconductor device comprises: an epitaxial substrate comprising a SiC (silicon carbide) substrate and a GaN (gallium nitride) epitaxial layer formed on the SiC substrate; a multi-layer wiring structure formed on a front-face side of the epitaxial substrate, and comprising at least one metal wiring layer and an organic interlayer dielectric; a back-face metal layer formed on a back face of the epitaxial substrate; and at least one via hole formed in the epitaxial substrate, and structured to provide a connection between the multi-layer wiring structure and the back-face metal layer.
  • SiC silicon carbide
  • GaN gallium nitride
  • this arrangement provides high-frequency operation.
  • via hole etching for forming the via hole may be performed under a condition that does not involve degradation of the interlayer dielectric.
  • the etching rate may be set to 1 ⁇ m/min or less.
  • the cooling temperature applied to a wafer may be 0° C. or less in etching. This arrangement is capable of appropriately suppressing an increase in the substrate temperature in etching, thereby preventing degradation of the interlayer dielectric.
  • impurities that have adhered to the epitaxial substrate may be removed by ultrasonic cleaning. This allows a plated layer to be appropriately formed.
  • the ultrasonic cleaning may be performed in pure water.
  • this method is capable of appropriately removing impurities including NiF (nickel fluoride) as compared with washing using an acid or alkali agent.
  • the manufacturing method comprises: forming a transistor element on an epitaxial substrate comprising a SiC (silicon carbide) substrate and a GaN (gallium nitride) epitaxial layer formed on the SiC substrate; forming a multi-layer wiring structure comprising at least one metal wiring layer and an organic interlayer dielectric on a front side of the epitaxial substrate; grinding a back face of the epitaxial substrate; performing via hole etching for a back-face side of the epitaxial substrate under a condition that does not involve degradation of the organic interlayer dielectric; and plating the back face of the epitaxial substrate and a side wall of a via hole.
  • FIG. 1 is a cross-sectional diagram showing a conventional nitride semiconductor device
  • FIG. 2 is a cross-sectional diagram showing a semiconductor device according to an embodiment
  • FIG. 3A is a cross-sectional diagram showing a via hole formed after acid or alkali washing
  • FIG. 3B is a cross-sectional diagram showing a via hole formed after ultrasonic cleaning.
  • the state represented by the phrase “the member A is coupled to the member B” includes a state in which the member A is indirectly coupled to the member B via another member that does not affect the electric connection therebetween, in addition to a state in which they are physically and directly coupled.
  • the state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly coupled to the member C, or the member B is indirectly coupled to the member C via another member that does not affect the electric connection therebetween, in addition to a state in which they are directly coupled.
  • FIG. 2 is a cross-sectional diagram showing a semiconductor device 100 according to an embodiment.
  • the semiconductor device 100 is provided with a HEMT 200 , a thin-film resistor 202 , a capacitor 204 , a pad 206 , wiring 208 , and the like, in an integrated manner, which are configured as a MMIC.
  • the semiconductor device 100 is provided with an epitaxial substrate 102 , a multi-layer wiring structure 300 , a back-face metal layer 120 , and a via hole 122 .
  • the epitaxial substrate 102 includes a SiC (silicon carbide) substrate and a GaN (gallium nitride) epitaxial layer formed on the SiC substrate.
  • the multi-layer wiring structure 300 is formed on the front-face side of the epitaxial substrate 102 .
  • the multi-layer wiring structure 300 includes at least one metal wiring layer, i.e., metal wiring layers M 1 through M 4 , and organic interlayer dielectrics I 1 through I 3 .
  • the back-face metal layer 120 is formed on the back face of the epitaxial substrate 102 .
  • a so-called low-k material having a relative dielectric constant on the order of 2.5 to 3 can be employed, examples of which include polyimide, BCB (benzocyclobutene), fluorine-based resin, and the like. It should be noted that the number of layers of the multi-layer wiring structure 300 is not restricted in particular.
  • the multi-layer wiring structure 300 may include a protective layer 302 interposed between the interlayer dielectric I 1 and the metal wiring layer M 1 .
  • the protective layer 302 may be formed of SiN (silicon nitride), for example.
  • At least one via hole 122 is formed in the epitaxial substrate 102 . Each via hole 122 is configured to provide a connection between the multi-layer wiring structure 300 and the back-face metal layer 120 .
  • the interlayer dielectrics I 1 through I 3 are formed of a low-k material. This provides the semiconductor device 100 with high-speed operation. Furthermore, this allows the multi-layer wiring structure 300 to have a further increased number of wiring layers according to necessity as compared with conventional techniques employing SiN films.
  • the above is the basic structure of the semiconductor device 100 . Next, description will be made regarding a manufacturing method thereof.
  • a transistor element such as a HEMT 200 or the like is formed on the epitaxial substrate 102 .
  • the multi-layer wiring structure 300 is formed on the front side of the epitaxial substrate 102 . To this point, the manufacturing steps are the same as those in conventional techniques.
  • the back face of the epitaxial substrate is ground such that it has a substrate thickness of 100 ⁇ m.
  • via hole etching is applied to the back-face side of the epitaxial substrate 102 under a condition that does not degrade the organic interlayer dielectrics I 1 through I 3 .
  • the condition that does not degrade the organic interlayer dielectrics may be determined giving consideration to the temperature limit of the material of the organic interlayer dielectric I 1 through I 3 to be employed, or the like.
  • the present inventors have confirmed that, under a condition that the substrate temperature of the epitaxial substrate 102 is maintained at a reduced temperature of 300° C. or less, via hole opening formation can be performed without the occurrence of degradation (cracking, peeling, discoloration) in the interlayer dielectrics I 1 through I 3 . Also, the substrate temperature of the epitaxial substrate 102 may preferably be maintained at a further reduced temperature of 250° C. or less for added safety.
  • the typical etching rate is set to 1 ⁇ m/min or more.
  • the etching rate is preferably set to 1 ⁇ m/min or less.
  • the etching rate is preferably set to a value on the order of 0.5 ⁇ m/min to 1 ⁇ m/min. This appropriately suppresses heating-up of the epitaxial substrate 102 due to etching, thereby preventing each interlayer dielectric from having a temperature that is higher than the upper temperature limit thereof
  • the epitaxial substrate 102 is preferably subjected to thermal cooling to 0° C. or less (e.g., ⁇ 30° C. to 0° C.). This arrangement is capable of preventing each interlayer dielectric from having a temperature that is higher than the upper temperature limit.
  • the back face of the epitaxial substrate 102 and the side wall of the via hole 122 are plated (e.g., Au (gold) plated). This forms the back-face metal layer 120 and the via hole 122 .
  • the present inventors have found that, if impurities adhere to the back face of the epitaxial substrate 102 or the side wall of the via hole 122 before plating, this leads to the occurrence of defects in the plating.
  • the via hole etching is performed using a combination of SF6 which is a typical etching gas and a Ni (nickel) metal mask, this involves the occurrence of NiF (nickel fluoride), which adheres to the back face of the epitaxial substrate 102 or the side wall of the via hole 122 .
  • FIG. 3A is a cross-sectional view of the via hole 122 formed after the washing and removing processing using such an acid or alkali agent.
  • the impurities that have adhered to the epitaxial substrate 102 are removed and detached by ultrasonic cleaning.
  • the ultrasonic cleaning is performed in pure water at a temperature of 50° C. or more (100° C. or less).
  • FIG. 3B is a cross-sectional view of the via hole 122 formed after the ultrasonic cleaning.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US16/031,493 2016-02-29 2018-07-10 Semiconductor device and manufacturing method thereof Abandoned US20180323295A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2016-036774 2016-02-29
JP2016036774A JP2017157585A (ja) 2016-02-29 2016-02-29 半導体デバイスおよびその製造方法
PCT/JP2017/004207 WO2017150080A1 (ja) 2016-02-29 2017-02-06 半導体デバイスおよびその製造方法

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10847510B2 (en) * 2017-07-18 2020-11-24 Sang-hun Lee RF power device capable of monitoring temperature and RF characteristics at wafer level
US11652043B2 (en) 2020-04-29 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with backside via
US11699704B2 (en) * 2017-09-28 2023-07-11 Intel Corporation Monolithic integration of a thin film transistor over a complimentary transistor
US11769768B2 (en) 2020-06-01 2023-09-26 Wolfspeed, Inc. Methods for pillar connection on frontside and passive device integration on backside of die

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102021102235A1 (de) * 2020-04-29 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierter schaltkreis mit rückseitiger durchkontaktierung

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060226415A1 (en) * 2004-11-22 2006-10-12 Masaaki Nishijima Semiconductor integrated circuit device and vehicle-mounted radar system using the same
US20160087052A1 (en) * 2014-09-19 2016-03-24 Kabushiki Kaisha Toshiba Semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6563079B1 (en) * 1999-02-25 2003-05-13 Seiko Epson Corporation Method for machining work by laser beam
US6475889B1 (en) * 2000-04-11 2002-11-05 Cree, Inc. Method of forming vias in silicon carbide and resulting devices and circuits
JP2006173595A (ja) * 2004-11-22 2006-06-29 Matsushita Electric Ind Co Ltd 半導体集積回路装置及びそれを用いた車載レーダシステム
JP5117698B2 (ja) * 2006-09-27 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置
JP5888027B2 (ja) * 2012-03-14 2016-03-16 富士通株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060226415A1 (en) * 2004-11-22 2006-10-12 Masaaki Nishijima Semiconductor integrated circuit device and vehicle-mounted radar system using the same
US20160087052A1 (en) * 2014-09-19 2016-03-24 Kabushiki Kaisha Toshiba Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10847510B2 (en) * 2017-07-18 2020-11-24 Sang-hun Lee RF power device capable of monitoring temperature and RF characteristics at wafer level
US11699704B2 (en) * 2017-09-28 2023-07-11 Intel Corporation Monolithic integration of a thin film transistor over a complimentary transistor
US11652043B2 (en) 2020-04-29 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with backside via
US11769768B2 (en) 2020-06-01 2023-09-26 Wolfspeed, Inc. Methods for pillar connection on frontside and passive device integration on backside of die
US11842997B2 (en) 2020-06-01 2023-12-12 Wolfspeed, Inc. Methods for pillar connection on frontside and passive device integration on backside of die

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