US20180277535A1 - Normally off iii nitride transistor - Google Patents

Normally off iii nitride transistor Download PDF

Info

Publication number
US20180277535A1
US20180277535A1 US15/988,618 US201815988618A US2018277535A1 US 20180277535 A1 US20180277535 A1 US 20180277535A1 US 201815988618 A US201815988618 A US 201815988618A US 2018277535 A1 US2018277535 A1 US 2018277535A1
Authority
US
United States
Prior art keywords
layer
gate
forming
etch process
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US15/988,618
Other versions
US11011515B2 (en
Inventor
Qhalid Fareed
Naveen Tipirneni
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US15/988,618 priority Critical patent/US11011515B2/en
Publication of US20180277535A1 publication Critical patent/US20180277535A1/en
Priority to US17/234,385 priority patent/US20210242200A1/en
Application granted granted Critical
Publication of US11011515B2 publication Critical patent/US11011515B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30621—Vapour phase etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02241—III-V semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Definitions

  • This invention relates to the field of semiconductor devices. More particularly, this invention relates to III-N field effect transistors in semiconductor devices.
  • An enhancement mode gallium nitride field effect transistor includes a recessed gate extending into a stressor layer and barrier layer, and vertically separated from a low-doped gallium nitride (GaN) layer.
  • GaN gallium nitride
  • Forming the gate recess by etching to have a desired vertical separation from the low-doped GaN layer is problematic. Timed etching results in unacceptable variation in the separation from the low-doped GaN layer.
  • Forming the gate recess using etch-blocking layers produces defects in the barrier layer and/or the stressor layer.
  • a gate recess of the enhancement mode GaN FET extends through the cap layer and the stressor layer, but not through the barrier layer.
  • a gate dielectric layer is disposed in the gate recess and a gate is disposed on the gate dielectric layer.
  • the semiconductor device is formed by forming the barrier layer with a high temperature metal organic chemical vapor deposition (MOCVD) process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process.
  • MOCVD metal organic chemical vapor deposition
  • the gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
  • FIG. 1 is a cross section of an example semiconductor device.
  • FIG. 2A through FIG. 2I are cross sections of the semiconductor device of FIG. 1 depicted in successive stages of an example fabrication sequence.
  • FIG. 3A and FIG. 3B are cross sections of the semiconductor device of FIG. 1 depicted in an alternate process sequence for forming the gate recess.
  • a gate recess of the enhancement mode GaN FET extends through the cap layer and the stressor layer, but not through the barrier layer.
  • a gate dielectric layer is disposed in the gate recess and a gate is disposed on the gate dielectric layer.
  • the semiconductor device may also include a depletion mode GaN FET with a planar gate over the cap layer and stressor layer.
  • a gate dielectric layer and the planar gate of the depletion mode GaN FET may be formed concurrently with the gate dielectric layer and the gate of the enhancement mode GaN FET.
  • the semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process.
  • the gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
  • the stressor layer may be oxidized by an anodic oxidation process in the gate recess to facilitate removal by the second etch step.
  • III-N material is understood to refer to semiconductor materials in which group III elements, that is, aluminum, gallium and indium, and possibly boron, provide a portion of the atoms in the semiconductor material and nitrogen atoms provide the remainder of the atoms in the semiconductor material.
  • group III elements that is, aluminum, gallium and indium, and possibly boron
  • nitrogen atoms provide the remainder of the atoms in the semiconductor material.
  • III-N semiconductor materials are gallium nitride, boron gallium nitride, aluminum gallium nitride, indium nitride, and indium aluminum gallium nitride. Terms such as aluminum gallium nitride describing elemental compositions of materials do not imply a particular stoichiometry of the elements.
  • GaN FET is understood to refer to a field effect transistor which includes III-N semiconductor materials.
  • FIG. 1 is a cross section of an example semiconductor device.
  • the semiconductor device 100 includes an enhancement mode GaN FET 102 and a depletion mode GaN FET 104 .
  • the semiconductor device 100 includes a substrate 106 which may be a wafer of silicon or other semiconductor material.
  • a buffer layer 108 of III-N material is disposed over the substrate 106 .
  • the buffer layer 108 may include for example, 100 to 300 nanometers of aluminum nitride on the substrate 106 and 1 to 7 microns of graded layers of Al x Ga 1-x N which is aluminum rich at a bottom surface, on the aluminum nitride, and gallium rich at a top surface of the buffer layer ( 108 ).
  • An electrical isolation layer ( 110 ) is disposed on the buffer layer ( 108 ).
  • the electrical isolation layer ( 110 ) may be, for example, 300 to 2000 nanometers of semi-insulating gallium nitride.
  • the electrical isolation layer ( 110 ) may be, for example, semi-insulating to provide a desired level of electrical isolation between layers below the electrical isolation layer ( 110 ) and layers above the electrical isolation layer ( 110 ).
  • the electrical isolation layer ( 110 ) may be doped with n-type or p-type dopants to reduce undesired effects of charge trapping on current density in the semiconductor device ( 100 ).
  • a low-doped layer ( 112 ) is disposed on the electrical isolation layer ( 110 ).
  • the low-doped layer ( 112 ) may be, for example, 25 to 1000 nanometers of gallium nitride.
  • the low-doped layer ( 112 ) may be formed so as to minimize crystal defects which may have an adverse effect on electron mobility.
  • the method of formation of the low-doped layer ( 112 ) may result in the low-doped layer ( 112 ) being doped with carbon, iron or other dopant species, for example with a net doping density less than 10 17 cm ⁇ 3 .
  • a barrier layer 114 is disposed over the low-doped layer 112 .
  • the barrier layer 114 may be primarily aluminum gallium nitride, with less than 1 atomic percent indium.
  • the barrier layer 114 may have a stoichiometry of Al 0.10 Ga 0.90 N to Al 0.30 Ga 0.70 N, and a thickness of 1 nanometers to 5 nanometers.
  • a minimum thickness of the barrier layer 114 may be selected to provide ease and reproducibility of fabrication; a maximum thickness may be selected to provide a desired off-state current in the enhancement mode GaN FET 102 , where increasing the thickness of the barrier layer 114 increases the off-state current.
  • the thickness may depend on a stoichiometry of the barrier layer 114 .
  • an instance of the barrier layer 114 with a stoichiometry of Al 0.10 Ga 0.90 N to Al 0.30 Ga 0.70 N may have a thickness of 1.5 nanometers to 2.0 nanometers.
  • a stressor layer 116 is disposed over the barrier layer 114 .
  • the stressor layer 116 is primarily indium aluminum nitride, with a stoichiometry of In 0.05 Al 0.95 N to In 0.30 Al 0.70 N, and a thickness of 1 nanometers to 5 nanometers.
  • the stressor layer 116 may have a stoichiometry of In 0.16 Al 0.84 N to In 0.18 Al 0.82 N and a thickness of 3.5 nanometers to 4.5 nanometers, which may provide a desired balance between providing a desired charge density in a two-dimensional electron gas (2DEG), which decreases with indium content, and providing a desired etch selectivity to the underlying barrier layer 114 , which increases with indium content.
  • the stoichiometry of In 0.16 Al 0.84 N to In 0.18 Al 0.82 N may also provide a desired lattice match to the low-doped layer 112 .
  • a cap layer 118 is disposed over the stressor layer 116 .
  • the cap layer 118 has less than 1 atomic percent indium, and may be primarily aluminum gallium nitride.
  • a thickness of the cap layer is selected to prevent oxidation of the stressor layer 116 during subsequent fabrication steps.
  • An example cap layer 118 may have a stoichiometry of Al 0.05 Ga 0.95 N to Al 0.30 Ga 0.70 N, and a thickness of 4 nanometers to 20 nanometers. The cap layer 118 advantageously prevents oxidation of the indium in the stressor layer 116 .
  • a gate recess 120 extends through the cap layer 118 and the stressor layer 116 in the enhancement mode GaN FET 102 .
  • the gate recess 120 may extend completely through the stressor layer 116 and not extend into the barrier layer 114 , as depicted in FIG. 1 .
  • the gate recess 120 may extend partway into the barrier layer 114 , or may extend only partway through the stressor layer 116 and stop short of the barrier layer 114 .
  • An enhancement mode gate dielectric layer 122 is disposed in the gate recess 120 in the enhancement mode GaN FET 102 .
  • a depletion mode gate dielectric layer 124 is disposed over the cap layer in the depletion mode GaN FET 104 .
  • the enhancement mode gate dielectric layer 122 and the depletion mode gate dielectric layer 124 may be 5 nanometers to 50 nanometers thick and may include one or more layers of silicon dioxide, silicon nitride and/or aluminum oxide.
  • the enhancement mode gate dielectric layer 122 and the depletion mode gate dielectric layer 124 may have substantially equal thicknesses and compositions, possibly as a result of being formed concurrently.
  • the enhancement mode gate dielectric layer 122 and the depletion mode gate dielectric layer 124 may have different thicknesses and compositions, so as to separately optimize performance of the enhancement mode GaN FET 102 and the depletion mode GaN FET 104 .
  • a field plate dielectric layer 126 may optionally be disposed over the cap layer 118 and under the enhancement mode gate dielectric layer 122 adjacent to the gate recess 120 and under the depletion mode gate dielectric layer 124 adjacent to a gate area in the depletion mode GaN FET 104 .
  • the field plate dielectric layer 126 may include one or more layers of silicon dioxide and/or silicon nitride, and may be, for example, 10 nanometers to 100 nanometers thick. In an alternate version of the instant example, the field plate dielectric layer 126 may be disposed over the enhancement mode gate dielectric layer 122 and the depletion mode gate dielectric layer 124 .
  • An enhancement mode gate 128 is disposed over the enhancement mode gate dielectric layer 122 in the gate recess 120 .
  • the enhancement mode gate 128 may overlap the field plate dielectric layer 126 in the enhancement mode GaN FET 102 , as depicted in FIG. 1 .
  • a depletion mode gate 130 is disposed over the depletion mode gate dielectric layer 124 in the gate area of the depletion mode GaN FET 104 and may overlap the field plate dielectric layer 126 in the depletion mode GaN FET 104 , as depicted in FIG. 1 .
  • the enhancement mode gate 128 and the depletion mode gate 130 may have substantially equal compositions, possibly as a result of being formed concurrently.
  • Dielectric isolation structures 132 extend through the cap layer 118 , the stressor layer 116 and the barrier layer 114 and possibly through the low-doped layer ( 112 ), so as to laterally isolate the enhancement mode GaN FET ( 102 ) and the depletion mode GaN FET ( 104 ).
  • the dielectric isolation structures 132 may include, for example, silicon dioxide and/or silicon nitride.
  • a source contact 134 and a drain contact 136 provide electrical connections to a 2DEG in the enhancement mode GaN FET 102 .
  • a source contact 138 and a drain contact 140 provide electrical connections to a 2DEG in the depletion mode GaN FET 104 .
  • the barrier layer 114 advantageously provides a low carrier density in the 2DEG of the enhancement mode GaN FET 102 under the gate recess 120 , so as to provide a desired off-state current.
  • the stressor layer 116 advantageously provides a desired high carrier density in the 2DEG of the enhancement mode GaN FET 102 in the access regions between the gate recess 120 and the source contact 134 and the drain contact 136 , so as to provide a desired on-state current.
  • the configuration of the gate recess 120 extending through the stressor layer 116 advantageously contributes to the low carrier density in the 2DEG of the enhancement mode GaN FET 102 under the gate recess 120 .
  • the stressor layer 116 extending under the depletion mode gate 130 advantageously provides a desired on-state current in the depletion mode GaN FET 104 .
  • FIG. 2A through FIG. 2I are cross sections of the semiconductor device of FIG. 1 depicted in successive stages of an example fabrication sequence.
  • the buffer layer 108 is formed over the substrate 106 .
  • the electrical isolation layer ( 110 ) is formed over the buffer layer ( 108 ), and the low-doped layer ( 112 ) is formed over the electrical isolation layer ( 110 ).
  • the buffer layer 108 , the electrical isolation layer ( 110 ) and the low-doped layer ( 112 ) may be formed, for example, by a series of MOCVD processes.
  • the substrate 106 is a 150 millimeter substrate.
  • the substrate 106 is placed on a susceptor 142 , possibly of graphite, in an MOCVD chamber 144 .
  • the susceptor 142 is heated, for example by heating coils, to a temperature of 900° C. to 1100° C.
  • a carrier gas such as hydrogen (H 2 ) as indicated in FIG. 2A is flowed into the MOCVD chamber 144 at a flow rate of 80 standard liters per minute (slm) to 120 slm, and a nitrogen source such as ammonia (NH 3 ) as indicated in FIG.
  • TMAl trimethylaluminum
  • TMGa trimethylgallium
  • a pressure in the MOCVD chamber 144 is maintained at 50 torr to 200 torr.
  • the nitrogen source, the aluminum precursor and the gallium precursor react at the existing surface of the semiconductor device 100 to form the barrier layer 114 over the low-doped layer 112 in the areas for the enhancement mode GaN FET 102 and the depletion mode GaN FET 104 .
  • Forming the barrier layer 114 at a temperature of 900° C. to 1100° C. advantageously provides fewer defects and hence higher reliability for the semiconductor device 100 compared to a barrier layer formed at a lower temperature.
  • substantially no indium precursor is flowed into the MOCVD chamber 144 while the barrier layer 114 is formed.
  • the barrier layer 114 may include a quaternary III-N material, that is, may include another element in addition to aluminum, gallium and nitrogen.
  • the barrier layer 114 may be formed in situ after the low-doped layer ( 112 ) to advantageously reduce defects in the semiconductor device ( 100 ).
  • the substrate 106 remains on the susceptor 142 in the MOCVD chamber 144 .
  • the susceptor 142 is heated to a temperature of 700° C. to 850° C.
  • a carrier gas, indicated in FIG. 2B as nitrogen (N 2 ) is flowed into the MOCVD chamber 144 at a flow rate of 60 slm to 100 slm, and a nitrogen source, indicated in FIG. 2B as ammonia (NH 3 ), is flowed into the MOCVD chamber 144 at a flow rate of 5 slm to 40 slm.
  • TMAl trimethylaluminum
  • TMIn trimethylindium
  • a pressure in the MOCVD chamber 144 is maintained at 100 torr to 400 torr.
  • the nitrogen source, the aluminum precursor and the indium precursor react at the existing surface of the semiconductor device 100 to form the stressor layer 116 over the barrier layer 114 in the areas for the enhancement mode GaN FET 102 and the depletion mode GaN FET 104 .
  • Forming the stressor layer 116 at a minimum temperature of 700° C. may advantageously enable a desired concentration of indium and uniform distribution of indium in the stressor layer 116 compared to forming at a lower temperature.
  • Forming the stressor layer 116 at a maximum temperature 850° C. may advantageously reduce indium diffusion into the barrier layer 114 compared to forming at a higher temperature.
  • substantially no aluminum precursor is flowed into the MOCVD chamber 144 while the stressor layer 116 is formed.
  • the stressor layer 116 may include a quaternary III-N material. Forming the stressor layer 116 in situ with the barrier layer 114 may advantageously reduce defects in the semiconductor device ( 100 ).
  • the substrate 106 remains on the susceptor 142 in the MOCVD chamber 144 .
  • the susceptor 142 is heated to a temperature of 750° C. to 900° C.
  • a carrier gas, indicated in FIG. 2C as hydrogen (H 2 ) is flowed into the MOCVD chamber 144 at a flow rate of 80 slm to 120 slm, and a nitrogen source, indicated in FIG. 2C as ammonia (NH 3 ), is flowed into the MOCVD chamber 144 at a flow rate of 5 slm to 35 slm.
  • TMAl trimethylaluminum
  • MOCVD chamber 144 is flowed into the MOCVD chamber 144 at a rate of 80 sccm to 130 sccm and a gallium precursor, indicated in FIG. 2C as trimethylgallium (TMGa), is flowed into the MOCVD chamber 144 at a rate of 40 sccm to 60 sccm.
  • a pressure in the MOCVD chamber 144 is maintained at 50 torr to 200 torr.
  • the nitrogen source, the aluminum precursor and the gallium precursor react at the existing surface of the semiconductor device 100 to form the cap layer 118 over the stressor layer 116 in the areas for the enhancement mode GaN FET 102 and the depletion mode GaN FET 104 .
  • Forming the cap layer 118 at a maximum temperature of 900° C. may advantageously reduce indium diffusion into the barrier layer 114 and the cap layer 118 compared to forming at a higher temperature.
  • substantially no indium precursor is flowed into the MOCVD chamber 144 while the cap layer 118 is formed.
  • the cap layer 118 may be formed in situ after the stressor layer ( 116 ) to advantageously reduce defects in the semiconductor device ( 100 ).
  • the field plate dielectric layer 126 is formed over the cap layer 118 .
  • the field plate dielectric layer 126 may be formed, for example, by forming a layer of dielectric material containing silicon dioxide and/or silicon nitride over the cap layer by a plasma enhanced chemical vapor deposition (PECVD) process.
  • PECVD plasma enhanced chemical vapor deposition
  • a field plate mask 146 is formed over the layer of dielectric material so as to expose gate areas for the enhancement mode GaN FET 102 and the depletion mode GaN FET 104 .
  • the layer of dielectric material is removed where exposed by the field plate mask 146 by an etch process such as a plasma etch process at over 100 torr, forming the field plate dielectric layer 126 with sloped sides as depicted in FIG. 2D .
  • a recess mask 148 is formed over the cap layer 118 to expose an area in the enhancement mode GaN FET 102 for the gate recess 120 .
  • the recess mask 148 may include photoresist and may be formed by a photolithographic process.
  • the recess mask 148 may further include an antireflection layer such as an organic bottom antireflection coating (BARC) and/or a hard mask layer such as silicon dioxide or silicon nitride.
  • BARC organic bottom antireflection coating
  • the recess mask 148 covers the area for the depletion mode GaN FET 104 .
  • a first etch process 150 such as a plasma etch process using chlorine radicals removes the cap layer 118 in the area exposed by the recess mask 148 to form a portion of the gate recess 120 .
  • the indium in the stressor layer 116 has a lower etch rate in the first etch process 150 than the cap layer 118 , so at least a portion of the stressor layer 116 remains in the area for the gate recess 120 after the first etch process 150 is completed.
  • the first etch process 150 may be, for example, an inductively-coupled plasma reactive ion etch (ICP-RIE) process using chlorine (Cl 2 ) gas sulfur hexafluoride (SF 6 ) gas, which has been demonstrated to desirably provide an etch selectivity of gallium aluminum nitride to indium aluminum nitride greater than 1.0.
  • ICP-RIE inductively-coupled plasma reactive ion etch
  • SF 6 sulfur hexafluoride
  • a second etch process 152 removes the stressor layer 116 in the gate recess 120 to form the complete gate recess 120 .
  • the second etch process 152 has a different chemistry than the first etch process 150 of FIG. 2E .
  • the barrier layer 114 has a lower etch rate in the second etch process 152 than the stressor layer 116 , so at least a portion, and possibly all, of the barrier layer 114 remains under the gate recess 120 after the second etch process 152 is completed.
  • the second etch process 152 may include, for example, a wet etch process using a 1 molar aqueous solution of 1,2 diaminoethane, which has been demonstrated to desirable provide an etch selectivity of indium aluminum nitride to gallium aluminum nitride eater than 1.0 at room temperature.
  • the first etch process 150 may provide a desirably rough surface on the exposed stressor layer 116 which may advantageously provide a more uniform initial etch rate for the second etch process 152 .
  • a remaining portion 154 of the stressor layer 116 in the gate recess 120 may be a transition layer 154 which includes elements of the underlying barrier layer 114 .
  • An oxidizing liquid 156 oxidizes the remaining portion 154 of the stressor layer 116 in the gate recess 120 .
  • the remaining portion 154 of the stressor layer 116 may be oxidized by an anodic oxidation process in which electrical current is passed through the oxidizing liquid 156 .
  • the oxidizing liquid 156 may be an aqueous solution of nitriloacetic acid and 0.3 molar potassium hydroxide (KOH) with a pH value of 8.5.
  • the electrical current may have a value of about 20 microamperes per square centimeter of exposed stressor layer 116 .
  • the oxidized remaining portion 154 may be subsequently removed, for example by a wet etch process using a dilute aqueous acidic solution, such as a dilute nitric acid solution or a citric acid solution.
  • the recess mask 148 is removed, possibly after the wet etch process 152 of FIG. 2F is completed, or possibly earlier.
  • a layer of gate dielectric material 158 is formed over the field plate dielectric layer 126 , extending into the gate recess 120 and overlying the barrier layer 114 at a bottom of the gate recess 120 .
  • the layer of gate dielectric material 158 extends over the cap layer 118 in the depletion mode GaN FET 104 .
  • the layer of gate dielectric material 158 may include one or more layers of silicon dioxide and/or silicon nitride, formed, for example, by PECVD processes.
  • a layer of gate material 160 is formed over the layer of gate dielectric material 158 .
  • the layer of gate material 160 may include, for example, gallium nitride or other III-N material, or may include polycrystalline silicon, referred to as polysilicon, or may include metal.
  • the layer of gate material 160 is formed in the areas for the gates of both the enhancement mode GaN FET 102 and the depletion mode GaN FET 104 .
  • the layer of gate material 160 of FIG. 2H is patterned to concurrently form the enhancement mode gate 128 and the depletion mode gate 130 .
  • the enhancement mode gate 128 and the depletion mode gate 130 may be formed by an etch process: forming an etch mask over the layer of gate material 160 which covers area for the enhancement mode gate 128 and the depletion mode gate 130 , and subsequently removing the layer of gate material 160 where exposed by the etch mask.
  • the enhancement mode gate 128 and the depletion mode gate 130 may be formed by a liftoff process: forming a liftoff mask of solvent-soluble organic material such as photoresist which exposes the layer of gate dielectric material 158 in the areas for the enhancement mode gate 128 and the depletion mode gate 130 , forming the layer of gate material 160 over the liftoff mask, and subsequently removing the liftoff mask and the overlying layer of gate material 160 , leaving the layer of gate material 160 in the areas exposed by the liftoff mask to provide the enhancement mode gate 128 and the depletion mode gate 130 .
  • Forming the enhancement mode gate 128 and the depletion mode gate 130 concurrently may advantageously reduce fabrication cost and complexity of the semiconductor device 100 .
  • the enhancement mode gate 128 and the depletion mode gate 130 may be formed separately, of materials with different work functions, to increase performance of both the enhancement mode GaN FET 102 and the depletion mode GaN FET 104 .
  • fabrication is continued to provide the structure of FIG. 1 .
  • FIG. 3A and FIG. 3B are cross sections of the semiconductor device of FIG. 1 depicted in an alternate process sequence for forming the gate recess.
  • the recess mask 148 is formed over the cap layer 118 .
  • the cap layer 118 is removed in the area exposed by the recess mask 148 to form a portion of the gate recess 120 , as described in reference to FIG. 2E .
  • An oxidizing liquid 162 for example an anodizing aqueous solution containing an aqueous solution of nitriloacetic acid and 0.3 molar KOH with a pH value of 8.5 with an electrical current of about 20 microamperes per square centimeter of exposed stressor layer 116 , oxidizes the stressor layer 116 where exposed by the cap layer 118 in the gate recess 120 to form an oxidized stressor layer 164 which includes indium oxide.
  • the barrier layer 114 may include a layer of gallium nitride (GaN) 1 nanometer to 3 nanometers thick immediately below the stressor layer 116 to prevent oxidation of the aluminum gallium nitride in the barrier layer 114 . At least a portion of the barrier layer 114 under the stressor layer 116 in the gate recess 120 is not oxidized.
  • a second etch process 166 removes the oxidized stressor layer 164 of FIG. 3A to form the gate recess 120 , while leaving at least a portion, and possibly all, of the barrier layer 114 under the gate recess 120 .
  • the second etch process 166 may include, for example, a dilute aqueous solution of nitric acid, phosphoric acid, and/or hydrochloric acid, or an aqueous solution of an organic acid such as citric acid.
  • the oxidation process described in reference to FIG. 3A and the second etch process of FIG. 3B may be repeated to completely remove the stressor layer 116 from the gate recess 120 .
  • the recess mask 148 is removed and fabrication is continued as described in reference to FIG. 2G .

Abstract

A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. Nonprovisional patent application Ser. No. 14/673,844, filed Mar. 30, 2015, the contents of which is herein incorporated by reference in its entirety.
    • FIELD OF THE INVENTION
  • This invention relates to the field of semiconductor devices. More particularly, this invention relates to III-N field effect transistors in semiconductor devices.
    • BACKGROUND OF THE INVENTION
  • An enhancement mode gallium nitride field effect transistor (GaN FET) includes a recessed gate extending into a stressor layer and barrier layer, and vertically separated from a low-doped gallium nitride (GaN) layer. Forming the gate recess by etching to have a desired vertical separation from the low-doped GaN layer is problematic. Timed etching results in unacceptable variation in the separation from the low-doped GaN layer. Forming the gate recess using etch-blocking layers produces defects in the barrier layer and/or the stressor layer.
    • SUMMARY OF THE INVENTION
  • The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to a more detailed description that is presented later.
  • A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack including a low-doped GaN layer, a barrier layer including aluminum disposed over the low-doped GaN layer, a stressor layer including indium disposed over the barrier layer, and a cap layer including aluminum disposed over the stressor layer. A gate recess of the enhancement mode GaN FET extends through the cap layer and the stressor layer, but not through the barrier layer. A gate dielectric layer is disposed in the gate recess and a gate is disposed on the gate dielectric layer.
  • The semiconductor device is formed by forming the barrier layer with a high temperature metal organic chemical vapor deposition (MOCVD) process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.
    • DESCRIPTION OF THE VIEWS OF THE DRAWING
  • FIG. 1 is a cross section of an example semiconductor device.
  • FIG. 2A through FIG. 2I are cross sections of the semiconductor device of FIG. 1 depicted in successive stages of an example fabrication sequence.
  • FIG. 3A and FIG. 3B are cross sections of the semiconductor device of FIG. 1 depicted in an alternate process sequence for forming the gate recess.
    •  DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
  • The present invention is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the invention. Several aspects of the invention are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details or with other methods. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. The present invention is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present invention.
  • A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack including a low-doped GaN layer, a barrier layer including aluminum disposed over the low-doped GaN layer, a stressor layer including indium disposed over the barrier layer, and a cap layer including aluminum disposed over the stressor layer. A gate recess of the enhancement mode GaN FET extends through the cap layer and the stressor layer, but not through the barrier layer. A gate dielectric layer is disposed in the gate recess and a gate is disposed on the gate dielectric layer.
  • The semiconductor device may also include a depletion mode GaN FET with a planar gate over the cap layer and stressor layer. A gate dielectric layer and the planar gate of the depletion mode GaN FET may be formed concurrently with the gate dielectric layer and the gate of the enhancement mode GaN FET.
  • The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer. The stressor layer may be oxidized by an anodic oxidation process in the gate recess to facilitate removal by the second etch step.
  • For the purposes of this description, the term “III-N material” is understood to refer to semiconductor materials in which group III elements, that is, aluminum, gallium and indium, and possibly boron, provide a portion of the atoms in the semiconductor material and nitrogen atoms provide the remainder of the atoms in the semiconductor material. Examples of III-N semiconductor materials are gallium nitride, boron gallium nitride, aluminum gallium nitride, indium nitride, and indium aluminum gallium nitride. Terms such as aluminum gallium nitride describing elemental compositions of materials do not imply a particular stoichiometry of the elements. For the purposes of this description, the term GaN FET is understood to refer to a field effect transistor which includes III-N semiconductor materials.
  • FIG. 1 is a cross section of an example semiconductor device. The semiconductor device 100 includes an enhancement mode GaN FET 102 and a depletion mode GaN FET 104. The semiconductor device 100 includes a substrate 106 which may be a wafer of silicon or other semiconductor material. A buffer layer 108 of III-N material is disposed over the substrate 106. The buffer layer 108 may include for example, 100 to 300 nanometers of aluminum nitride on the substrate 106 and 1 to 7 microns of graded layers of AlxGa1-xN which is aluminum rich at a bottom surface, on the aluminum nitride, and gallium rich at a top surface of the buffer layer (108). An electrical isolation layer (110) is disposed on the buffer layer (108). The electrical isolation layer (110) may be, for example, 300 to 2000 nanometers of semi-insulating gallium nitride. The electrical isolation layer (110) may be, for example, semi-insulating to provide a desired level of electrical isolation between layers below the electrical isolation layer (110) and layers above the electrical isolation layer (110). Alternatively, the electrical isolation layer (110) may be doped with n-type or p-type dopants to reduce undesired effects of charge trapping on current density in the semiconductor device (100). A low-doped layer (112) is disposed on the electrical isolation layer (110). The low-doped layer (112) may be, for example, 25 to 1000 nanometers of gallium nitride. The low-doped layer (112) may be formed so as to minimize crystal defects which may have an adverse effect on electron mobility. The method of formation of the low-doped layer (112) may result in the low-doped layer (112) being doped with carbon, iron or other dopant species, for example with a net doping density less than 1017 cm−3.
  • A barrier layer 114 is disposed over the low-doped layer 112. The barrier layer 114 may be primarily aluminum gallium nitride, with less than 1 atomic percent indium. The barrier layer 114 may have a stoichiometry of Al0.10Ga0.90N to Al0.30Ga0.70N, and a thickness of 1 nanometers to 5 nanometers. A minimum thickness of the barrier layer 114 may be selected to provide ease and reproducibility of fabrication; a maximum thickness may be selected to provide a desired off-state current in the enhancement mode GaN FET 102, where increasing the thickness of the barrier layer 114 increases the off-state current. The thickness may depend on a stoichiometry of the barrier layer 114. For example, an instance of the barrier layer 114 with a stoichiometry of Al0.10Ga0.90N to Al0.30Ga0.70N may have a thickness of 1.5 nanometers to 2.0 nanometers.
  • A stressor layer 116 is disposed over the barrier layer 114. The stressor layer 116 is primarily indium aluminum nitride, with a stoichiometry of In0.05Al0.95N to In0.30Al0.70N, and a thickness of 1 nanometers to 5 nanometers. In one version of the instant example, the stressor layer 116 may have a stoichiometry of In0.16Al0.84N to In0.18Al0.82N and a thickness of 3.5 nanometers to 4.5 nanometers, which may provide a desired balance between providing a desired charge density in a two-dimensional electron gas (2DEG), which decreases with indium content, and providing a desired etch selectivity to the underlying barrier layer 114, which increases with indium content. The stoichiometry of In0.16Al0.84N to In0.18Al0.82N may also provide a desired lattice match to the low-doped layer 112.
  • A cap layer 118 is disposed over the stressor layer 116. The cap layer 118 has less than 1 atomic percent indium, and may be primarily aluminum gallium nitride. A thickness of the cap layer is selected to prevent oxidation of the stressor layer 116 during subsequent fabrication steps. An example cap layer 118 may have a stoichiometry of Al0.05Ga0.95N to Al0.30Ga0.70N, and a thickness of 4 nanometers to 20 nanometers. The cap layer 118 advantageously prevents oxidation of the indium in the stressor layer 116.
  • A gate recess 120 extends through the cap layer 118 and the stressor layer 116 in the enhancement mode GaN FET 102. The gate recess 120 may extend completely through the stressor layer 116 and not extend into the barrier layer 114, as depicted in FIG. 1. Alternatively, the gate recess 120 may extend partway into the barrier layer 114, or may extend only partway through the stressor layer 116 and stop short of the barrier layer 114.
  • An enhancement mode gate dielectric layer 122 is disposed in the gate recess 120 in the enhancement mode GaN FET 102. A depletion mode gate dielectric layer 124 is disposed over the cap layer in the depletion mode GaN FET 104. The enhancement mode gate dielectric layer 122 and the depletion mode gate dielectric layer 124 may be 5 nanometers to 50 nanometers thick and may include one or more layers of silicon dioxide, silicon nitride and/or aluminum oxide. In one version of the instant example, the enhancement mode gate dielectric layer 122 and the depletion mode gate dielectric layer 124 may have substantially equal thicknesses and compositions, possibly as a result of being formed concurrently. In an alternate version, the enhancement mode gate dielectric layer 122 and the depletion mode gate dielectric layer 124 may have different thicknesses and compositions, so as to separately optimize performance of the enhancement mode GaN FET 102 and the depletion mode GaN FET 104.
  • A field plate dielectric layer 126 may optionally be disposed over the cap layer 118 and under the enhancement mode gate dielectric layer 122 adjacent to the gate recess 120 and under the depletion mode gate dielectric layer 124 adjacent to a gate area in the depletion mode GaN FET 104. The field plate dielectric layer 126 may include one or more layers of silicon dioxide and/or silicon nitride, and may be, for example, 10 nanometers to 100 nanometers thick. In an alternate version of the instant example, the field plate dielectric layer 126 may be disposed over the enhancement mode gate dielectric layer 122 and the depletion mode gate dielectric layer 124.
  • An enhancement mode gate 128 is disposed over the enhancement mode gate dielectric layer 122 in the gate recess 120. The enhancement mode gate 128 may overlap the field plate dielectric layer 126 in the enhancement mode GaN FET 102, as depicted in FIG. 1. A depletion mode gate 130 is disposed over the depletion mode gate dielectric layer 124 in the gate area of the depletion mode GaN FET 104 and may overlap the field plate dielectric layer 126 in the depletion mode GaN FET 104, as depicted in FIG. 1. The enhancement mode gate 128 and the depletion mode gate 130 may have substantially equal compositions, possibly as a result of being formed concurrently.
  • Dielectric isolation structures 132 extend through the cap layer 118, the stressor layer 116 and the barrier layer 114 and possibly through the low-doped layer (112), so as to laterally isolate the enhancement mode GaN FET (102) and the depletion mode GaN FET (104). The dielectric isolation structures 132 may include, for example, silicon dioxide and/or silicon nitride.
  • A source contact 134 and a drain contact 136 provide electrical connections to a 2DEG in the enhancement mode GaN FET 102. A source contact 138 and a drain contact 140 provide electrical connections to a 2DEG in the depletion mode GaN FET 104.
  • During operation of the semiconductor device 100, the barrier layer 114 advantageously provides a low carrier density in the 2DEG of the enhancement mode GaN FET 102 under the gate recess 120, so as to provide a desired off-state current. The stressor layer 116 advantageously provides a desired high carrier density in the 2DEG of the enhancement mode GaN FET 102 in the access regions between the gate recess 120 and the source contact 134 and the drain contact 136, so as to provide a desired on-state current. The configuration of the gate recess 120 extending through the stressor layer 116 advantageously contributes to the low carrier density in the 2DEG of the enhancement mode GaN FET 102 under the gate recess 120. The stressor layer 116 extending under the depletion mode gate 130 advantageously provides a desired on-state current in the depletion mode GaN FET 104.
  • FIG. 2A through FIG. 2I are cross sections of the semiconductor device of FIG. 1 depicted in successive stages of an example fabrication sequence. Referring to FIG. 2A, the buffer layer 108 is formed over the substrate 106. The electrical isolation layer (110) is formed over the buffer layer (108), and the low-doped layer (112) is formed over the electrical isolation layer (110). The buffer layer 108, the electrical isolation layer (110) and the low-doped layer (112) may be formed, for example, by a series of MOCVD processes.
  • In the instant example, process parameters will be described for a case wherein the substrate 106 is a 150 millimeter substrate. The substrate 106 is placed on a susceptor 142, possibly of graphite, in an MOCVD chamber 144. The susceptor 142 is heated, for example by heating coils, to a temperature of 900° C. to 1100° C. A carrier gas such as hydrogen (H2) as indicated in FIG. 2A is flowed into the MOCVD chamber 144 at a flow rate of 80 standard liters per minute (slm) to 120 slm, and a nitrogen source such as ammonia (NH3) as indicated in FIG. 2A is flowed into the MOCVD chamber 144 at a flow rate of 5 slm to 30 slm. An aluminum precursor such as trimethylaluminum (TMAl) as indicated in FIG. 2A, or triethylaluminum, is flowed into the MOCVD chamber 144 at a rate of 80 standard cubic centimeters per minute (sccm) to 130 sccm and a gallium precursor such as trimethylgallium (TMGa) as indicated in FIG. 2A, or triethylgallium, is flowed into the MOCVD chamber 144 at a rate of 40 sccm to 60 sccm. A pressure in the MOCVD chamber 144 is maintained at 50 torr to 200 torr. The nitrogen source, the aluminum precursor and the gallium precursor react at the existing surface of the semiconductor device 100 to form the barrier layer 114 over the low-doped layer 112 in the areas for the enhancement mode GaN FET 102 and the depletion mode GaN FET 104. Forming the barrier layer 114 at a temperature of 900° C. to 1100° C. advantageously provides fewer defects and hence higher reliability for the semiconductor device 100 compared to a barrier layer formed at a lower temperature. In the instant example, substantially no indium precursor is flowed into the MOCVD chamber 144 while the barrier layer 114 is formed. In an alternate version of the instant example, the barrier layer 114 may include a quaternary III-N material, that is, may include another element in addition to aluminum, gallium and nitrogen. The barrier layer 114 may be formed in situ after the low-doped layer (112) to advantageously reduce defects in the semiconductor device (100).
  • Referring to FIG. 2B, the substrate 106 remains on the susceptor 142 in the MOCVD chamber 144. The susceptor 142 is heated to a temperature of 700° C. to 850° C. A carrier gas, indicated in FIG. 2B as nitrogen (N2), is flowed into the MOCVD chamber 144 at a flow rate of 60 slm to 100 slm, and a nitrogen source, indicated in FIG. 2B as ammonia (NH3), is flowed into the MOCVD chamber 144 at a flow rate of 5 slm to 40 slm. An aluminum precursor, indicated in FIG. 2B as trimethylaluminum (TMAl), is flowed into the MOCVD chamber 144 at a rate of 80 sccm to 130 sccm and an indium precursor such as trimethylindium (TMIn) as indicated in FIG. 2B, or triethylindium, is flowed into the MOCVD chamber 144 at a rate of 100 sccm to 300 sccm. A pressure in the MOCVD chamber 144 is maintained at 100 torr to 400 torr. The nitrogen source, the aluminum precursor and the indium precursor react at the existing surface of the semiconductor device 100 to form the stressor layer 116 over the barrier layer 114 in the areas for the enhancement mode GaN FET 102 and the depletion mode GaN FET 104. Forming the stressor layer 116 at a minimum temperature of 700° C. may advantageously enable a desired concentration of indium and uniform distribution of indium in the stressor layer 116 compared to forming at a lower temperature. Forming the stressor layer 116 at a maximum temperature 850° C. may advantageously reduce indium diffusion into the barrier layer 114 compared to forming at a higher temperature. In the instant example, substantially no aluminum precursor is flowed into the MOCVD chamber 144 while the stressor layer 116 is formed. In an alternate version of the instant example, the stressor layer 116 may include a quaternary III-N material. Forming the stressor layer 116 in situ with the barrier layer 114 may advantageously reduce defects in the semiconductor device (100).
  • Referring to FIG. 2C, the substrate 106 remains on the susceptor 142 in the MOCVD chamber 144. The susceptor 142 is heated to a temperature of 750° C. to 900° C. A carrier gas, indicated in FIG. 2C as hydrogen (H2), is flowed into the MOCVD chamber 144 at a flow rate of 80 slm to 120 slm, and a nitrogen source, indicated in FIG. 2C as ammonia (NH3), is flowed into the MOCVD chamber 144 at a flow rate of 5 slm to 35 slm. An aluminum precursor, indicated in FIG. 2C as trimethylaluminum (TMAl), is flowed into the MOCVD chamber 144 at a rate of 80 sccm to 130 sccm and a gallium precursor, indicated in FIG. 2C as trimethylgallium (TMGa), is flowed into the MOCVD chamber 144 at a rate of 40 sccm to 60 sccm. A pressure in the MOCVD chamber 144 is maintained at 50 torr to 200 torr. The nitrogen source, the aluminum precursor and the gallium precursor react at the existing surface of the semiconductor device 100 to form the cap layer 118 over the stressor layer 116 in the areas for the enhancement mode GaN FET 102 and the depletion mode GaN FET 104. Forming the cap layer 118 at a maximum temperature of 900° C. may advantageously reduce indium diffusion into the barrier layer 114 and the cap layer 118 compared to forming at a higher temperature. In the instant example, substantially no indium precursor is flowed into the MOCVD chamber 144 while the cap layer 118 is formed. The cap layer 118 may be formed in situ after the stressor layer (116) to advantageously reduce defects in the semiconductor device (100).
  • Referring to FIG. 2D, the field plate dielectric layer 126 is formed over the cap layer 118. The field plate dielectric layer 126 may be formed, for example, by forming a layer of dielectric material containing silicon dioxide and/or silicon nitride over the cap layer by a plasma enhanced chemical vapor deposition (PECVD) process. A field plate mask 146 is formed over the layer of dielectric material so as to expose gate areas for the enhancement mode GaN FET 102 and the depletion mode GaN FET 104. The layer of dielectric material is removed where exposed by the field plate mask 146 by an etch process such as a plasma etch process at over 100 torr, forming the field plate dielectric layer 126 with sloped sides as depicted in FIG. 2D.
  • Referring to FIG. 2E, a recess mask 148 is formed over the cap layer 118 to expose an area in the enhancement mode GaN FET 102 for the gate recess 120. The recess mask 148 may include photoresist and may be formed by a photolithographic process. The recess mask 148 may further include an antireflection layer such as an organic bottom antireflection coating (BARC) and/or a hard mask layer such as silicon dioxide or silicon nitride. The recess mask 148 covers the area for the depletion mode GaN FET 104.
  • A first etch process 150 such as a plasma etch process using chlorine radicals removes the cap layer 118 in the area exposed by the recess mask 148 to form a portion of the gate recess 120. The indium in the stressor layer 116 has a lower etch rate in the first etch process 150 than the cap layer 118, so at least a portion of the stressor layer 116 remains in the area for the gate recess 120 after the first etch process 150 is completed. The first etch process 150 may be, for example, an inductively-coupled plasma reactive ion etch (ICP-RIE) process using chlorine (Cl2) gas sulfur hexafluoride (SF6) gas, which has been demonstrated to desirably provide an etch selectivity of gallium aluminum nitride to indium aluminum nitride greater than 1.0. Forming the cap layer 118 at a maximum temperature of 900° C., in combination with the indium content in the stressor layer 116, may advantageously increase the etch selectivity for the first etch process 150 so as to reduce the amount, if any, of the stressor layer 116 removed by the first etch process 150.
  • Referring to FIG. 2F, a second etch process 152 removes the stressor layer 116 in the gate recess 120 to form the complete gate recess 120. The second etch process 152 has a different chemistry than the first etch process 150 of FIG. 2E. The barrier layer 114 has a lower etch rate in the second etch process 152 than the stressor layer 116, so at least a portion, and possibly all, of the barrier layer 114 remains under the gate recess 120 after the second etch process 152 is completed. The second etch process 152 may include, for example, a wet etch process using a 1 molar aqueous solution of 1,2 diaminoethane, which has been demonstrated to desirable provide an etch selectivity of indium aluminum nitride to gallium aluminum nitride eater than 1.0 at room temperature. The first etch process 150 may provide a desirably rough surface on the exposed stressor layer 116 which may advantageously provide a more uniform initial etch rate for the second etch process 152.
  • Referring to FIG. 2G, there may be a remaining portion 154 of the stressor layer 116 in the gate recess 120, possibly a transition layer 154 which includes elements of the underlying barrier layer 114. An oxidizing liquid 156 oxidizes the remaining portion 154 of the stressor layer 116 in the gate recess 120. The remaining portion 154 of the stressor layer 116 may be oxidized by an anodic oxidation process in which electrical current is passed through the oxidizing liquid 156. For example, the oxidizing liquid 156 may be an aqueous solution of nitriloacetic acid and 0.3 molar potassium hydroxide (KOH) with a pH value of 8.5. The electrical current may have a value of about 20 microamperes per square centimeter of exposed stressor layer 116. The oxidized remaining portion 154 may be subsequently removed, for example by a wet etch process using a dilute aqueous acidic solution, such as a dilute nitric acid solution or a citric acid solution. The recess mask 148 is removed, possibly after the wet etch process 152 of FIG. 2F is completed, or possibly earlier.
  • Referring to FIG. 2H, a layer of gate dielectric material 158 is formed over the field plate dielectric layer 126, extending into the gate recess 120 and overlying the barrier layer 114 at a bottom of the gate recess 120. In the instant example, the layer of gate dielectric material 158 extends over the cap layer 118 in the depletion mode GaN FET 104. The layer of gate dielectric material 158 may include one or more layers of silicon dioxide and/or silicon nitride, formed, for example, by PECVD processes. A layer of gate material 160 is formed over the layer of gate dielectric material 158. The layer of gate material 160 may include, for example, gallium nitride or other III-N material, or may include polycrystalline silicon, referred to as polysilicon, or may include metal. In the instant example, the layer of gate material 160 is formed in the areas for the gates of both the enhancement mode GaN FET 102 and the depletion mode GaN FET 104.
  • Referring to FIG. 2I, the layer of gate material 160 of FIG. 2H is patterned to concurrently form the enhancement mode gate 128 and the depletion mode gate 130. The enhancement mode gate 128 and the depletion mode gate 130 may be formed by an etch process: forming an etch mask over the layer of gate material 160 which covers area for the enhancement mode gate 128 and the depletion mode gate 130, and subsequently removing the layer of gate material 160 where exposed by the etch mask. Alternatively, the enhancement mode gate 128 and the depletion mode gate 130 may be formed by a liftoff process: forming a liftoff mask of solvent-soluble organic material such as photoresist which exposes the layer of gate dielectric material 158 in the areas for the enhancement mode gate 128 and the depletion mode gate 130, forming the layer of gate material 160 over the liftoff mask, and subsequently removing the liftoff mask and the overlying layer of gate material 160, leaving the layer of gate material 160 in the areas exposed by the liftoff mask to provide the enhancement mode gate 128 and the depletion mode gate 130. Forming the enhancement mode gate 128 and the depletion mode gate 130 concurrently may advantageously reduce fabrication cost and complexity of the semiconductor device 100. In an alternate version of the instant example, the enhancement mode gate 128 and the depletion mode gate 130 may be formed separately, of materials with different work functions, to increase performance of both the enhancement mode GaN FET 102 and the depletion mode GaN FET 104. After forming the enhancement mode GaN FET 102 and the depletion mode GaN FET 104, fabrication is continued to provide the structure of FIG. 1.
  • FIG. 3A and FIG. 3B are cross sections of the semiconductor device of FIG. 1 depicted in an alternate process sequence for forming the gate recess. Referring to FIG. 3A, the recess mask 148 is formed over the cap layer 118. The cap layer 118 is removed in the area exposed by the recess mask 148 to form a portion of the gate recess 120, as described in reference to FIG. 2E. An oxidizing liquid 162, for example an anodizing aqueous solution containing an aqueous solution of nitriloacetic acid and 0.3 molar KOH with a pH value of 8.5 with an electrical current of about 20 microamperes per square centimeter of exposed stressor layer 116, oxidizes the stressor layer 116 where exposed by the cap layer 118 in the gate recess 120 to form an oxidized stressor layer 164 which includes indium oxide. In the instant example, the barrier layer 114 may include a layer of gallium nitride (GaN) 1 nanometer to 3 nanometers thick immediately below the stressor layer 116 to prevent oxidation of the aluminum gallium nitride in the barrier layer 114. At least a portion of the barrier layer 114 under the stressor layer 116 in the gate recess 120 is not oxidized.
  • Referring to FIG. 3B, a second etch process 166 removes the oxidized stressor layer 164 of FIG. 3A to form the gate recess 120, while leaving at least a portion, and possibly all, of the barrier layer 114 under the gate recess 120. The second etch process 166 may include, for example, a dilute aqueous solution of nitric acid, phosphoric acid, and/or hydrochloric acid, or an aqueous solution of an organic acid such as citric acid. The oxidation process described in reference to FIG. 3A and the second etch process of FIG. 3B may be repeated to completely remove the stressor layer 116 from the gate recess 120. The recess mask 148 is removed and fabrication is continued as described in reference to FIG. 2G.
  • While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.

Claims (18)

What is claimed is:
1. A method of forming a semiconductor device, comprising the steps:
forming a low-doped layer of III-N material over a substrate, in an area for an enhancement mode GaN FET;
forming a barrier layer of III-N material by a metal-organic chemical vapor deposition (MOCVD) process over the low-doped layer, the barrier layer having less than 1 atomic percent indium;
forming a stressor layer of III-N material by an MOCVD process over the barrier layer, the stressor layer having a stoichiometry of In0.05Al0.95N to In0.30Al0.70N, and a thickness of 1 nanometers to 5 nanometers;
forming a cap layer of III-N material by an MOCVD process over the stressor layer;
forming a recess mask over the cap layer which exposes an area for a gate recess in the area for the enhancement mode GaN FET;
removing the cap layer in the area exposed by the recess mask by a first etch process to form a portion of a gate recess of the enhancement mode GaN FET, the first etch process leaving at least a portion of the stressor layer under the area exposed by the recess mask;
removing the stressor layer in the area exposed by the recess mask by a second etch process to form the gate recess, the second etch process having a different chemistry than the first etch process, the second etch process leaving at least a portion of the barrier layer under the gate recess;
forming a gate dielectric layer over the barrier layer in the gate recess; and
forming a gate of the enhancement mode GaN FET over the gate dielectric layer in the gate recess.
2. The method of claim 1, wherein the substrate is a 150 millimeter wafer, and forming the barrier layer comprises:
placing the substrate on a susceptor in an MOCVD chamber;
heating the susceptor to a temperature of 900° C. to 1100° C.;
flowing hydrogen gas into the MOCVD chamber at a flow rate of 80 standard liters per minute (slm) to 120 slm;
flowing a nitrogen source into the MOCVD chamber at a flow rate of 5 slm to 30 slm;
flowing an aluminum precursor into the MOCVD chamber at a rate of 80 standard cubic centimeters per minute (sccm) to 130 sccm;
flowing a gallium precursor into the MOCVD chamber at a rate of 40 sccm to 160 sccm; and
maintaining a pressure in the MOCVD chamber at 50 torr to 200 torr.
3. The method of claim 1, wherein the substrate is a 150 millimeter wafer, and forming the stressor layer comprises:
placing the substrate on a susceptor in an MOCVD chamber;
heating the susceptor to a temperature of 700° C. to 850° C.;
flowing nitrogen gas into the MOCVD chamber at a flow rate of 60 slm to 100 slm;
flowing a nitrogen source into the MOCVD chamber at a flow rate 5 slm to 40 slm;
flowing an aluminum precursor into the MOCVD chamber at a rate of 80 sccm to 130 sccm;
flowing a indium precursor into the MOCVD chamber at a rate 100 sccm to 300 sccm; and
maintaining a pressure in the MOCVD chamber at 100 torr to 400 torr.
4. The method of claim 1, wherein the substrate is a 150 millimeter wafer, and forming the cap layer comprises:
placing the substrate on a susceptor in an MOCVD chamber;
heating the susceptor to a temperature of 750° C. to 900° C.;
flowing nitrogen gas into the MOCVD chamber at a flow rate of 80 slm to 120 slm;
flowing a nitrogen source into the MOCVD chamber at a flow rate of 5 slm to 35 slm;
flowing an aluminum precursor into the MOCVD chamber at a rate of 80 sccm to 130 sccm;
flowing a gallium precursor into the MOCVD chamber at a rate of 40 sccm to 60 sccm; and
maintaining a pressure in the MOCVD chamber at 50 torr to 200 torr.
5. The method of claim 1, wherein the barrier layer, the stressor layer and the cap layer are formed in one MOCVD chamber.
6. The method of claim 1, wherein the first etch process comprises a plasma etch process with chlorine radicals.
7. The method of claim 1, wherein the second etch process comprises a wet etch process with an aqueous solution of 1,2 diaminoethane.
8. The method of claim 1, comprising oxidizing the stressor layer in the area exposed by the recess mask to form an oxidized stressor layer, after removing the cap layer in the area exposed by the recess mask, wherein the second etch process removes the oxidized stressor layer.
9. The method of claim 1, comprising oxidizing a remaining portion of the stressor layer left in the area exposed by the recess mask after the step of removing the stressor layer by the first etch process.
10. The method of claim 1, wherein the gate dielectric layer extends over the cap layer, the stressor layer and the barrier layer in an area for a gate of a depletion mode GaN FET of the semiconductor device.
11. The method of claim 10, wherein forming the gate of the enhancement mode GaN FET comprises:
forming a layer of gate material over the gate dielectric layer in the gate recess and in the area for the gate of the depletion mode GaN FET; and
forming the gate of the enhancement mode GaN FET concurrently with the gate of the depletion mode GaN FET from the layer of gate material.
12. A method of forming a semiconductor device, comprising the steps:
forming a first layer of III-N material over a substrate, in an area for an enhancement mode GaN FET;
forming a second layer of III-N material by a metal-organic chemical vapor deposition (MOCVD) process over the first layer, the second layer having less than 1 atomic percent indium;
forming a third layer of III-N material by an MOCVD process over the second layer, the third layer having a stoichiometry of In0.05Al0.95N to In0.30Al0.70N, and a thickness of 1 nanometers to 5 nanometers;
forming a fourth layer of III-N material by an MOCVD process over the third layer;
forming a recess mask over the fourth layer which exposes an area for a gate recess in the area for the enhancement mode GaN FET;
removing the fourth layer in the area exposed by the recess mask by a first etch process to form a portion of a gate recess of the enhancement mode GaN FET, the first etch process leaving at least a portion of the third layer under the area exposed by the recess mask;
removing the third layer in the area exposed by the recess mask by a second etch process to form the gate recess, the second etch process having a different chemistry than the first etch process, the second etch process leaving at least a portion of the second layer under the gate recess;
forming a gate dielectric layer over the second layer in the gate recess; and
forming a gate of the enhancement mode GaN FET over the gate dielectric layer in the gate recess.
13. The method of claim 12, wherein the second layer, the third layer and the fourth layer are formed in one MOCVD chamber.
14. The method of claim 12, wherein the first etch process comprises a plasma etch process with chlorine radicals.
15. The method of claim 12, wherein the second etch process comprises a wet etch process with an aqueous solution of 1,2 diaminoethane.
16. The method of claim 12, comprising oxidizing the third layer in the area exposed by the recess mask to form an oxidized third layer, after removing the fourth layer in the area exposed by the recess mask, wherein the second etch process removes the oxidized third layer.
17. The method of claim 12, comprising oxidizing a remaining portion of the third layer left in the area exposed by the recess mask after the step of removing the third layer by the first etch process.
18. The method of claim 12, wherein the gate dielectric layer extends over the fourth layer, the third layer and the second layer in an area for a gate of a depletion mode GaN FET of the semiconductor device.
US15/988,618 2015-03-30 2018-05-24 Normally off III nitride transistor Active US11011515B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US15/988,618 US11011515B2 (en) 2015-03-30 2018-05-24 Normally off III nitride transistor
US17/234,385 US20210242200A1 (en) 2015-03-30 2021-04-19 Normally off iii nitride transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/673,844 US20160293596A1 (en) 2015-03-30 2015-03-30 Normally off iii-nitride transistor
US15/988,618 US11011515B2 (en) 2015-03-30 2018-05-24 Normally off III nitride transistor

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US14/673,844 Division US20160293596A1 (en) 2015-03-30 2015-03-30 Normally off iii-nitride transistor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/234,385 Continuation US20210242200A1 (en) 2015-03-30 2021-04-19 Normally off iii nitride transistor

Publications (2)

Publication Number Publication Date
US20180277535A1 true US20180277535A1 (en) 2018-09-27
US11011515B2 US11011515B2 (en) 2021-05-18

Family

ID=57005255

Family Applications (3)

Application Number Title Priority Date Filing Date
US14/673,844 Abandoned US20160293596A1 (en) 2015-03-30 2015-03-30 Normally off iii-nitride transistor
US15/988,618 Active US11011515B2 (en) 2015-03-30 2018-05-24 Normally off III nitride transistor
US17/234,385 Pending US20210242200A1 (en) 2015-03-30 2021-04-19 Normally off iii nitride transistor

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US14/673,844 Abandoned US20160293596A1 (en) 2015-03-30 2015-03-30 Normally off iii-nitride transistor

Family Applications After (1)

Application Number Title Priority Date Filing Date
US17/234,385 Pending US20210242200A1 (en) 2015-03-30 2021-04-19 Normally off iii nitride transistor

Country Status (5)

Country Link
US (3) US20160293596A1 (en)
EP (1) EP3278367A4 (en)
JP (2) JP6835736B2 (en)
CN (1) CN107210323B (en)
WO (1) WO2016160690A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200194575A1 (en) * 2018-12-13 2020-06-18 Intel Corporation E-d mode 2deg fet with gate spacer to locally tune vt and improve breakdown
US11664417B2 (en) * 2018-09-13 2023-05-30 Intel Corporation III-N metal-insulator-semiconductor field effect transistors with multiple gate dielectric materials

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160293596A1 (en) * 2015-03-30 2016-10-06 Texas Instruments Incorporated Normally off iii-nitride transistor
JP6604036B2 (en) * 2015-06-03 2019-11-13 富士通株式会社 Compound semiconductor device and manufacturing method thereof
US20190288089A9 (en) * 2015-12-28 2019-09-19 Texas Instruments Incorporated Methods for transistor epitaxial stack fabrication
US9722065B1 (en) * 2016-02-03 2017-08-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device
CN109690784A (en) 2016-08-22 2019-04-26 香港科技大学 With gate-dielectric/interface protective layer metal insulator semiconductor transistor
US11444172B2 (en) * 2017-12-01 2022-09-13 Mitsubishi Electric Corporation Method for producing semiconductor device and semiconductor device
US10103239B1 (en) * 2017-12-28 2018-10-16 Vanguard International Semiconductor Corporation High electron mobility transistor structure
CN111384166A (en) * 2018-12-29 2020-07-07 苏州捷芯威半导体有限公司 Semiconductor device and semiconductor device manufacturing method
CN109742143A (en) * 2018-12-29 2019-05-10 苏州汉骅半导体有限公司 Integrated enhanced and depletion type HEMT and its manufacturing method
US10879382B1 (en) 2019-06-26 2020-12-29 Northrop Grumman Systems Corporation Enhancement mode saddle gate device
US11251294B2 (en) * 2020-03-24 2022-02-15 Infineon Technologies Austria Ag High voltage blocking III-V semiconductor device
US11742390B2 (en) 2020-10-30 2023-08-29 Texas Instruments Incorporated Electronic device with gallium nitride transistors and method of making same
CN113707708B (en) * 2021-07-26 2023-03-14 西安电子科技大学 Junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor and manufacturing method thereof
CN115172367A (en) * 2022-07-07 2022-10-11 广东中科半导体微纳制造技术研究院 GaN-based HEMT structure with multiple threshold voltages, and preparation method and application thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080203477A1 (en) * 2007-02-22 2008-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20100317132A1 (en) * 2009-05-12 2010-12-16 Rogers John A Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays
US20110241020A1 (en) * 2010-03-31 2011-10-06 Triquint Semiconductor, Inc. High electron mobility transistor with recessed barrier layer
US20130313561A1 (en) * 2012-05-25 2013-11-28 Triquint Semiconductor, Inc. Group iii-nitride transistor with charge-inducing layer
US20160027964A1 (en) * 2014-07-25 2016-01-28 Seoul Viosys Co., Ltd. Uv light emitting diode and method of fabricating the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0194676A (en) * 1987-10-06 1989-04-13 Nec Corp Semiconductor device and manufacture thereof
US7456443B2 (en) * 2004-11-23 2008-11-25 Cree, Inc. Transistors having buried n-type and p-type regions beneath the source region
US7429534B2 (en) 2005-02-22 2008-09-30 Sensor Electronic Technology, Inc. Etching a nitride-based heterostructure
JP5051980B2 (en) 2005-03-31 2012-10-17 住友電工デバイス・イノベーション株式会社 Semiconductor device
JP4584293B2 (en) * 2007-08-31 2010-11-17 富士通株式会社 Nitride semiconductor device, Doherty amplifier, drain voltage control amplifier
US7915643B2 (en) * 2007-09-17 2011-03-29 Transphorm Inc. Enhancement mode gallium nitride power devices
JP5906004B2 (en) * 2007-11-19 2016-04-20 ルネサスエレクトロニクス株式会社 Field effect transistor and manufacturing method thereof
US20100117118A1 (en) * 2008-08-07 2010-05-13 Dabiran Amir M High electron mobility heterojunction device
US8816395B2 (en) * 2010-05-02 2014-08-26 Visic Technologies Ltd. Field effect power transistors
WO2012003609A1 (en) * 2010-07-06 2012-01-12 The Hong Kong University Of Science And Technology Normally-off iii-nitride metal-2deg tunnel junction field-effect transistors
US20120292663A1 (en) * 2011-05-19 2012-11-22 National Central University Structure and Method for Monolithically Fabrication Sb-Based E/D Mode MISFETs
JP2013077635A (en) * 2011-09-29 2013-04-25 Sumitomo Electric Ind Ltd Semiconductor device and manufacturing method of the same
US20130099284A1 (en) * 2011-10-20 2013-04-25 Triquint Semiconductor, Inc. Group iii-nitride metal-insulator-semiconductor heterostructure field-effect transistors
KR20130063833A (en) 2011-12-07 2013-06-17 삼성전기주식회사 Monolithic semiconductor device and manufacturing method thereof
JP2013235873A (en) * 2012-05-02 2013-11-21 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
US8933461B2 (en) * 2012-08-09 2015-01-13 Texas Instruments Incorporated III-nitride enhancement mode transistors with tunable and high gate-source voltage rating
CN104871319B (en) 2012-11-16 2018-04-10 麻省理工学院 Semiconductor structure and groove form etching technique
US9093301B2 (en) * 2013-03-08 2015-07-28 Texas Instruments Incorporated Driver for normally on III-nitride transistors to get normally-off functionality
US9553183B2 (en) * 2013-06-19 2017-01-24 Infineon Technologies Austria Ag Gate stack for normally-off compound semiconductor transistor
JP2015046444A (en) * 2013-08-27 2015-03-12 ルネサスエレクトロニクス株式会社 Semiconductor device
JP6337726B2 (en) * 2014-09-29 2018-06-06 株式会社デンソー Semiconductor device and manufacturing method thereof
US10468406B2 (en) 2014-10-08 2019-11-05 Northrop Grumman Systems Corporation Integrated enhancement mode and depletion mode device structure and method of making the same
US20160293596A1 (en) * 2015-03-30 2016-10-06 Texas Instruments Incorporated Normally off iii-nitride transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080203477A1 (en) * 2007-02-22 2008-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20100317132A1 (en) * 2009-05-12 2010-12-16 Rogers John A Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays
US20110241020A1 (en) * 2010-03-31 2011-10-06 Triquint Semiconductor, Inc. High electron mobility transistor with recessed barrier layer
US20130313561A1 (en) * 2012-05-25 2013-11-28 Triquint Semiconductor, Inc. Group iii-nitride transistor with charge-inducing layer
US20160027964A1 (en) * 2014-07-25 2016-01-28 Seoul Viosys Co., Ltd. Uv light emitting diode and method of fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11664417B2 (en) * 2018-09-13 2023-05-30 Intel Corporation III-N metal-insulator-semiconductor field effect transistors with multiple gate dielectric materials
US20200194575A1 (en) * 2018-12-13 2020-06-18 Intel Corporation E-d mode 2deg fet with gate spacer to locally tune vt and improve breakdown
US11757027B2 (en) * 2018-12-13 2023-09-12 Intel Corporation E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown

Also Published As

Publication number Publication date
CN107210323B (en) 2022-03-08
JP6835736B2 (en) 2021-02-24
JP2021044556A (en) 2021-03-18
US20160293596A1 (en) 2016-10-06
US11011515B2 (en) 2021-05-18
US20210242200A1 (en) 2021-08-05
JP7434679B2 (en) 2024-02-21
EP3278367A4 (en) 2018-03-14
JP2018517280A (en) 2018-06-28
CN107210323A (en) 2017-09-26
WO2016160690A1 (en) 2016-10-06
EP3278367A1 (en) 2018-02-07

Similar Documents

Publication Publication Date Title
US20210242200A1 (en) Normally off iii nitride transistor
US9564526B2 (en) Group III nitride integration with CMOS technology
US20180358458A1 (en) Normally-off hemt transistor with selective generation of 2deg channel, and manufacturing method thereof
KR101168824B1 (en) Methods for manufacturing enhancement-mode hemts with self-aligned field plate
US9111904B2 (en) Substrate breakdown voltage improvement for group III-nitride on a silicon substrate
US20110042719A1 (en) Semiconductor device and method of manufacturing a semiconductor device
CN111916351A (en) Semiconductor device and method for manufacturing the same
US20170222034A1 (en) METHOD FOR FORMATION OF VERTICAL CYLINDRICAL GaN QUANTUM WELL TRANSISTOR
US10096711B2 (en) Silicon-containing, tunneling field-effect transistor including III-N source
US20160149027A1 (en) Asymmetrical finfet structure and method of manufacturing same
CN111415987B (en) Gallium nitride device structure combining secondary epitaxy and self-alignment process and preparation method thereof
US10957790B2 (en) Semiconductor device with selectively etched surface passivation
JP6609926B2 (en) Compound semiconductor device and manufacturing method thereof
US9496401B1 (en) III-V device structure with multiple threshold voltage
US9184240B2 (en) Method of producing semiconductor wafer, and semiconductor wafer
CN117438457B (en) Groove gate type GaN-based HEMT device and preparation method thereof
CN115588616B (en) Method and device for manufacturing enhanced gallium nitride high electron mobility transistor
WO2022205469A1 (en) Iii nitride semiconductor wafers
US20240154012A1 (en) Semiconductor device and method for manufacturing the same
WO2022204913A1 (en) Iii nitride semiconductor devices on patterned substrates
KR20220083619A (en) High electron mobility transistor and fabricating method thereof

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF PUBLICATIONS

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT RECEIVED

STPP Information on status: patent application and granting procedure in general

Free format text: PUBLICATIONS -- ISSUE FEE PAYMENT VERIFIED

STCF Information on status: patent grant

Free format text: PATENTED CASE