US20160293608A1 - Semiconductor Devices and Methods for Manufacturing the Same - Google Patents

Semiconductor Devices and Methods for Manufacturing the Same Download PDF

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Publication number
US20160293608A1
US20160293608A1 US15/086,660 US201615086660A US2016293608A1 US 20160293608 A1 US20160293608 A1 US 20160293608A1 US 201615086660 A US201615086660 A US 201615086660A US 2016293608 A1 US2016293608 A1 US 2016293608A1
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Prior art keywords
contact
sub
active
source
patterns
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US15/086,660
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English (en)
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Changseop YOON
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YOON, CHANGSEOP
Publication of US20160293608A1 publication Critical patent/US20160293608A1/en
Priority to US15/821,230 priority Critical patent/US10366997B2/en
Priority to US16/437,914 priority patent/US10763268B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H01L27/1104—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

Definitions

  • the inventive concepts relate to semiconductor devices and methods for manufacturing the same. More particularly, the inventive concepts relate to semiconductor devices including field effect transistors and methods for manufacturing the same.
  • Semiconductor devices may be attractive in the electronics industry because of their small sizes, multi-functional characteristics, and/or relatively low manufacture costs.
  • Semiconductor devices may be categorized as memory devices for storing logical data, logic devices for processing logical data, and hybrid semiconductor devices having the functionalities of both the memory devices and the logic devices.
  • Semiconductor devices with excellent characteristics may be increasingly demanded with the development of the electronics industry. For example, high-reliability, high-speed, and/or multi-functional semiconductor devices may be increasingly demanded. To satisfy these demands, structures in semiconductor devices may become more complex and semiconductor devices may become more highly integrated.
  • Embodiments of the inventive concepts may provide semiconductor devices including an active contact, which is capable of improving reliability.
  • Embodiments of the inventive concepts may also provide methods for manufacturing semiconductor devices with improved reliability by a less complex process.
  • a semiconductor device includes a substrate including active patterns extending in parallel thereon; a gate electrode extending across the active patterns; respective source/drain regions in the active patterns at opposite sides of the gate electrode; and respective active contacts on and electrically contacting the respective source/drain regions.
  • At least one of the respective active contacts includes a first sub-contact extending on a corresponding one of the respective source/drain regions opposite the substrate, and a second sub-contact extending toward the substrate beyond the first sub-contact and between adjacent ones of the active patterns. The second sub-contact is separated from the adjacent ones of the active patterns by an insulating material.
  • the semiconductor device may further include respective conductive connection patterns between the respective source/drain regions and the respective active contacts thereon.
  • the respective conductive connection patterns and the respective active contacts may include different materials.
  • the second sub-contact of the at least one of the respective active contacts may extend towards the substrate between ones of the respective conductive connection patterns on the adjacent ones of the active patterns and may be separated from sidewalls of the ones of the respective conductive connection patterns by the insulating material.
  • respective upper surfaces of the first and second sub-contacts opposite the substrate may be coplanar, and the first and second sub-contacts of the at least one of the respective active contacts may define a unitary member.
  • the semiconductor device may further include device isolation layers on the substrate between the active patterns.
  • the insulating material may be an interlayer insulating layer on the device isolation layers.
  • the second sub-contact of the at least one of the respective active contacts may extend towards the substrate beyond a surface of the gate electrode and into the interlayer insulating layer but may be confined above the device isolation layers, and the first sub-contact of the at least one of the respective active contacts may be confined above the surface of the gate electrode.
  • the semiconductor device may further include a conductive via on the respective upper surfaces of the first and/or second sub-contacts of the at least one of the respective active contacts.
  • the via may be between ones of the active patterns in plan view.
  • a conductive line on the conductive via may be electrically connected to the at least one of the respective active contacts thereby.
  • the respective active contacts may have coplanar surfaces. Another of the respective active contacts may include the first sub-contact extending on a corresponding one of the respective source/drain regions opposite the substrate, but may be free of the second sub-contact extending toward the substrate beyond the first sub-contact and between adjacent ones of the active patterns.
  • the first sub-contact of the at least one of the respective active contacts may extend in a different direction than the second sub-contact thereof to increase a contact area thereof.
  • the first sub-contact of the at least one of the respective active contacts may extend parallel to the gate electrode, and the second sub-contact of the at least one of the respective active contacts may extend perpendicular to the gate electrode and parallel to the active patterns.
  • a semiconductor device may include a substrate including first and second active patterns formed thereon, the first and second active patterns extending in a first direction parallel to a top surface of the substrate, a first gate electrode intersecting the first and second active patterns and extending in a second direction intersecting the first direction, first and second source/drain regions respectively provided in upper portions of the first and second active patterns at one side of the first gate electrode, the first and second source/drain regions spaced apart from each other in the second direction, and an active contact disposed on the first source/drain region so as to be electrically connected to the first source/drain region.
  • the active contact may include a first sub-contact overlapping with the first source/drain region in plan view, and a second sub-contact provided between the first and second source/drain regions in plan view.
  • the second sub-contact may include a vertical extension vertically extending toward the substrate, and a bottom surface of the vertical extension may be lower than a bottom surface of the first sub-contact.
  • the semiconductor device may further include device isolation layers disposed in the substrate to define the first and second active patterns, and an interlayer insulating layer covering the first and second source/drain regions and sidewalls of the first gate electrode.
  • the bottom surface of the vertical extension may be disposed at a level between a top surface of the interlayer insulating layer and top surfaces of the device isolation layers.
  • a top surface of the second sub-contact may be substantially coplanar with a top surface of the first sub-contact.
  • the first sub-contact and the second sub-contact may include the same material and may be connected to each other to constitute one body.
  • the vertical extension may overlap with the first sub-contact in plan view.
  • the top surface of the interlayer insulating layer may be substantially coplanar with a top surface of the first gate electrode.
  • the semiconductor device may further include first and second conductive connection patterns provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively.
  • the first sub-contact may be disposed on a top surface of the first conductive connection pattern so as to be electrically connected to the first source/drain region through the first conductive connection pattern, and the second sub-contact may be provided between the first and second conductive connection patterns.
  • the semiconductor device may further include a barrier layer surrounding sidewalls and a bottom surface of the active contact. A portion of the barrier layer may be disposed between the first sub-contact and the first conductive connection pattern.
  • the semiconductor device may further include a second gate electrode intersecting the first and second active patterns and extending in parallel to the first gate electrode.
  • the first and second gate electrodes may be spaced apart from each other in the first direction, and the active contact may be provided between the first and second gate electrodes in plan view.
  • the semiconductor device may further include a capping layer covering top surfaces of the first and second gate electrodes in common.
  • the bottom surface of the vertical extension may be lower than a bottom surface of the capping layer.
  • the semiconductor device may further include a via provided on the active contact, and a conductive line provided on the via so as to be electrically connected to the first source/drain region through the via and the active contact.
  • the active contact may have a T-shape when viewed from a cross-sectional view taken along the first direction.
  • one sidewall of the second sub-contact which is adjacent to the vertical extension, may have a stepped profile when viewed from a cross-sectional view taken along the second direction.
  • the first sub-contact may have a first sidewall
  • the second sub-contact may have a second sidewall adjacent to the first sidewall.
  • the first sidewall and the second sidewall may be coplanar with each other.
  • the first sub-contact may extend in the second direction to penetrate the second sub-contact in plan view.
  • a semiconductor device may include a substrate, device isolation layers provided in the substrate to define active patterns, the active patterns including upper portions protruding from top surfaces of the device isolation layers, a source/drain region provide in the upper portion of at least one of the active patterns, a conductive connection pattern provided on the source/drain region so as to be connected to the source/drain region, an active contact provided on the conductive connection pattern so as to be electrically connected to the source/drain region, the active contact including a first sub-contact connected to a top surface of the conductive connection pattern and a second sub-contact connected to the first sub-contact in one body, a via provided on the active contact, and a conductive line provided on the via so as to be electrically connected to the source/drain region through the via and the active contact.
  • the second sub-contact may include a vertical extension vertically extending toward the substrate, and the vertical extension may overlap with the first sub-contact in plan view.
  • a bottom surface of the vertical extension may be lower than a bottom surface of the first sub-contact.
  • the semiconductor device may further include a barrier layer surrounding the active contact. A portion of the barrier layer may be disposed between the first sub-contact and the conductive connection pattern.
  • the semiconductor device may further include first and second gate electrodes spaced apart from each other with the source/drain region interposed therebetween.
  • the first and second gate electrodes may extend in parallel to each other to intersect the active patterns.
  • the active contact may be disposed between the first and second gate electrodes in plan view, and the active contact may be spaced apart from all of the first and second gate electrodes.
  • the semiconductor device may further include a capping layer covering top surfaces of the first and second gate electrodes in common.
  • the second sub-contact may penetrate the capping layer.
  • a semiconductor device may include a substrate, device isolation layers disposed in the substrate to define active patterns, the active patterns including upper portions protruding from top surfaces of the device isolation layers, a gate electrode intersecting the active patterns, a source/drain region provided in the upper portion of at least one of the active patterns, the source/drain region adjacent to the gate electrode, and an active contact disposed on the source/drain region so as to be electrically connected to the source/drain region.
  • the active contact may be spaced apart from the gate electrode, and the active contact may include a vertical extension having a bottom surface lower than a top surface of the gate electrode.
  • the active contact may include a first sub-contact overlapping with the source/drain region in plan view, and a second sub-contact connected to the first sub-contact in one body. A portion of the second sub-contact, which vertically extends toward the substrate, may correspond to the vertical extension.
  • the vertical extension may overlap with the first sub-contact in plan view.
  • a method for manufacturing a semiconductor device may include forming first and second active patterns on a substrate, forming first and second gate electrodes extending in parallel to each other to intersect the first and second active patterns, forming first and second source/drain regions in upper portions of the first and second active patterns between the first and second gate electrodes, respectively, forming at least one interlayer insulating layer covering the first and second gate electrodes and the first and second source/drain regions, forming a first sub-contact hole overlapping with the first source/drain region in a plan view by patterning the at least one interlayer insulating layer, forming a second sub-contact hole between the first and second source/drain regions in a plan view by patterning the at least one interlayer insulating layer, the first and second sub-contact holes connected to each other to constitute one communicating hole, and forming an active contact filling the communicating hole.
  • Forming the second sub-contact hole may include forming a vertical extension hole vertically extending from a portion of a bottom surface of the first sub-contact
  • a first layout defining a position of the first sub-contact hole may be provided to partially overlap with a second layout defining a position of the second sub-contact hole, and the vertical extension hole may be formed in an overlapping region of the first and second layouts.
  • the method may further include patterning the at least one interlayer insulating layer to form a gate contact hole exposing a top surface of at least one of the first and second gate electrodes.
  • the gate contact hole may be formed simultaneously with the second sub-contact hole.
  • the method may further include forming first and second conductive connection patterns connected to the first and second source/drain regions, respectively. At least one of the interlayer insulating layers may be formed to cover the first and second conductive connection patterns, and the first sub-contact hole may expose a top surface of the first conductive connection pattern.
  • FIG. 1 is an equivalent circuit diagram illustrating a static random access memory (SRAM) cell according to example embodiments of the inventive concepts.
  • SRAM static random access memory
  • FIG. 2 is a plan view illustrating semiconductor devices according to example embodiments of the inventive concepts.
  • FIGS. 3A, 3B, 3C, 3D, and 3E are cross-sectional views taken along lines A-A′, B-B′, C-C′, D-D′, and E-E′ of FIG. 2 , respectively.
  • FIGS. 4, 6, and 8 are plan views illustrating methods for manufacturing semiconductor devices according to example embodiments of the inventive concepts.
  • FIGS. 5A, 7A, and 9A are cross-sectional views taken along lines A-A′ of FIGS. 4, 6, and 8 , respectively.
  • FIGS. 5B, 7B, and 9B are cross-sectional views taken along lines B-B′ of FIGS. 4, 6, and 8 , respectively.
  • FIGS. 5C, 7C, and 9C are cross-sectional views taken along lines C-C′ of FIGS. 4, 6, and 8 , respectively.
  • FIGS. 7D and 9D are cross-sectional views taken along lines D-D′ of FIGS. 6 and 8 , respectively.
  • FIGS. 7E and 9E are cross-sectional views taken along lines E-E′ of FIGS. 6 and 8 , respectively.
  • FIG. 10 is a schematic block diagram illustrating an electronic system including semiconductor devices according to example embodiments of the inventive concepts.
  • FIG. 11 is a schematic block diagram illustrating an electronic device including semiconductor devices according to example embodiments of the inventive concepts.
  • FIGS. 12 to 14 illustrate embodiments of multimedia devices including semiconductor devices according to example embodiments of the inventive concepts.
  • inventive concepts will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the inventive concepts are shown.
  • the advantages and features of the inventive concepts and methods of achieving them will be apparent from the following exemplary embodiments that will be described in more detail with reference to the accompanying drawings.
  • inventive concepts are not limited to the following exemplary embodiments, and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose the inventive concepts and let those skilled in the art know the category of the inventive concepts.
  • embodiments of the inventive concepts are not limited to the specific examples provided herein and are exaggerated for clarity.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • exemplary embodiments are described herein with reference to cross-sectional illustrations and/or plane illustrations that are idealized exemplary illustrations. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etching region illustrated as a rectangle will, typically, have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • devices and methods of forming devices according to various embodiments described herein may be embodied in microelectronic devices such as integrated circuits, wherein a plurality of devices according to various embodiments described herein are integrated in the same microelectronic device. Accordingly, the cross-sectional view(s) illustrated herein may be replicated in two different directions, which need not be orthogonal, in the microelectronic device.
  • a plan view of the microelectronic device that embodies devices according to various embodiments described herein may include a plurality of the devices in an array and/or in a two-dimensional pattern that is based on the functionality of the microelectronic device.
  • microelectronic devices according to various embodiments described herein may be interspersed among other devices depending on the functionality of the microelectronic device. Moreover, microelectronic devices according to various embodiments described herein may be replicated in a third direction that may be orthogonal to the two different directions, to provide three-dimensional integrated circuits.
  • the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view.
  • the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure.
  • FIG. 1 is an equivalent circuit diagram illustrating a static random access memory (SRAM) cell according to example embodiments of the inventive concepts.
  • SRAM static random access memory
  • a SRAM cell may include a first pull-up transistor TU 1 , a first pull-down transistor TD 1 , a second pull-up transistor TU 2 , a second pull-down transistor TD 2 , a first access transistor TA 1 , and a second access transistor TA 2 .
  • the first and second pull-up transistors TU 1 and TU 2 may be P-type metal-oxide-semiconductor (PMOS) transistors, but the first and second pull-down transistors TD 1 and TD 2 and the first and second access transistors TA 1 and TA 2 may be N-type MOS (NMOS) transistors.
  • PMOS P-type metal-oxide-semiconductor
  • a first source/drain of the first pull-up transistor TU 1 and a first source/drain of the first pull-down transistor TD 1 may be connected to a first node N 1 .
  • a second source/drain of the first pull-up transistor TU 1 may be connected to a power line Vcc, and a second source/drain of the first pull-down transistor TD 1 may be connected to a ground line Vss.
  • a gate of the first pull-up transistor TU 1 may be electrically connected to a gate of the first pull-down transistor TD 1 .
  • the first pull-up transistor TU 1 and the first pull-down transistor TD 1 may define a first inverter.
  • the gates of the first pull-up and first pull-down transistors TU 1 and TD 1 which are connected to each other, may correspond to an input terminal of the first inverter.
  • the first node N 1 may correspond to an output terminal of the first inverter.
  • a first source/drain of the second pull-up transistor TU 2 and a first source/drain of the second pull-down transistor TD 2 may be connected to a second node N 2 .
  • a second source/drain of the second pull-up transistor TU 2 may be connected to the power line Vcc, and a second source/drain of the second pull-down transistor TD 2 may be connected to the ground line Vss.
  • a gate of the second pull-up transistor TU 2 may be electrically connected to a gate of the second pull-down transistor TD 2 .
  • the second pull-up transistor TU 2 and the second pull-down transistor TD 2 may define a second inverter.
  • the gates of the second pull-up and second pull-down transistors TU 2 and TD 2 which are connected to each other, may correspond to an input terminal of the second inverter.
  • the second node N 2 may correspond to an output terminal of the second inverter.
  • the first and second inverters may be combined with each other to define a latch structure.
  • the gates of the first pull-up and first pull-down transistors TU 1 and TD 1 may be electrically connected to the second node N 2
  • the gates of the second pull-up and second pull-down transistors TU 2 and TD 2 may be electrically connected to the first node N 1 .
  • a first source/drain of the first access transistor TA 1 may be connected to the first node N 1
  • a second source/drain of the first access transistor TA 1 may be connected to a first bit line BL 1 .
  • a first source/drain of the second access transistor TA 2 may be connected to the second node N 2 , and a second source/drain of the second access transistor TA 2 may be connected to a second bit line BL 2 .
  • Gates of the first and second access transistors TA 1 and TA 2 may be electrically connected to a word line WL.
  • FIG. 2 is a plan view illustrating semiconductor devices according to example embodiments of the inventive concepts.
  • FIGS. 3A, 3B, 3C, 3D, and 3E are cross-sectional views taken along lines A-A′, B-B′, C-C′, D-D′, and E-E′ of FIG. 2 , respectively.
  • a first device isolation layer ST 1 may be provided in a substrate 100 to define logic cells.
  • FIG. 2 illustrates one of the logic cells.
  • the logic cell may correspond to a unit for performing a logic function.
  • the logic cell may include the SRAM cell described with reference to FIG. 1 .
  • the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.
  • Second device isolation layers ST 2 may be provided in a substrate 100 to define active patterns FN 1 to FN 6 .
  • the active patterns FN 1 to FN 6 may include first to sixth active patterns FN 1 to FN 6 extending in a second direction D 2 parallel to a top surface of the substrate 100 .
  • the active patterns FN 1 to FN 6 may be arranged in a first direction D 1 intersecting the second direction D 2 .
  • the first direction D 1 may be parallel to the top surface of the substrate 100 .
  • the second device isolation layers ST 2 extending in the second direction D 2 may be disposed at both sides of each of the active patterns FN 1 to FN 6 .
  • upper portions of the active patterns FN 1 to FN 6 may include fin portions, respectively. The fin portions may have fin shapes protruding from between the second device isolation layers ST 2 .
  • each of the active patterns FN 1 to FN 6 may define a P-type metal-oxide-semiconductor field effect transistor (PMOSFET) region or an N-type MOSFET (NMOSFET) region.
  • the second, third and sixth active patterns FN 2 , FN 3 and FN 6 may define the PMOSFET regions
  • the first, fourth and fifth active patterns FN 1 , FN 4 and FN 5 may define the NMOSFET regions.
  • Distances between the active patterns FN 1 to FN 6 may be varied according to region-types of the active patterns FN 1 to FN 6 .
  • the first active pattern FN 1 may be the NMOSFET region
  • the second active pattern FN 2 may be the PMOSFET region different from the NMOSFET region.
  • the distance between the first and second active patterns FN 1 and FN 2 may be defined as a first distance.
  • the second and third active patterns FN 2 and FN 3 may be the PMOSFET regions.
  • the second and third active pattern FN 2 and FN 3 may be the same kind of regions.
  • the distance between the second and third active patterns FN 2 and FN 3 may be defined as a second distance.
  • the second distance may be greater than the first distance.
  • the first device isolation layer ST 1 and the second device isolation layers ST 2 may be connected to each other to define an insulating layer that is of one body or defines a unitary member.
  • a thickness (or a depth) of the first device isolation layer ST 1 may be greater than thicknesses (or depths) of the second device isolation layers ST 2 .
  • the second device isolation layers ST 2 may be formed by a process different from a process of forming the first device isolation layer ST 1 .
  • the second device isolation layers ST 2 may be formed simultaneously with the first device isolation layer ST 1 , so the thicknesses of the second device isolation layers ST 2 may be substantially equal to the thickness of the first device isolation layer ST 1 .
  • the first and second device isolation layers ST 1 and ST 2 may be formed in an upper portion of the substrate 100 .
  • the first and second device isolation layers ST 1 and ST 2 may include a silicon oxide layer.
  • Gate electrodes G 1 to G 6 may be provided on the active patterns FN 1 to FN 6 .
  • the gate electrodes G 1 to G 6 may extend in the first direction D 1 to intersect the active patterns FN 1 to FN 6 .
  • the gate electrodes G 1 to G 6 may be spaced apart from each other in the second direction D 2 .
  • the gate electrodes G 1 to G 6 may include first to sixth gate electrodes G 1 to G 6 that extend in the first direction D 1 to intersect the active patterns FN 1 to FN 6 and the second device isolation layer ST 2 .
  • a gate insulating pattern GI may be provided under each of the gate electrodes G 1 to G 6 , and gate spacers GS may be provided on both sidewalls of each of the gate electrodes G 1 to G 6 .
  • a first interlayer insulating layer 110 may be provided to fill spaces between the gate electrodes G 1 to G 6 .
  • a capping layer GP may be provided on the first interlayer insulating layer 110 to extend on or cover top surfaces of the gate electrodes G 1 to G 6 in common.
  • Second, third, fourth and fifth interlayer insulating layers 115 , 120 , 130 , and 140 may be sequentially stacked on the capping layer GP.
  • a first etch stop layer ES 1 may be disposed between the second and third interlayer insulating layers 115 and 120
  • a second etch stop layer ES 2 may be disposed between the third and fourth interlayer insulating layers 120 and 130
  • a third etch stop layer ES 3 may be disposed between the fourth and fifth interlayer insulating layers 130 and 140 .
  • the gate electrodes G 1 to G 6 may include at least one of a doped semiconductor material, a metal, or a conductive metal nitride.
  • the gate insulating pattern GI may include at least one of a silicon oxide layer, a silicon oxynitride layer, or a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer.
  • Each of the capping layer GP and the gate spacer GS may include at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • Each of the first to fifth interlayer insulating layers 110 , 115 , 120 , 130 and 140 may include a silicon oxide layer and/or a silicon oxynitride layer.
  • Each of the first to third etch stop layers ES 1 , ES 2 and ES 3 may include silicon carbonitride (SiCN).
  • Source/drain regions SD 1 to SD 6 may be provided in upper portions of the active patterns FN 1 to FN 6 disposed at both sides of each of the gate electrodes G 1 to G 6 .
  • the source/drain regions SD 1 to SD 6 may include first to sixth source/drain regions SD 1 to SD 6 that are disposed in the upper portions of the first to sixth active patterns FN 1 to FN 6 , respectively.
  • the source/drain regions SD 1 to SD 6 may be disposed on the active patterns FN 1 to FN 6 and may extend onto the substrate 100 (i.e., onto the second device isolation layers ST 2 ). Alternatively, the source/drains SD may be confined in the active patterns FN 1 to FN 6 .
  • the second, third and sixth source/drain regions SD 2 , SD 3 and SD 6 of the second, third and sixth active patterns FN 2 , FN 3 and FN 6 may be doped with P-type dopants, and the first, fourth and fifth source/drain regions SD 1 , SD 4 and SD 5 of the first, fourth and fifth active patterns FN 1 , FN 4 and FN 5 may be doped with N-type dopants.
  • the fin portions which are disposed under and overlap with the gate electrodes G 1 to G 6 may be used as channel regions.
  • the source/drain regions SD 1 to SD 6 may include epitaxial patterns formed by a selective epitaxial growth (SEG) process.
  • the upper portions of the active patterns FN 1 to FN 6 in which the source/drain regions SD 1 to SD 6 are formed, may include the epitaxial patterns.
  • top surfaces of the source/drain regions SD 1 to SD 6 may be disposed at a higher level than top surfaces of the fin portions.
  • the source/drain regions SD 1 to SD 6 may include a different semiconductor element from the substrate 100 .
  • the source/drain regions SD 1 to SD 6 may include a semiconductor element of which a lattice constant is larger or smaller than that of the semiconductor element of the substrate 100 .
  • the source/drain regions SD 1 to SD 6 may provide compressive stress or tensile stress to the channel regions.
  • the substrate 100 is a silicon substrate
  • the second, third and sixth source/drain regions SD 2 , SD 3 and SD 6 of the PMOSFET regions may include embedded silicon-germanium (SiGe) or germanium (Ge).
  • the second, third and sixth source/drain regions SD 2 , SD 3 and SD 6 may provide the compressive stress to the channel region adjacent thereto.
  • the first, fourth and fifth source/drain regions SD 1 , SD 4 and SD 5 of the NMOSFET regions may include silicon carbide (SiC).
  • the first, fourth and fifth source/drain regions SD 1 , SD 4 and SD 5 may provide the tensile stress to the channel regions adjacent thereto. Since the source/drain regions SD 1 to SD 6 provide the compressive stress or the tensile stress to the channel regions, mobility of the carriers generated in the channel regions may be improved when the field effect transistors according to the inventive concepts are operated.
  • Conductive connection patterns TS may be provided at both sides of each of the gate electrodes G 1 to G 6 .
  • some of the conductive connection patterns TS may be disposed to correspond to some of the source/drain regions SD 1 to SD 6 , respectively.
  • the some of the conductive connection patterns TS may be spaced apart from each other in the first direction D 1 , like the source/drain regions SD 1 to SD 6 .
  • others of the conductive connection patterns TS may electrically connect others, spaced apart from each other, of the source/drain regions SD 1 to SD 6 to each other.
  • the conductive connection pattern TS covering the fourth and fifth source/drain regions SD 4 and SD 5 in common may electrically connect the fourth and fifth source/drain regions SD 4 and SD 5 to each other (see FIG. 3B ).
  • the conductive connection patterns TS may be in direct contact with the source/drain regions SD 1 to SD 6 .
  • the conductive connection patterns TS may include a metal silicide.
  • the conductive connection patterns TS may include at least one of titanium silicide, tantalum silicide, or tungsten silicide.
  • the conductive connection patterns TS may further include a metal layer.
  • the metal layer may include at least one of titanium, tantalum, or tungsten.
  • each of the conductive connection patterns TS may include the metal silicide layer and the metal layer disposed on the metal silicide layer.
  • the conductive connection patterns TS may be provided in the first and second interlayer insulating layers 110 and 115 and the capping layer GP.
  • First barrier layers BM 1 may be provided between the conductive connection patterns TS and the first and second interlayer insulating layers 110 and 115 , between the conductive connection patterns TS and the capping layer GP, and between the conductive connection patterns TS and the source/drain regions SD 1 to SD 6 .
  • Each of the first barrier layers BM 1 may have a substantially uniform thickness and may extend on or surround each of the conductive connection patterns TS. However, top surfaces of the conductive connection patterns TS may not be covered with the first barrier layer BM 1 .
  • the first barrier layer BM 1 may include titanium/titanium nitride (Ti/TiN).
  • Source/drain contacts SDC and first to fourth active contacts CA 1 to CA 4 may be provided on the conductive connection patterns TS.
  • the source/drain contacts SDC may be provided at both sides of each of the gate electrodes G 1 to G 6 in plan view.
  • Each of the source/drain contacts SDC may extend on or cover the top surface of the conductive connection pattern TS and may have a bar shape extending in the first direction D 1 .
  • At least one of the source/drain contacts SDC may electrically connect two or more conductive connection patterns TS to each other.
  • Gate contacts CB may be provided on the gate electrodes G 1 to G 6 , respectively. In some embodiments, each of the gate contacts CB may be disposed on an end portion of each of the gate electrodes G 1 to G 6 .
  • the gate contacts CB may penetrate the second and third interlayer insulating layers 115 and 120 , the first etch stop layer ES 1 , and the capping layer GP so as to be in direct contact with top surfaces of the gate electrodes G 1 to G 6 .
  • the gate electrodes G 1 to G 6 may be electrically connected to conductive lines disposed thereon through the gate contacts CB and vias disposed on the gate contacts CB.
  • the fourth gate electrode G 4 may be electrically connected to a fifth conductive line CBL 5 through the gate contact CB and a fifth via V 5 disposed on the gate contact CB.
  • the source/drain contacts SDC and the gate contacts CB may include at least one of a doped semiconductor material, a metal, or a conductive metal nitride.
  • the conductive connection patterns TS may include a different material from the source/drain contacts SDC.
  • the source/drain contacts SDC may include tungsten
  • the conductive connection patterns TS may include a metal silicide.
  • first, second and third active contacts CA 1 , CA 2 and CA 3 may be provided on the second active pattern FN 2
  • a fourth active contact CA 4 may be provided on the third and fourth active patterns FN 3 and FN 4
  • the fourth active contact CA 4 may intersect the third and fourth active patterns FN 3 and FN 4
  • the first active contact CA 1 may be provided between the first and second gate electrodes G 1 and G 2
  • the second and fourth active contacts CA 2 and CA 4 may be provided between the third and fourth gate electrodes G 3 and G 4
  • the third active contact CA 3 may be provided between the fifth and sixth gate electrodes G 5 and G 6 .
  • Second barrier layers BM 2 may be provided to extend on or surround sidewalls and bottom surfaces of the first to fourth active contacts CA 1 to CA 4 . However, top surfaces of the first to fourth active contacts CA 1 to CA 4 may not be covered with the second barrier layers BM 2 . Portions of the second barrier layers BM 2 may be disposed between the conductive connection patterns TS and the active contacts CA 1 to CA 4 .
  • the second barrier layers BM 2 may include Ti/TiN. Thus, the second barrier layers BM 2 may reduce or substantially prevent a metal from being diffused between the conductive connection patterns TS and the active contacts CA 1 to CA 4 .
  • the first active contact CA 1 may include first and second sub-contacts or portions SC 1 and SC 2 .
  • the first sub-contact SC 1 may be disposed on and connected to the top surface of the conductive connection pattern TS disposed on the second source/drain region SD 2 .
  • the second sub-contact SC 2 may be spaced apart from both the second source/drain region SD 2 and the conductive connection pattern TS disposed on the second source/drain region SD 2 .
  • the first sub-contact SC 1 may overlap with the second source/drain region SD 2 in plan view, but the second sub-contact SC 2 may be disposed between the second and third source/drain regions SD 2 and SD 3 in plan view.
  • the first sub-contact SC 1 and the second sub-contact SC 2 may include the same material and may be connected to each other to define the first active contact CA 1 that is of one body or defines a unitary member.
  • the first and second sub-contacts SC 1 and SC 2 may include at least one of a doped semiconductor material, a metal, or a conductive metal nitride.
  • the first and second sub-contacts SC 1 and SC 2 may include the same material as the source/drain contacts SDC.
  • the source/drain contacts SDC may correspond to active contacts that include the first sub-contact or portion SC 1 but are free of the second sub-contact or portion SC 2 .
  • the first sub-contact SC 1 may be provided in the third interlayer insulating layer 120 .
  • a top surface of the first sub-contact SC 1 may be substantially coplanar with a top surface of the third interlayer insulating layer 120 .
  • the top surface of the first sub-contact SC 1 may be disposed at the substantially same level as top surfaces of the source/drain contacts SDC, and a bottom surface of the first sub-contact SC 1 may be disposed at the substantially same level as bottom surfaces of the source/drain contacts SDC.
  • the first sub-contact SC 1 may be disposed between the first and second gate electrodes G 1 and G 2 in plan view.
  • the first sub-contact SC 1 may have a bar shape extending in the first direction D 1 .
  • a bottom surface of the second sub-contact SC 2 may be disposed at the substantially same level as bottom surfaces of the gate contacts CB. In other words, the bottom surface of the second sub-contact SC 2 may be disposed at the substantially same level as the top surfaces of the gate electrodes G 1 to G 6 . In other embodiments, the bottom surface of the second sub-contact SC 2 may be disposed at a lower level than the bottom surfaces of the gate contacts CB. However, the inventive concepts are not limited thereto.
  • a top surface of the second sub-contact SC 2 may be substantially coplanar with the top surface of the first sub-contact SC 1 . In other words, the top surface of the second sub-contact SC 2 may be substantially coplanar with the top surface of the third interlayer insulating layer 120 .
  • the second sub-contact SC 2 may include a vertical extension VP that extends toward the substrate 100 between the second and third source/drain regions SD 2 and SD 3 .
  • a bottom surface of the vertical extension VP may be lower than the bottom surface of the first sub-contact SC 1 .
  • the bottom surface of the vertical extension VP may be lower than the top surfaces of the first and second gate electrodes G 1 and G 2 adjacent to the vertical extension VP.
  • the bottom surface of the vertical extension VP may be disposed at a level between the top surface of the first interlayer insulating layer 110 and a top surface of the second device isolation layer ST 2 .
  • the vertical extension VP may be formed using double-etching when the first and second sub-contacts SC 1 and SC 2 are formed. This will be described later in more detail. As a result, the vertical extension VP may also overlap with the first sub-contact SC 1 in plan view.
  • the vertical extension VP may extend from the bottom surface of the second sub-contact SC 2 toward the substrate 100 when viewed from a cross-sectional view taken along the second direction D 2 .
  • the first active contact CA 1 may have a T-shaped cross section.
  • the second to fourth active contacts CA 2 to CA 4 may also have the same T-shaped cross section.
  • the second sub-contact SC 2 may extend on or surround one end portion of the first sub-contact SC 1 in plan view.
  • one sidewall, adjacent to the vertical extension VP, of the second sub-contact SC 2 may have a stepped profile, as illustrated in FIG. 3D .
  • the bottom surface of the vertical extension VP may be disposed at a first height H 1 from the top surface of the second device isolation layer ST 2
  • the bottom surface of the second sub-contact SC 2 may be disposed at a second height H 2 from the top surface of the second device isolation layer ST 2 .
  • the second height H 2 may be higher than the first height H 1 .
  • the one sidewall of the second sub-contact SC 2 may have the stepped profile.
  • each of the gate contacts CB may be disposed at a third height H 3 from the top surfaces of the first and second device isolation layers ST 1 and ST 2 .
  • the third height H 3 may be the same as or higher than the second height H 2 , as described above.
  • a first conductive line CBL 1 may be disposed on the first active contact CA 1 .
  • a first via V 1 may be disposed between the first active contact CA 1 and the first conductive line CBL 1 .
  • the first via V 1 may be provided on the first active contact CA 1 .
  • the first conductive line CBL 1 may be electrically connected to the second source/drain region SD 2 through the first via V 1 and the first active contact CA 1 to exchange input/output signals with the second source/drain region SD 2 .
  • the first via V 1 may be provided in the fourth interlayer insulating layer 130
  • the first conductive line CBL 1 may be provided in the fifth interlayer insulating layer 140 .
  • the second sub-contact SC 2 may be formed at the same level as the gate contacts CB, and the first active contact CA 1 may be laterally enlarged from the first sub-contact SC 1 to over the second device isolation layer ST 2 due to the second sub-contact SC 2 .
  • the first via V 1 may be stably formed on the first active contact CA 1 having an enlarged planar area.
  • the second sub-contact SC 2 may act as a pad on which the first via V 1 is disposed.
  • a contact area between the first active contact CA 1 and the first via V 1 may be increased by the enlarged planar area of the first active contact CA 1 , and thus, semiconductor devices with a low contact resistance may be realized.
  • the first active contact CA 1 described above may be one example according to some embodiments of the inventive concepts.
  • the second active contact CA 2 corresponding to another example of the inventive concepts will be described in more detail.
  • the descriptions to the same features as in the first active contact CA 1 will be omitted or mentioned briefly. In other words, differences between the second active contact CA 2 and the first active contact CA 1 will be mainly described.
  • the second active contact CA 2 may include first and second sub-contacts SC 1 and SC 2 . Unlike the first active contact CA 1 , one sidewall of the first sub-contact SC 1 of the second active contact CA 2 may be aligned with one sidewall of the second sub-contact SC 2 of the second active contact CA 2 (see FIG. 3B ). In other words, the first sub-contact SC 1 of the second active contact CA 2 may have a first sidewall SW 1 , and the second sub-contact SC 2 of the second active contact CA 2 may have a second sidewall SW 2 adjacent to the first sidewall SW 1 .
  • the first sidewall SW 1 and the second sidewall SW 2 may be coplanar with each other.
  • a second conductive line CBL 2 may be disposed on the second active contact CA 2 .
  • a second via V 2 may be disposed between the second active contact CA 2 and the second conductive line CBL 2 .
  • the second via V 2 may be provided on the second active contact CA 2 .
  • the second sub-contact SC 2 of the second active contact CA 2 may act as a pad on which the second via V 2 is disposed.
  • the third active contact CA 3 may include first and second sub-contacts SC 1 and SC 2 . Unlike the first active contact CA 1 , the first sub-contact SC 1 of the third active contact CA 3 may extend in the first direction D 1 to penetrate the second sub-contact SC 2 in plan view. In other words, as illustrated in FIG. 3E , the first sub-contact SC 1 of the third active contact CA 3 may laterally protrude from one sidewall of the second sub-contact SC 2 of the third active contact CA 3 when viewed from a cross-sectional view taken along the first direction D 1 . This is because the first sub-contact SC 1 of the third active contact CA 3 may be offset from the second sub-contact SC 2 of the third active contact CA 3 in a direction opposite to the first direction D 1 .
  • a third conductive line CBL 3 may be disposed on the third active contact CA 3 .
  • a third via V 3 may be disposed between the third active contact CA 3 and the third conductive line CBL 3 .
  • the third via V 3 may be provided on the third active contact CA 3 .
  • the second sub-contact SC 2 of the third active contact CA 3 may act as a pad on which the third via V 3 is disposed.
  • the fourth active contact CA 4 may include first and second sub-contacts SC 1 and SC 2 .
  • the second sub-contact SC 2 of the fourth active contact CA 4 may be disposed on the conductive connection pattern TS connecting the fourth and fifth source/drain regions SD 4 and SD 5 to each other.
  • the second sub-contact SC 2 of the fourth active contact CA 4 may not include a vertical extension due to the conductive connection pattern TS.
  • the first sub-contact SC 1 of the fourth active contact CA 4 may be connected to two conductive connection patterns TS adjacent to each other.
  • the third, fourth and fifth source/drain regions SD 3 , SD 4 and SD 5 may be electrically connected to each other through the fourth active contact CA 4 and the conductive connection patterns TS.
  • a fourth conductive line CBL 4 may be disposed on the fourth active contact CA 4 .
  • a fourth via V 4 may be disposed between the fourth active contact CA 4 and the fourth conductive line CBL 4 .
  • the fourth via V 4 may be provided on the fourth active contact CA 4 .
  • the second sub-contact SC 2 of the fourth active contact CA 4 may act as a pad on which the fourth via V 4 is disposed.
  • FIGS. 4, 6, and 8 are plan views illustrating methods for manufacturing semiconductor devices according to example embodiments of the inventive concepts.
  • FIGS. 5A, 7A, and 9A are cross-sectional views taken along lines A-A′ of FIGS. 4, 6, and 8 , respectively.
  • FIGS. 5B, 7B, and 9B are cross-sectional views taken along lines B-B′ of FIGS. 4, 6, and 8 , respectively.
  • FIGS. 5C, 7C, and 9C are cross-sectional views taken along lines C-C′ of FIGS. 4, 6, and 8 , respectively.
  • FIGS. 7D and 9D are cross-sectional views taken along lines D-D′ of FIGS. 6 and 8 , respectively.
  • FIGS. 7E and 9E are cross-sectional views taken along lines E-E′ of FIGS. 6 and 8 , respectively.
  • a first device isolation layer ST 1 may be formed in a substrate 100 to define logic cells.
  • second device isolation layers ST 2 may be formed in the substrate 100 of each of the logic cells to define a plurality of active patterns FN 1 to FN 6 .
  • the second device isolation layers ST 2 may extend in the second direction D 2 , so the active patterns FN 1 to FN 6 may extend in the second direction D 2 and may be spaced apart from each other in the first direction D 1 .
  • the substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a SOI substrate.
  • the first and second device isolation layers ST 1 and ST 2 may be formed by a shallow-trench isolation (STI) process and may include, for example, a silicon oxide layer.
  • STI shallow-trench isolation
  • Each of the first and second device isolation layers ST 1 and ST 2 may have a depth in a direction opposite to the third direction D 3 .
  • the third direction D 3 may be perpendicular to the first and second directions D 1 and D 2 and may be perpendicular to the top surface of the substrate 100 .
  • the depths of the second device isolation layers ST 2 may be smaller than that of the first device isolation layer ST 1 .
  • the second device isolation layers ST 2 may be formed by a process different from a process of forming the first device isolation layer ST 1 .
  • the first and second device isolation layers ST 1 and ST 2 may be formed at the same time, and the second device isolation layers ST 2 may have the substantially same depth as the first device isolation layer ST 1 .
  • the active patterns FN 1 to FN 6 may include first to sixth active patterns FN 1 to FN 6 .
  • the active patterns FN 1 to FN 6 may include fin portions protruding from between the second device isolation layers ST 2 .
  • the fin portions may correspond to upper portions of the active patterns FN 1 to FN 6 .
  • Gate electrodes G 1 to G 6 may be disposed on the substrate 100 and may extend in the first direction D 1 to intersect the active patterns FN 1 to FN 6 .
  • the gate electrodes G 1 to G 6 may include first to sixth gate electrodes G 1 to G 6 which extend in parallel to each other and intersect the active patterns FN 1 to FN 6 .
  • the gate electrodes G 1 to G 6 may be spaced apart from each other in the second direction D 2 .
  • a gate insulating pattern GI may be formed between each of the gate electrodes G 1 to G 6 and the substrate 100 .
  • Gate spacers GS may be formed on both sidewalls of each of the gate electrodes G 1 to G 6 .
  • the gate insulating pattern GI may extend to be disposed between each of the gate electrodes G 1 to G 6 and the gate spacers GS.
  • Forming the gate electrodes G 1 to G 6 , the gate insulating patterns GI, and the gate spacers GS may include forming sacrificial gate patterns on the substrate 100 , forming the gate spacers GS on both sidewalls of each of the sacrificial gate patterns, and replacing the sacrificial gate patterns with the gate insulating patterns GI and the gate electrodes G 1 to G 6 .
  • the gate insulating patterns GI may include at least one of a silicon oxide layer, a silicon oxynitride layer, or a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer.
  • the gate electrodes G 1 to G 6 may include at least one of a doped semiconductor material, a metal, or a conductive metal nitride.
  • the gate spacers GS may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer.
  • ion implantation processes may be performed on the substrate 100 having the gate electrodes G 1 to G 6 to form source/drain regions SD 1 to SD 6 in active patterns FN 1 to FN 6 at both sides of each of the gate electrodes G 1 to G 6 .
  • First to sixth source/drain regions SD 1 to SD 6 may be respectively formed in the first to sixth active patterns FN 1 to FN 6 at both sides of each of the gate electrodes G 1 to G 6 .
  • the source/drain regions SD 1 to SD 6 may not be formed in the fin portions of the active patterns FN 1 to FN 6 , which are disposed under and overlap with the gate electrodes G 1 to G 6 .
  • the second, third and sixth active patterns FN 2 , FN 3 and FN 6 may define PMOSFET regions, so the second, third and sixth source/drain regions SD 2 , SD 3 and SD 6 may be doped with P-type dopants.
  • the first, fourth and fifth active patterns FN 1 , FN 4 and FN 5 may define NMOSFET regions, so the first, fourth and fifth source/drain regions SD 1 , SD 4 and SD 5 may be doped with N-type dopants.
  • forming the source/drain regions SD 1 to SD 6 may include forming epitaxial patterns on the active patterns FN 1 to FN 6 .
  • Forming the epitaxial patterns may include removing upper portions of the active patterns FN 1 to FN 6 at both sides of each of the gate electrodes G 1 to G 6 , and performing a selective epitaxial growth (SEG) process using exposed lower portions of the active patterns FN 1 to FN 6 as seeds or seed layers.
  • the epitaxial patterns may be doped in-situ or may be doped using ion implantation processes.
  • the epitaxial patterns may correspond to upper portions of the active patterns FN 1 to FN 6 . In other words, the upper portions of the active patterns FN 1 to FN 6 at both sides of each of the gate electrodes G 1 to G 6 may be replaced with or may otherwise include the epitaxial patterns.
  • a first interlayer insulating layer 110 may be formed on the substrate 100 to extend on or cover the source/drain regions SD 1 to SD 6 and to fill spaces between the gate electrodes G 1 to G 6 .
  • the epitaxial patterns and the first interlayer insulating layer 110 may be formed before replacing the sacrificial gate patterns with the gate insulating patterns GI and the gate electrodes G 1 to G 6 .
  • the first interlayer insulating layer 110 may be planarized to expose top surfaces of the sacrificial gate patterns, and then, the sacrificial gate patterns may be replaced with the gate insulating patterns GI and the gate electrodes G 1 to G 6 .
  • a capping layer GP may be formed on the first interlayer insulating layer 110 to extend on or cover top surfaces of the gate electrodes G 1 to G 6 .
  • the capping layer GP may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer.
  • a second interlayer insulating layer 115 may be formed on the capping layer GP.
  • Each of the first and second interlayer insulating layers 110 and 115 may include at least one of a silicon oxide layer or a silicon oxynitride layer.
  • Conductive connection patterns TS may be formed to penetrate the first and second interlayer insulating layers 110 and 115 and the capping layer GP.
  • the conductive connection patterns TS may be connected to the source/drain regions SD 1 to SD 6 .
  • Forming the conductive connection patterns TS may include forming recess regions penetrating the first and second interlayer insulating layers 110 and 115 and the capping layer GP to expose the source/drain regions SD 1 to SD 6 , filling the recess regions with a conductive material, and planarizing the conductive material until the second interlayer insulating layer 115 is exposed.
  • a first barrier layer BM 1 may be deposited on inner surfaces of the recess regions before the recess regions are filled with the conductive material.
  • the first barrier layer BM 1 may include Ti/TiN.
  • the conductive connection patterns TS may include a metal silicide.
  • the conductive connection patterns TS may include at least one of titanium silicide, tantalum silicide, or tungsten silicide.
  • the conductive connection patterns TS may further include a metal layer.
  • the metal layer may include at least one of a titanium layer, a tantalum layer, or a tungsten layer.
  • the conductive connection patterns TS may include the metal silicide layer and the metal layer disposed on the metal silicide layer.
  • some of the conductive connection patterns TS may be disposed to correspond to some of the source/drain regions SD 1 to SD 6 , respectively. Others of the conductive connection patterns TS may electrically connect the source/drain regions, spaced apart from each other in the first direction D 1 , to each other. Top surfaces of the conductive connection patterns TS may be disposed at a higher level than the top surfaces of the gate electrodes G 1 to G 6 .
  • a first etch stop layer ES 1 and a third interlayer insulating layer 120 may be sequentially formed on the resultant structure including the conductive connection patterns TS.
  • the first etch stop layer ES 1 may include SiCN, and the third interlayer insulating layer 120 may include at least one of a silicon oxide layer or a silicon oxynitride layer.
  • the first etch stop layer ES 1 may reduce or substantially prevent a metal included in the conductive connection patterns TS from being diffused through the exposed top surfaces of the conductive connection patterns TS.
  • the third interlayer insulating layer 120 and the first etch stop layer ES 1 may be patterned using a first photo mask to form first sub-contact holes SH 1 and source/drain contact holes SDH.
  • the first sub-contact holes SH 1 and the source/drain contact holes SDH may be formed using a first photolithography process at the same time.
  • the process of patterning the third interlayer insulating layer 120 and the first etch stop layer ES 1 may be performed until a top surface of the second interlayer insulating layer 115 and top surfaces of the conductive connection patterns TS are exposed.
  • the first sub-contact holes SH 1 may be formed between the first and second gate electrodes G 1 and G 2 , between the third and fourth gate electrodes G 3 and G 4 , and between the fifth and sixth gate electrodes G 5 and G 6 , respectively, in plan view. Some of the first sub-contact holes SH 1 may be formed on the second source/drain regions SD 2 , respectively, and another of the first sub-contact holes SH 1 may be formed on the third and fourth source/drain regions SD 3 and SD 4 .
  • the first sub-contact holes SH 1 may have bar shapes extending in the first direction D 1 in plan view.
  • the source/drain contact holes SDH may have the substantially same depth as the first sub-contact holes SH 1 . In addition, source/drain contact holes SDH may have the substantially same width as the first sub-contact holes SH 1 .
  • the source/drain contact holes SDH may expose the conductive connection patterns TS at both sides of the gate electrodes G 1 to G 6 , like the first sub-contact holes SH 1 .
  • the source/drain contact holes SDH may have bar shapes that extend along the top surfaces of the conductive connection patterns TS in the first direction D 1 .
  • a mask layer 150 may be formed on the third interlayer insulating layer 120 to fill the first sub-contact holes SH 1 and the source/drain contact holes SDH.
  • the mask layer 150 may include, for example, a spin-on-hardmask (SOH) material.
  • the mask layer 150 may be patterned using a second photo mask to form second sub-contact holes SH 2 and gate contact holes CBH.
  • the second photo mask may be different from the first photo mask described above.
  • the second sub-contact holes SH 2 and the gate contact holes CBH may be formed using a second photolithography process at the same time.
  • the first to third interlayer insulating layers 110 , 115 and 120 and the first etch stop layer ES 1 may also be patterned while the mask layer 150 is patterned.
  • the process of patterning the mask layer 150 may be performed until the gate electrodes G 1 to G 6 are exposed through the gate contact holes CBH. In other words, portions of the capping layer GP disposed on the gate electrodes G 1 to G 6 may be completely removed when the gate contact holes CBH are formed.
  • Each of some of the second sub-contact holes SH 2 may be formed between the second and third source/drain regions SD 2 and SD 3 in plan view. Another of the second sub-contact holes SH 2 may be formed between the fourth and fifth source/drain regions SD 4 and SD 5 in plan view.
  • the second sub-contact holes SH 2 may be connected to the first sub-contact holes SH 1 , respectively.
  • a first communicating hole CH 1 may be formed between the first and second gate electrodes G 1 and G 2
  • second and fourth communicating holes CH 2 and CH 4 may be formed between the third and fourth gate electrodes G 3 and G 4
  • a third communicating hole CH 3 may be formed between the fifth and sixth gate electrodes G 5 and G 6 .
  • each of the first to fourth communicating holes CH 1 to CH 4 may include the first sub-contact hole SH 1 and the second sub-contact hole SH 2 .
  • the second sub-contact hole SH 2 may include a vertical extension hole VH extending toward the top surface of the substrate 100 .
  • a bottom surface of the vertical extension hole VH may be disposed at a level between a top surface of the first interlayer insulating layer 110 and a top surface of the second device isolation layer ST 2 .
  • the first sub-contact holes SH 1 may be formed using the first photolithography process which uses first layouts defining positions of the first sub-contact holes SH 1 .
  • the second sub-contact holes SH 2 may be formed using the second photolithography process which uses second layouts defining positions of the second sub-contact holes SH 2 .
  • the second layouts may overlap with portions of the first layouts, respectively.
  • portions of bottom surfaces of the first sub-contact holes SH 1 may be etched again during the patterning process using the second photolithography process (double-etching).
  • an overlapping region of the second and first sub-contact holes SH 2 and SH 1 may be over-etched to form the vertical extension hole VH.
  • the vertical extension hole VH may also overlap with the first sub-contact hole SH 1 in plan view.
  • the bottom surface of the vertical extension hole VH may be positioned at a first height H 1 from the top surface of the second device isolation layer ST 2
  • a bottom surface of the second sub-contact hole SH 2 may be positioned at a second height H 2 from the top surface of the second device isolation layer ST 2
  • the second height H 2 may be higher than the first height H 1
  • one sidewall of the second sub-contact SH 2 of the first communicating hole CH 1 may have a stepped profile.
  • a bottom surface of each of the gate contact holes CBH may be positioned at a third height H 3 from the top surfaces of the first and second device isolation layers ST 1 and ST 2 .
  • the third height H 3 may be the substantially same as or higher than the second height H 2 .
  • the mask layer 150 may be removed.
  • the mask layer 150 may be removed using an ashing process and/or a strip process.
  • a second barrier layer BM 2 and a conductive layer may be formed on the third interlayer insulating layer 120 to fill the first to fourth communicating holes CH 1 to CH 4 , the gate contact holes CBH, and the source/drain contact holes SDH.
  • the second barrier layer BM 2 may include Ti/TiN, and the conductive layer may include at least one of a doped semiconductor material, a metal, or a conductive metal nitride.
  • the conductive layer and the second barrier layer BM 2 may be planarized until the third interlayer insulating layer 120 is exposed, thereby forming first to fourth active contacts CA 1 to CA 4 in the first to fourth communicating holes CH 1 to CH 4 , gate contacts CB in the gate contact holes CBH, and source/drain contacts SDC in the source/drain contact holes SDH, respectively.
  • each of the first to fourth active contacts CA 1 to CA 4 may include first and second sub-contacts SC 1 and SC 2 constituting one body.
  • Each of the second barrier layers BM 2 may extend on or surround each of the first to fourth active contacts CA 1 to CA 4 .
  • portions of the second barrier layers BM 2 may be disposed between the conductive connection patterns TS and the active contacts CA 1 to CA 4 , respectively.
  • a second etch stop layer ES 2 , a fourth interlayer insulating layer 130 , a third etch stop layer ES 3 , and a fifth interlayer insulating layer 140 may be sequentially formed on the third interlayer insulating layer 120 to extend on or cover the first to fourth active contacts CA 1 to CA 4 , the gate contacts CB, and the source/drain contacts SDC.
  • Vias V 1 to V 5 and conductive lines CBL 1 to CBL 5 may be formed.
  • the vias V 1 to V 5 may penetrate the fourth interlayer insulating layer 130 , and the conductive lines CBL 1 to CBL 5 may be formed in the fifth interlayer insulating layer 140 .
  • the first to fourth vias V 1 to V 4 may be formed on the first to fourth active contacts CA 1 to CA 4 , respectively.
  • Each of the first to fourth active contacts CA 1 to CA 4 may include the second sub-contact SC 2 which is formed simultaneously with the gate contacts CB.
  • the second sub-contacts SC 2 may further enlarge planar contact areas of the first to fourth active contacts CA 1 to CA 4 , and thus, misalignment of the first to fourth vias V 1 to V 4 may be reduced or minimized or substantially prevented. This means that a margin of the process for forming the first to fourth vias V 1 to V 4 may be improved.
  • contact areas of the active contacts CA 1 to CA 4 and the vias V 1 to V 4 may be increased by the wide planar areas of the active contacts CA 1 to CA 4 .
  • FIG. 10 is a schematic block diagram illustrating an electronic system including semiconductor devices according to example embodiments of the inventive concepts.
  • an electronic system 1100 may include a controller 1110 , an input/output (I/O) device 1120 , a memory device 1130 , an interface unit 1140 , and a data bus 1150 . At least two of the controller 1110 , the I/O device 1120 , the memory device 1130 , and the interface unit 1140 may communicate with each other through the data bus 1150 .
  • the data bus 1150 may correspond to a path through which electrical signals are transmitted.
  • the controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, or other logic devices having a similar function to any one thereof.
  • the I/O device 1120 may include a keypad, a keyboard and/or a display device.
  • the memory device 1130 may store data and/or commands.
  • the memory device 1130 may include a non-volatile memory device (e.g., a flash memory device, a phase change memory device, and/or a magnetic memory device).
  • the memory device 1130 may further include a volatile memory device.
  • the memory device 1130 may include a SRAM device including semiconductor devices according to the aforementioned embodiments of the inventive concepts.
  • the memory device 1130 may be omitted according to application of the electronic system 1100 or an electronic product implemented with the electronic system 1100 .
  • the interface unit 1140 may transmit electrical data to a communication network or may receive electrical data from a communication network.
  • the interface unit 1140 may operate wirelessly or by cable.
  • the interface unit 1140 may include an antenna or a wireless/cable transceiver.
  • Semiconductor devices according to the aforementioned embodiments of the inventive concepts may be applied to the controller 1110 or a portion of the I/O device 1120 .
  • the electronic system 1100 may further include a fast dynamic random access memory (DRAM) device and/or a fast SRAM device which acts as a cache memory for improving an operation of the controller 1110 .
  • DRAM fast dynamic random access memory
  • FIG. 11 is a schematic block diagram illustrating an electronic device including semiconductor devices according to example embodiments of the inventive concepts.
  • an electronic device 1200 may include a semiconductor chip 1210 .
  • the semiconductor chip 1210 may include a processor 1211 , an embedded memory 1213 , and a cache memory 1215 .
  • the processor 1211 may include one or more processor cores C 1 to Cn.
  • the one or more process cores C 1 to Cn may process electrical data and electrical signals.
  • the processor cores C 1 to Cn may include a plurality of logic cells.
  • the logic cells may include semiconductor devices according to the above mentioned embodiments of the inventive concepts.
  • the electronic device 1200 may perform a specific function using the processed data and signals.
  • the processor 1211 may be an application processor.
  • the embedded memory 1213 may exchange first data DAT 1 with the processor 1211 .
  • the first data DAT 1 may be data processed or to be processed by the one or more processor cores C 1 to Cn.
  • the embedded memory 1213 may manage the first data DAT 1 .
  • the embedded memory 1213 may buffer the first data DAT 1 .
  • the embedded memory 1213 may act as a buffer memory or working memory of the processor 1211 .
  • the electronic device 1200 may be applied to a wearable electronic device.
  • the wearable electronic device may mainly perform functions requiring a relatively small quantity of operations.
  • the embedded memory 1213 may not have a large buffer capacity.
  • the embedded memory 1213 may be a SRAM.
  • An operating speed of the SRAM may be faster than that of a DRAM.
  • the SRAM is embedded in the semiconductor chip 1210 , it is possible to realize the electronic device 1200 having a small size and a fast operating speed.
  • the SRAM may include semiconductor devices according to the above mentioned embodiments of the inventive concepts.
  • the cache memory 1215 may be mounted on the semiconductor chip 1210 along with the one or more process cores C 1 to Cn.
  • the cache memory 1215 may store cache data DATc.
  • the cache data DATc may be data used by the one or more process cores C 1 to Cn.
  • the cache memory 1215 may have a relatively small capacity but may have a very fast operating speed.
  • the cache memory 1215 may include a SRAM including semiconductor devices according to the above mentioned embodiments of the inventive concepts. When the cache memory 1215 is used, it is possible to reduce an accessing number and an accessing time of the processor 1211 with respect to the embedded memory 1213 . Thus, the operating speed of the electronic device 1200 may be improved when the cache memory 1215 is used.
  • the cache memory 1215 is separated from the processor 1211 for the purpose of ease and convenience in explanation. However, in other embodiments, the cache memory 1215 may be configured to be included in the processor 1211 . In other words, embodiments of the inventive concepts are not limited to the embodiment illustrated in FIG. 11 .
  • the processor 1211 , the embedded memory 1213 , and the cache memory 1215 may transmit electrical data on the basis of at least one of various interface protocols.
  • the processor 1211 , the embedded memory 1213 , and the cache memory 1215 may transmit electrical data on the basis of at least one interface protocol of universal serial bus (USB), small computer system interface (SCSI), peripheral component interconnect (PCI) express, advanced technology attachment (ATA), parallel ATA (PATA), serial ATA (SATA), serial attached SCSI (SAS), integrated drive electronics (IDE), or universal flash storage (UFS).
  • USB universal serial bus
  • SCSI small computer system interface
  • PCI peripheral component interconnect express
  • ATA advanced technology attachment
  • PATA parallel ATA
  • SATA serial ATA
  • SAS serial attached SCSI
  • IDE integrated drive electronics
  • UFS universal flash storage
  • FIGS. 12 to 14 illustrate embodiments of multimedia devices including semiconductor devices according to example embodiments of the inventive concepts.
  • the electronic system 1100 of FIG. 10 and/or the electronic device 1200 of FIG. 11 may be applied to a mobile or smart phone 2000 illustrated in FIG. 12 , a tablet or smart table 3000 illustrated in FIG. 13 , and/or a notebook computer 4000 illustrated in FIG. 14 .
  • the enlarged active contact disposed on the source/drain region may be formed by less complex processes.
  • the misalignment of the via on the active contact may be reduced or substantially prevented and the process margin may be improved.
  • the reliability of semiconductor devices may be improved.
  • the contact area between the active contact and the via may be increased to reduce the resistance of semiconductor devices.

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170287986A1 (en) * 2016-04-05 2017-10-05 Samsung Display Co., Ltd. Display panel and method of manufacturing the same
US10957765B2 (en) 2017-10-19 2021-03-23 Samsung Electronics Co., Ltd. Semiconductor devices having power rails
US10977417B2 (en) * 2018-09-28 2021-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure, device, and method
US11328957B2 (en) * 2020-02-25 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106784390A (zh) * 2017-03-06 2017-05-31 京东方科技集团股份有限公司 用于显示面板的基板及其制作方法、显示面板及封装方法
KR20230006054A (ko) * 2017-11-30 2023-01-10 인텔 코포레이션 진보된 집적 회로 구조체 제조를 위한 핀 패터닝
EP3723127A1 (en) * 2019-04-10 2020-10-14 IMEC vzw A standard cell device and a method for forming an interconnect structure for a standard cell device
US11062739B2 (en) * 2019-06-27 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor chip having memory and logic cells
KR20210042222A (ko) * 2019-10-08 2021-04-19 삼성전자주식회사 반도체 소자

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010009805A1 (en) * 2000-01-21 2001-07-26 Samsung Electronics Co., Ltd. Borderless contact structure and method of forming the same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685080A (ja) 1992-08-31 1994-03-25 Nippon Steel Corp 半導体装置及びその製造方法
JPH0831932A (ja) 1994-07-12 1996-02-02 Hitachi Ltd 半導体集積回路装置の製造方法
KR100266005B1 (ko) 1997-09-04 2000-09-15 김영환 반도체소자의 접촉홀 형성방법
JP4477197B2 (ja) 2000-05-18 2010-06-09 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP2003163214A (ja) 2001-11-26 2003-06-06 Mitsubishi Electric Corp 半導体装置及びその製造方法
DE10303771B3 (de) * 2003-01-30 2004-09-30 Infineon Technologies Ag Stegfeldeffekttransistor (FinFet) und Verfahren zur Herstellung von Stegfeldeffekttransistoren
JP3795882B2 (ja) 2003-10-06 2006-07-12 株式会社東芝 半導体装置およびその製造方法
KR100506460B1 (ko) * 2003-10-31 2005-08-05 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
JP4316358B2 (ja) 2003-11-27 2009-08-19 株式会社東芝 半導体記憶装置及びその製造方法
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7795096B2 (en) * 2006-12-29 2010-09-14 Qimonda Ag Method of forming an integrated circuit with two types of transistors
US7910994B2 (en) 2007-10-15 2011-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for source/drain contact processing
DE102008059500B4 (de) 2008-11-28 2010-08-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Mehr-Gatetransistors mit homogen silizidierten Stegendbereichen
JP5465958B2 (ja) * 2009-09-01 2014-04-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8987831B2 (en) * 2012-01-12 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. SRAM cells and arrays
US9105691B2 (en) 2013-04-09 2015-08-11 International Business Machines Corporation Contact isolation scheme for thin buried oxide substrate devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010009805A1 (en) * 2000-01-21 2001-07-26 Samsung Electronics Co., Ltd. Borderless contact structure and method of forming the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170287986A1 (en) * 2016-04-05 2017-10-05 Samsung Display Co., Ltd. Display panel and method of manufacturing the same
US10332938B2 (en) * 2016-04-05 2019-06-25 Samsung Display Co., Ltd. Display panel capable of reducing color variation and method of manufacturing the same
US10957765B2 (en) 2017-10-19 2021-03-23 Samsung Electronics Co., Ltd. Semiconductor devices having power rails
US10977417B2 (en) * 2018-09-28 2021-04-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure, device, and method
US20210233990A1 (en) * 2018-09-28 2021-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure, device, and method
US11720737B2 (en) * 2018-09-28 2023-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure, device, and method
US11328957B2 (en) * 2020-02-25 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US20220254688A1 (en) * 2020-02-25 2022-08-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing semiconductor device

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US10366997B2 (en) 2019-07-30
KR20160118450A (ko) 2016-10-12
KR102311929B1 (ko) 2021-10-15
US20180108663A1 (en) 2018-04-19
US20190296027A1 (en) 2019-09-26

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