US20150243438A1 - Multilayer ceramic capacitor and board having the same - Google Patents

Multilayer ceramic capacitor and board having the same Download PDF

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Publication number
US20150243438A1
US20150243438A1 US14/601,724 US201514601724A US2015243438A1 US 20150243438 A1 US20150243438 A1 US 20150243438A1 US 201514601724 A US201514601724 A US 201514601724A US 2015243438 A1 US2015243438 A1 US 2015243438A1
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United States
Prior art keywords
ceramic
conductive layer
lead
portions
layer
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Abandoned
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US14/601,724
Inventor
Young Ghyu Ahn
Hyun Tae Kim
Kyo Kwang LEE
Jin Kim
Byoung HWA Lee
Hwi Geun IM
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Priority to KR1020140023639A priority Critical patent/KR20140039016A/en
Priority to KR10-2014-0023639 priority
Priority to KR1020140143390A priority patent/KR101532180B1/en
Priority to KR10-2014-0143390 priority
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD. reassignment SAMSUNG ELECTRO-MECHANICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AHN, YOUNG GHYU, IM, HWI GEUN, KIM, HYUN TAE, KIM, JIN, LEE, BYOUNG HWA, LEE, KYO KWANG
Publication of US20150243438A1 publication Critical patent/US20150243438A1/en
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/005Electrodes
    • H01G4/008Selection of materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • H01G2/065Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/14Protection against electric or thermal overload
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/005Electrodes
    • H01G4/012Form of non-self-supporting electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10015Non-printed capacitor
    • Y02P70/611

Abstract

A multilayer ceramic capacitor and a board having the same are provided. The multilayer ceramic capacitor includes three external electrodes including a conductive layer, a nickel plating layer, and a tin plating layer sequentially stacked on a mounting surface of the ceramic body, and spaced apart from each other. When an outermost portion of a lead-out portion of an internal electrode exposed to the mounting surface is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is bp, (b−bp)/a satisfies 0.264≦(b−bp)/a≦0.638.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims the priority and benefit of Korean Patent Application No. 10-2014-0023639 filed on Feb. 27, 2014 and Korean Patent Application No. 10-2014-0143390 filed on Oct. 22, 2014, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
  • BACKGROUND
  • The present disclosure relates to a multilayer ceramic capacitor and a board having the same.
  • As electronic components using a ceramic material, capacitors, inductors, a piezoelectric material, varistors, thermistors, and the like may be used.
  • Among these ceramic electronic components, multilayer ceramic capacitors (MLCCs) have advantages such as a small size, high capacitance, ease of mounting, and the like.
  • The multilayer ceramic capacitors are chip-shaped condensers mounted on boards of several electronic products such as computers, personal digital assistants (PDAs), cellular phones, and the like, to serve to be charged with electricity or discharge electricity, and have various sizes and multilayer forms according to the use and capacitance thereof.
  • Particularly, in accordance with the recent trend toward the miniaturization of electronic products, micro-miniaturized and super high capacitance multilayer ceramic capacitors have been required in electronic products.
  • Therefore, multilayer ceramic capacitors in which thicknesses of dielectric layers and internal electrodes are decreased for implementations of micro-miniaturized electronic products and a number of dielectric layers are stacked for implementations of super high capacitance electronic products have been manufactured.
  • In this case, a plating solution may infiltrate through a portion of an external electrode having a thin thickness and a low degree of densification on a surface of the capacitor to which the internal electrode is exposed, such that moisture resistance reliability, high-temperature load reliability, or the like, may be deteriorated.
  • SUMMARY
  • Some embodiments in the present disclosure may provide a multilayer ceramic capacitor capable of preventing deterioration of reliability while maintaining low equivalent series inductance (ESL) characteristics, and a board having the same.
  • According to some embodiments in the present disclosure, a multilayer ceramic capacitor may include: three external electrodes including a conductive layer, a nickel plating layer, and a tin plating layer sequentially stacked on a mounting surface of the ceramic body, and disposed to be spaced apart from each other, wherein when an outermost portion of a lead-out portion of an internal electrode exposed to the mounting surface of the ceramic body is defined as P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is defined as a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is defined as b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is defined as bp, (b−bp)/a may satisfy 0.264≦(b−bp)/a≦0.638.
  • BRIEF DESCRIPTION OF DRAWINGS
  • The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a perspective view schematically illustrating a multilayer ceramic capacitor according to an exemplary embodiment in the present disclosure in a state in which the multilayer ceramic capacitor is overturned;
  • FIG. 2 is a perspective view illustrating a ceramic body of the multilayer ceramic capacitor of FIG. 1 in a state in which the ceramic body is overturned;
  • FIG. 3 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 1 in a state in which external electrodes thereof are omitted;
  • FIG. 4 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 1;
  • FIG. 5 is an enlarged side cross-sectional view illustrating part A of FIG. 4;
  • FIG. 6 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure;
  • FIG. 7 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 6 in a state in which external electrodes thereof are omitted;
  • FIG. 8 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 6;
  • FIG. 9 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure;
  • FIG. 10 is a perspective view illustrating a ceramic body of the multilayer ceramic capacitor of FIG. 9;
  • FIG. 11 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 9 in a state in which external electrodes thereof are omitted;
  • FIG. 12 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 9;
  • FIG. 13 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure;
  • FIG. 14 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 13 in a state in which external electrodes thereof are omitted;
  • FIG. 15 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 13;
  • FIG. 16 is a perspective view illustrating a form in which the multilayer ceramic capacitor of FIG. 9 is mounted on a substrate; and
  • FIG. 17 is a cross-sectional view illustrating the form in which the multilayer ceramic capacitor of FIG. 9 is mounted on the substrate.
  • DETAILED DESCRIPTION
  • Exemplary embodiments in the present disclosure will now be described in detail with reference to the accompanying drawings.
  • The disclosure may, however, be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
  • In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements.
  • A multilayer ceramic capacitor according to an exemplary embodiment in the present disclosure may include: a ceramic body including a plurality of dielectric layers stacked therein; a plurality of first and second internal electrodes alternately disposed in the ceramic body, each first and second internal electrodes interposed between the respective dielectric layer, and the first and second internal electrodes including first and second body portions overlapped with each other and first and second lead-out portions extended from the first and second body portions to be exposed to one surface of the ceramic body, respectively; and first and second external electrodes formed on the one surface of the ceramic body to be connected to the first and second lead-out portions, respectively. In the first and second external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the one surface of the ceramic body, and when an outermost portion of one of the first and second lead-out portions exposed to the one surface of the ceramic body is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is bp, (b−bp)/a satisfies 0.264≦(b−bp)/a≦0.638.
  • In addition, when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is c, b/c satisfies 0.930≦b/c≦5.391.
  • Directions of a hexahedron will be defined in order to clearly describe exemplary embodiments in the present disclosure. L, W and T shown in the accompanying drawings refer to a length direction, a width direction, and a thickness direction, respectively.
  • Multilayer Ceramic Capacitor
  • FIG. 1 is a perspective view schematically illustrating a multilayer ceramic capacitor according to an exemplary embodiment in the present disclosure in a state in which the multilayer ceramic capacitor is overturned, FIG. 2 is a perspective view illustrating a ceramic body of the multilayer ceramic capacitor of FIG. 1 in a state in which the ceramic body is overturned, FIG. 3 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 1 in a state in which external electrodes thereof are omitted, and FIG. 4 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 1.
  • Referring to FIGS. 1 through 4, the multilayer ceramic capacitor 100 according to the exemplary embodiment in the present disclosure may include a ceramic body 110 in which a plurality of dielectric layers 111 are stacked in the width direction of the ceramic body, an active layer including a plurality of first and second internal electrodes 120 and 130, and first to third external electrodes 141 to 143.
  • The multilayer ceramic capacitor 100 according to the exemplary embodiment in the present disclosure may be considered as a so-called 3-terminal capacitor having a total of 3 external terminals.
  • The ceramic body 110 may be formed by stacking the plurality of dielectric layers 111 in the width direction and then sintering the stacked dielectric layers 111, and a shape thereof is not particularly limited, but may be a hexahedral shape as shown in the accompanying drawings.
  • The ceramic body 110 may include first and second main surfaces S1 and S2 opposing each other in the thickness direction, first and second side surfaces S5 and S6 connecting the first and second main surfaces S1 and S2 to each other and opposing each other in the width direction, and first and second end surfaces S3 and S4 opposing each other in the length direction.
  • Hereinafter, in the exemplary embodiment of the present disclosure, a mounting surface of the multilayer ceramic capacitor 100 may be the first main surface S1 of the ceramic body 110.
  • However, a shape and a dimension of the ceramic body 110 and the number of stacked dielectric layers 111 are not limited to those of the exemplary embodiment in the present disclosure shown in the accompanying drawings.
  • The plurality of dielectric layers 111 configuring the ceramic body 110 may be in a sintered state. Adjacent dielectric layers 111 may be integrated so as to be difficult to confirm a boundary therebetween without using a scanning electron microscope (SEM).
  • This ceramic body 110 may include the active layer including the plurality of internal electrodes as a part contributing to forming capacitance of the capacitor and the cover layers 112 and 113 formed on both sides of the active layer in the width direction as margin parts.
  • The active layer may be formed by alternately stacking the plurality of first and second internal electrodes 120 and 130 in the width direction with the respective dielectric layer 111 interposed therebetween.
  • In this case, a thickness of the dielectric layer 111 may be optionally changed according to the capacitance design of the multilayer ceramic capacitor 100, but a thickness of a single layer may be 0.4 to 3.0 μm after sintering. However, the present disclosure is not limited thereto.
  • Further, the dielectric layer 111 may contain ceramic powder having high permittivity, for example, barium titanate (BaTiO3)-based powder or strontium titanate (SrTiO3)-based powder, but the present disclosure is not limited thereto as long as sufficient capacitance may be obtained.
  • In addition, when necessary, a ceramic additive, an organic solvent, a plasticizer, a binder, a dispersant, and the like, may be further added to the dielectric layer 111 together with the ceramic powder.
  • In this case, an average particle size of ceramic powder particles used to form the dielectric layer 111 is not particularly limited and may be adjusted according to the purpose of the present disclosure. For example, the average particle size of the ceramic powder particle may be controlled to be equal to 400 nm or less, but the present disclosure is not limited thereto.
  • The cover layers 112 and 113 may have the same material and configuration as those of the dielectric layer 111 except that internal electrodes are not included therein.
  • In addition, the cover layers 112 and 113 may be formed by further stacking a single dielectric layer, or two or more dielectric layers, on both sides of the active layer in the width direction, respectively, and may serve to prevent the first and second internal electrodes 120 and 130 from being damaged due to physical or chemical stress.
  • The first and second internal electrodes 120 and 130 having different polarities may be formed in the ceramic body 110 and disposed so as to face each other with the respective dielectric layer 111 interposed therebetween.
  • In this case, the first and second internal electrodes 120 and 130 may be electrically insulated from each other by the dielectric layer 111 disposed therebetween.
  • In addition, the first and second internal electrodes 120 and 130 may be disposed to be spaced apart from the first and second end surfaces S3 and S4 of the ceramic body 110 in the length direction thereof.
  • The first and second internal electrodes 120 and 130 may include a body portion contributing to the formation of capacitance through overlapped portions of internal electrodes adjacent to each other and a lead-out portion as a portion partially extended from the body portion and exposed to the outer surface of the ceramic body 110.
  • The lead-out portion may have, for example, a length shorter than that of the body portion, but is not particularly limited thereto.
  • Further, a thickness of the first and second internal electrodes 120 and 130 may be determined according to the use thereof. For example, the thickness may be determined to be in a range of 0.2 to 1.0 μm in consideration of a size of the ceramic body 110, but the present disclosure is not limited thereto.
  • In addition, a material forming the first and second internal electrodes 120 and 130 is not particularly limited. For example, the first and second internal electrodes 120 and 130 may be formed using a conductive paste containing one or more of a noble metal such as palladium (Pd), a palladium-silver (Pd—Ag) alloy, or the like, nickel (Ni), and copper (Cu), or the like.
  • Further, as a printing method of the conductive paste, a screen printing method, a gravure printing method, or the like, may be used, but the present disclosure is not limited thereto.
  • In the exemplary embodiment of the present disclosure, the first internal electrode 120 may have first and second lead-out portions 121 and 122 spaced apart from each other in the length direction of the ceramic body and exposed to the first main surface S1 of the ceramic body 110 and may be spaced apart from the first and second end surfaces S3 and S4 by a predetermined distance.
  • In addition, the second internal electrode 130 may have a third lead-out portion 131 exposed to the first main surface S1 of the ceramic body 110 and formed between the first and second lead-out portions 121 and 122 so as to be spaced apart from the respective first and second lead-out portions 121 and 122 by a predetermined distance, and may be spaced apart from the first and second end surfaces S3 and S4 by a predetermined distance.
  • In a general multilayer ceramic electronic component, an external electrode may be disposed on both end surfaces of a ceramic body opposing each other in a length direction of the ceramic body.
  • However, in this case, at the time of applying an alternating current (AC) voltage to the external electrode, since a current path is relatively long, a current loop may be relatively large, and an intensity of an induced magnetic field may be increased, such that inductance may be increased.
  • In order to solve this problem, according to an exemplary embodiment in the present disclosure, the first and second external electrodes 141 and 142 may be disposed on the first main surface S1 of the ceramic body 110, and the third external electrode 143 may be disposed between the first and second external electrodes 141 and 142 on the first main surface S1 of the ceramic body 110.
  • In this case, since an interval between the first and second external electrodes 141 and 142 and the third external electrode 143 is relatively short, the current loop may be decreased, such that inductance may be decreased.
  • The first and second external electrodes 141 and 142 may be formed on the first main surface S1 of the ceramic body 110 so as to be spaced apart from each other in the length direction of the ceramic body and contact the first and second lead-out portions 121 and 122, respectively, to thereby be electrically connected thereto.
  • The third external electrode 143 may be formed on the first main surface S1 of the ceramic body 110 so as to be spaced apart from the respective first and second external electrodes 141 and 142 by a predetermined distance and contact the third lead-out portion 131 to thereby be electrically connected thereto.
  • In addition, the first to third external electrodes 141 to 143 may be electrically connected to the corresponding lead-out portions of the first and second internal electrodes 120 and 130, respectively, in order to form capacitance, and when necessary, the first to third external electrodes 141 to 143 may be extended to portions of the first and second side surfaces S5 and S6 of the ceramic body 110 to form side bands.
  • In the exemplary embodiment of the present disclosure, the first to third external electrodes 141 to 143 may have a three layer structure and may include first to third conductive layers 141 a to 143 a contacting the corresponding lead-out portions of the internal electrode, respectively, to thereby be electrically connected thereto, first to third nickel (Ni) plating layers 141 b to 143 b formed to cover the first to third conductive layers 141 a to 143 a, respectively, and first to third tin (Sn) plating layers 141 c to 143 c formed to cover the first to third nickel plating layers 141 b to 143 b, respectively.
  • The first to third conductive layers 141 a to 143 a may be formed using the same conductive material as that of the first and second internal electrodes 120 and 130, but are not limited thereto. For example, the first to third conductive layers 141 a to 143 a may be formed using powder of a metal such as copper (Cu), silver (Ag), nickel (Ni), or the like, and formed by applying a conductive paste prepared by adding glass frit to this metal powder and then sintering the applied conductive paste.
  • FIG. 5 is an enlarged side cross-sectional view illustrating part A of FIG. 4.
  • In the exemplary embodiment of the present disclosure, the first lead-out portion 121 and the first external electrode 141 connected to the first lead-out portion 121 are described by way of example, but the present disclosure is not limited thereto. Numerical limitations to be described below may be similarly applied to the second and third lead-out portions and the second and third external electrodes contacting the respective lead-out portions to thereby be electrically connected thereto, and a detailed description thereof will be omitted in order to avoid an overlapping description.
  • In addition, the numerical limitations may be similarly applied to fourth to sixth lead-out portions to be described below and fourth to sixth external electrodes contacting the respective lead-out portions to thereby be electrically connected thereto.
  • Referring to FIG. 5, an outermost portion of the first lead-out portion 121 exposed to the first main surface S1 of the ceramic body 110 may be defined as P, a total thickness of the first conductive layer 141 a, the first nickel plating layer 141 b, and the first tin plating layer 141 c in a normal line direction of the first conductive layer 141 a from P may be defined as a, a thickness of the first conductive layer 141 a in the normal line direction of the first conductive layer 141 a from P may be defined as b, and a thickness of the first nickel plating layer 141 b in the normal line direction of the first conductive layer 141 a from P may be defined as c.
  • Here, the normal line L indicates a straight line which passes through P and is perpendicular to a tangent plane T at a point on a curved line forming a boundary surface between the first conductive layer and the first nickel plating layer.
  • In addition, a sum of pore heights bp1 and bp2 of pores existing in the first conductive layer 141 a in the normal line direction of the first conductive layer 141 a from P may be defined as bp.
  • The case in which the number of corresponding pores is two is shown in FIG. 5 and described in the exemplary embodiment of the present disclosure, but the present disclosure is not limited thereto. The number of pores existing in the first conductive layer 141 a in the normal line direction of the first conductive layer 141 a from P may be one or three or more in some cases.
  • In the exemplary embodiment of the present disclosure, (b−bp)/a, which is a ratio of a real thickness (b−bp, a thickness of only a metal portion) except for thickness bp of the pores from the thickness b of the conductive layer directly connected to the internal electrode to the thickness a of the entire external electrode, may satisfy 0.264≦(b−bp)/a≦0.638.
  • Since the lower the ratio (b−bp)/a is, the smaller the real thickness of the external electrode is, the possibility that a plating solution will infiltrate into the internal electrode at the time of plating, for example, forming the nickel plating layer, may be increased, thereby increasing the possibility of deterioration in reliability.
  • In addition, b/c, a ratio of the thickness b of the conductive layer directly connected to the internal electrode to the thickness c of the nickel plating layer may satisfy 0.930≦b/c≦5.391.
  • Since the lower the ratio b/c is, the thinner the conductive layer is and the thicker the nickel plating layer is, the possibility that the plating solution will infiltrate into the internal electrode at the time of plating, for example, forming the nickel plating layer, may be increased, thereby increasing the possibility of deterioration in reliability.
  • Modified Example
  • FIG. 6 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure, FIG. 7 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 6 in a state in which external electrodes thereof are omitted, and FIG. 8 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 6.
  • Here, since a structure of a ceramic body 110 is the same as that in the above-mentioned exemplary embodiment, a detailed description thereof will be omitted in order to avoid an overlapped description, and first and second internal electrodes 120 and 130 having different structures from those in the above-mentioned exemplary embodiment and an insulating layer 150 will be described in detail.
  • Referring to FIGS. 6 through 8, in a multilayer ceramic capacitor 100′ according to another exemplary embodiment in the present disclosure, the insulating layer 150 may be disposed on the second surface S2 opposing the mounting surface of the ceramic body 110.
  • The first internal electrode 120 may have fourth and fifth lead-out portions 123 and 124 exposed to the second main surface S2 of the ceramic body 110 to contact the insulating layer 150 formed on the second main surface S2 of the ceramic body 110.
  • The second internal electrode 130 may have a sixth lead-out portion 132 disposed between the fourth and fifth lead-out portions 123 and 124 and exposed to the second main surface S2 of the ceramic body 110 to contact the insulating layer 150.
  • FIG. 9 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure, FIG. 10 is a perspective view illustrating a ceramic body of the multilayer ceramic capacitor of FIG. 9, FIG. 11 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 9 in a state in which external electrodes thereof are omitted, and FIG. 12 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 9.
  • Here, since a structure of a ceramic body 110 is the same as that in the above-mentioned exemplary embodiment, a detailed description thereof will be omitted in order to avoid an overlapped description, and fourth to sixth external electrodes 144 to 146 and first and second internal electrodes 120 and 130 having different structures from those in the above-mentioned exemplary embodiment will be described in detail.
  • Referring to FIGS. 9 through 12, in a multilayer ceramic capacitor 100″ according to the present exemplary embodiment, the fourth to sixth external electrodes 144 to 146 may be disposed on the second main surface S2 of the ceramic body 110 to oppose the first to third external electrodes 141 to 143, respectively.
  • In this case, when necessary, the fourth to sixth external electrodes 144 to 146 may be extended to portions of the first and second side surfaces S5 and S6 in the width direction of the ceramic body 110.
  • The fourth to sixth external electrodes 144 to 146 may have a three layer structure and may include fourth to sixth conductive layers 144 a to 146 a contacting corresponding lead-out portions of the internal electrodes to thereby be connected thereto, respectively, fourth to sixth nickel (Ni) plating layers 144 b to 146 b formed to cover the fourth to sixth conductive layers 144 a to 146 a, respectively, and fourth to sixth tin (Sn) plating layers 144 c to 146 c formed to cover the fourth to sixth nickel plating layers 144 b to 146 b, respectively.
  • The first internal electrode 120 may have fourth and fifth lead-out portions 123 and 124 exposed to the second main surface S2 of the ceramic body 110 to be connected to the fourth and fifth external electrodes 144 and 145 formed on the second main surface S2 of the ceramic body 110, respectively.
  • The second internal electrode 130 may have a sixth lead-out portion 132 disposed between the fourth and fifth lead-out portions 123 and 124 and exposed to the second main surface S2 of the ceramic body 110 to be connected to the sixth external electrode 146.
  • As described above, in the case of forming internal and external structures of the multilayer ceramic capacitor 100″ to be vertically symmetric structure, directionality of the capacitor may be removed.
  • In detail, since the multilayer ceramic capacitor 100″ has a vertically symmetric structure, a defect occurring when amounting surface is inversely disposed at the time of mounting the capacitor on a substrate may be prevented.
  • Therefore, since one of the first and second main surfaces S1 and S2 of the multilayer ceramic capacitor 100″ may be provided as amounting surface, at the time of mounting the multilayer ceramic capacitor 100″ on a substrate, there is no need to consider a direction of the mounting surface.
  • FIG. 13 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure, FIG. 14 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 13 in a state in which external electrodes thereof are omitted, and FIG. 15 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 13.
  • Referring to FIGS. 13 through 15, in a multilayer ceramic capacitor 1000 according to another exemplary embodiment in the present disclosure, a plurality of first and second internal electrodes 1200 and 1300 may be alternately formed in a ceramic body 1100 with the respective dielectric layer 1110 interposed therebetween. Here, reference numerals 1120 and 1130 indicate cover layers.
  • The first internal electrode 1200 may have first and second lead-out portions 1210 and 1220 spaced apart from each other in a length direction of the ceramic body and exposed to a first main surface S1 of the ceramic body 1100 and may be formed to be spaced apart from first and second end surfaces S3 and S4.
  • In addition, the second internal electrode 1300 may have third and fourth lead-out portions 1310 and 1320 exposed to the first main surface S1 of the ceramic body 1100 and formed alternately with the first and second lead-out portions 1210 and 1220 in the length direction thereof so as not to be overlapped with each other, and may be spaced apart from the first and second end surfaces S3 and S4.
  • First and second external electrodes 1410 and 1420 may be formed on the first main surface S1 of the ceramic body 1110 so as to be spaced apart from each other in the length direction of the ceramic body and contact the first and second lead-out portions 1210 and 1220, respectively, to thereby be electrically connected thereto.
  • The third and fourth external electrodes 1430 and 1440 may be formed on the first main surface S1 of the ceramic body 1100 so as to be spaced apart from each other in the length direction of the ceramic body and contact the third and fourth lead-out portions 1310 and 1320, respectively, to thereby be electrically connected thereto.
  • Further, the first internal electrode 1200 may have fifth and sixth lead-out portions 1230 and 1240 spaced apart from each other in the length direction of the ceramic body and exposed to a second main surface S2 of the ceramic body 1100.
  • In addition, the second internal electrode 1300 may have seventh and eighth lead-out portions 1330 and 1340 exposed to the second main surface S2 of the ceramic body 1100 and formed alternately with the fifth and sixth lead-out portions 1230 and 1240 in the length direction so as not to be overlapped with each other.
  • Further, fifth to eighth external electrodes 1450 to 1480 may be formed on the second main surface S2 of the ceramic body 1100 so as to be spaced apart from each other.
  • In this case, the fifth and sixth external electrodes 1450 and 1460 may contact the fifth and sixth lead-out portions 1230 and 1240, respectively, to thereby be electrically connected thereto, and the seventh and eighth external electrodes 1470 and 1480 may contact the seventh and eighth lead-out portions 1330 and 1340, respectively, to thereby be electrically connected thereto.
  • In the multilayer ceramic capacitor 1000 according to the exemplary embodiment in the present disclosure configured as described above, an area formed by a current loop may be further decreased, and a current path may be further dispersed, such that ESL of the capacitor may be further decreased by about 50% as compared to the 3-terminal capacitor according to the exemplary embodiment in the present disclosure.
  • Meanwhile, since a structure of the ceramic body 1100 and a three-layer structure and numerical limitations of the first to eighth external electrodes 1410 to 1480 are similar to those in the foregoing exemplary embodiment of the present disclosure, a detailed description thereof will be omitted.
  • Experimental Example
  • Multilayer ceramic capacitors according to Inventive Examples and Comparative Examples were manufactured as follows.
  • A slurry containing powder such as barium titanate (BaTiO3) powder, or the like, was applied to a carrier film to then be dried thereon, thereby preparing a plurality of ceramic green sheets having a thickness of 1.8 μm.
  • Then, a conductive paste for an internal electrode was applied to the ceramic green sheet using screen printing, thereby forming first and second internal electrodes 120 and 130.
  • The first internal electrode 120 may include first and second lead-out portions 121 and 122 exposed to a first main surface and fourth and fifth lead-out portions 123 and 124 exposed to a second main surface on the ceramic green sheet.
  • The second internal electrode 130 may include a third lead-out portion 131 exposed to the first main surface and a sixth lead-out portion 132 exposed to the second main surface on the ceramic green sheet.
  • The third lead-out portion 131 was formed to be spaced apart from the first and second lead-out portions 121 and 122, and the sixth lead-out portion 132 was formed to be spaced apart from the fourth and fifth lead-out portions 123 and 124.
  • Then, the plurality of ceramic green sheets were stacked so that the first and second internal electrodes 120 and 130 were alternately disposed.
  • Thereafter, on both sides of the stacked first and second internal electrodes, at least one or more ceramic green sheets on which the first and second internal electrodes 120 and 130 were not formed were stacked, respectively, to form cover layers 112 and 113, thereby manufacturing a multilayer body.
  • Then, the isostatic pressing was performed on the multilayer body at about 85° C. and a pressure of about 1000 kgf/cm2.
  • Next, a ceramic multilayer body subjected to the isostatic pressing was cut into regions to have the form of individual chips.
  • Then, the cut chip was subjected to a de-binding process to be maintained at about 230° C. for about 60 hours under an air atmosphere.
  • Next, a ceramic body was prepared by sintering the chip at about 1200° C. under a reduction atmosphere having an oxygen partial pressure of 10−11 atm to 10−10 atm lower than Ni/NiO equilibrium oxygen partial pressure so that the internal electrode was not oxidized.
  • A chip size of the multilayer chip capacitor after sintering was about 2.0 mm×1.25 mm (Length×Width (L×W), so-called 2012 size). In this case, a manufacturing tolerance was in a range of ±0.1 mm (Length×Width (L×W)).
  • Then, a process of forming first to sixth external electrodes 141 to 146 on first and second main surfaces S1 and S2 of a ceramic body 110 so as to be connected to the corresponding lead-out portions of the first and second internal electrodes 120 and 130, respectively, was performed.
  • The multilayer ceramic capacitor was completed through the above-mentioned processes and whether or not a defect due to a high temperature/moisture resistance load occurred and whether or not a size defect occurred were tested. The test results were shown in Table 1.
  • Here, a high temperature load test was performed at 85° C. and 1.25× rated voltage, and a moisture resistance load test was performed at 85° C., a humidity of 85%, and 1× rated voltage.
  • In this case, the high temperature/moisture resistance load test was performed on 800 test samples under the same test conditions, and the size defect test was performed on 100 test samples under the same test conditions. Here, the size defect indicates a defect in which, since a thickness of the external electrode is excessively thick, the entire chip size is outside of the range of the specification.
  • TABLE 1 High Temperature/Moisture Resistance Size No a b bp c (b − bp)/a b/c Load Defect Defect  1* 11.1 um  2.7 um 0.55 um 4.40 um 0.194 0.614 12/800  0/100  2* 13.9 um  3.2 um 0.33 um 5.20 um 0.206 0.615 9/800 0/100 3 16.0 um  5.3 um 1.08 um 5.70 um 0.264 0.930 0/800 0/100 4 14.6 um  5.8 um 0.62 um 4.40 um 0.355 1.318 0/800 0/100 5 14.8 um  7.9 um 1.48 um 3.80 um 0.434 2.079 0/800 0/100 6 19.6 um  8.2 um 1.04 um 5.50 um 0.365 1.491 0/800 0/100 7 22.7 um 11.2 um 1.87 um 5.50 um 0.411 2.036 0/800 0/100 8 20.6 um 11.8 um 1.33 um 4.80 um 0.508 2.458 0/800 0/100 9 23.0 um 13.5 um 2.02 um 4.40 um 0.499 3.068 0/800 0/100 10  22.4 um 14.0 um 1.29 um 4.60 um 0.567 3.043 0/800 0/100 11  28.9 um 18.0 um 3.10 um 5.30 um 0.516 3.396 0/800 0/100 12  25.6 um 17.5 um 2.42 um 4.00 um 0.589 4.375 0/800 0/100 13  34.4 um 24.0 um 4.24 um 5.60 um 0.574 4.286 0/800 0/100 14  34.1 um 24.8 um 3.05 um 4.60 um 0.638 5.391 0/800 0/100 15* 43.1 um 34.2 um 6.14 um 5.20 um 0.651 6.577 0/800 7/100 16* 43.9 um 34.8 um 3.18 um 5.60 um 0.720 6.214 0/800 9/100
  • Referring to FIG. 5, an outermost portion of the first lead-out portion 121 exposed to the first main surface S1 of the ceramic body 110 may be defined as P, a total thickness of the first conductive layer 141 a, the first nickel plating layer 141 b, and the first tin plating layer 141 c in a normal line direction of the first conductive layer 141 a from P may be defined as a, a thickness of the first conductive layer 141 a in the normal line direction of the first conductive layer 141 a from P may be defined as b, and a thickness of the first nickel plating layer 141 b in the normal line direction of the first conductive layer 141 a from P may be defined as c.
  • Here, the normal line L refers to a straight line which passes through P and is perpendicular to a tangent plane T at a point on a curved line forming a boundary surface between the conductive layer and the nickel plating layer.
  • In addition, a sum of pore heights bp1 and bp2 of pores existing in the first conductive layer in the normal line direction of the first conductive layer from P may be defined as bp.
  • In the exemplary embodiment the present disclosure, (b−bp)/a, which is a ratio of a real thickness (b−bp, a thickness of only a metal portion) except for thickness bp of the pores from the thickness b of the conductive layer directly connected to the internal electrode to the thickness a of the entire external electrode, may satisfy 0.264≦(b−bp)/a≦0.638.
  • In addition, b/c, a ratio of the thickness b of the conductive layer directly connected to the internal electrode to the thickness c of the nickel plating layer may satisfy 0.930≦b/c≦5.391.
  • Referring to Table 1, in the cases of samples 1 and in which (b−bp)/a was less than 0.264, a high temperature/moisture resistance load defect occurred, and in the case of samples 15 and 16 in which (b−bp)/a was more than 0.638, the thickness of the external electrodes was excessively thick, such that a size defect in which the chip size was outside of the range of the specification occurred.
  • Therefore, (b−bp)/a may be 0.264 or more, but 0.638 or less.
  • Further, in the cases of the samples 1 and 2 in which b/c was less than 0.930, since the thickness b of the conductive layer was excessively thin, at the time of performing nickel plating, infiltration of the plating solution was not blocked, such that the high temperature/moisture resistance load defect occurred, and in the cases of the samples 15 and 16 in which b/c was more than 5.391, the thickness of the external electrode was excessively thick, such that the size defect in which the chip size was outside of the range of the specification occurred.
  • Meanwhile, the results shown in Table 1 may be similarly applied to the first to third external electrodes of the multilayer ceramic capacitors according to the exemplary embodiments shown in FIGS. 1 and 6.
  • Board Having Multilayer Ceramic Capacitor
  • FIG. 16 is a perspective view illustrating a form in which the multilayer ceramic capacitor of FIG. 9 is mounted on a substrate, and FIG. 17 is a cross-sectional view illustrating the form in which the multilayer ceramic capacitor of FIG. 9 is mounted on the substrate.
  • Referring to FIGS. 16 and 17, a board 200 having a multilayer ceramic capacitor 100″ according to the present exemplary embodiment may include a substrate 210 on which the multilayer ceramic capacitor 100″ is mounted, and first to third electrode pads 221 to 223 formed on the substrate 210 so as to be spaced apart from each other.
  • In this case, the multilayer ceramic capacitor 100″ may be adhered to the substrate 210 by a solder 230 to thereby be electrically connected to each other in a state in which first to third external electrodes 141 to 143 are positioned on the first to third electrode pads 221 to 223, respectively, so as to contact each other.
  • In FIG. 17, reference numeral 224 indicates a ground terminal, and reference numeral 225 indicates a power terminal.
  • Meanwhile, although the case in which the multilayer ceramic capacitor of FIG. 9 is mounted is described in the present exemplary embodiment, the present disclosure is not limited thereto. For example, the multilayer ceramic capacitors illustrated in FIGS. 1 and 6 may also be mounted on a substrate in a manner similar thereto to thereby configure boards including a multilayer ceramic capacitor.
  • Further, the electrode pads included in the board according to the present disclosure may be changed according to the structure of the multilayer ceramic capacitor to be mounted. For example, in the case of a board on which a multilayer ceramic capacitor having a 4-terminal structure is mounted, the board may include four electrode pads formed thereon. Therefore, a structure of the board having a multilayer ceramic capacitor according to the present disclosure is not limited to those of the drawings.
  • As set forth above, according to exemplary embodiments in the present disclosure, since the lead-out portion of the internal electrode is positioned on the mounting surface, the area of the current loop may be decreased, such that ESL may be decreased, and infiltration of a plating solution through an external electrode may be prevented, thereby preventing reliability from being deteriorated.
  • While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims (20)

What is claimed is:
1. A multilayer ceramic capacitor comprising:
a ceramic body including a plurality of dielectric layers stacked therein;
a plurality of first and second internal electrodes alternately disposed in the ceramic body, each first and second internal electrodes interposed between the respective dielectric layer, and the first and second internal electrodes including first and second body portions overlapped with each other and first and second lead-out portions extended from the first and second body portions to be exposed to one surface of the ceramic body, respectively; and
first and second external electrodes formed on the one surface of the ceramic body to be connected to the first and second lead-out portions, respectively,
wherein in the first and second external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the one surface of the ceramic body, and
when an outermost portion of one of the first and second lead-out portions exposed to the one surface of the ceramic body is P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is bp, (b−bp)/a satisfies 0.264≦(b−bp)/a≦0.638.
2. The multilayer ceramic capacitor of claim 1, wherein when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is c, b/c satisfies 0.930≦b/c≦5.391.
3. A multilayer ceramic capacitor comprising:
a ceramic body including a plurality of dielectric layers stacked in a width direction of the ceramic body;
an active layer including a plurality of first and second internal electrodes alternately disposed in the ceramic body to have a respective dielectric layer interposed between the first and second internal electrodes;
first and second lead-out portions extended from the first internal electrode to be exposed to a mounting surface of the ceramic body, and spaced apart from each other in a length direction of the ceramic body;
a third lead-out portion extended from the second internal electrode to be exposed to the mounting surface of the ceramic body, and disposed between the first and second lead-out portions;
first and second external electrodes disposed on the mounting surface of the ceramic body to be spaced apart from each other in the length direction, and connected to the first and second lead-out portions, respectively; and
a third external electrode formed on the mounting surface of the ceramic body to be located between the first and second external electrodes, and connected to the third lead-out portion,
wherein in the first to third external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the mounting surface of the ceramic body, and
when an outermost portion of one of the first to third lead-out portions exposed to the mounting surface of the ceramic body is defined as P, a total thickness of the conductive layer, the nickel plating layer, and the tinplating layer in a normal line direction of the conductive layer from P is defined as a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is defined as b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is defined as bp, (b−bp)/a satisfies 0.264≦(b−bp)/a≦0.638.
4. The multilayer ceramic capacitor of claim 3, wherein when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is c, b/c satisfies 0.930≦b/c≦5.391.
5. The multilayer ceramic capacitor of claim 3, wherein the first and second internal electrodes are disposed to be spaced apart from both end surfaces of the ceramic body in the length direction.
6. The multilayer ceramic capacitor of claim 3, wherein the first to third external electrodes are extended to portions of both side surfaces of the ceramic body in the width direction, respectively.
7. The multilayer ceramic capacitor of claim 3, further comprising:
fourth and fifth lead-out portions extended from the first internal electrode to be exposed to a surface opposing the mounting surface of the ceramic body, and disposed to be spaced apart from each other in the length direction of the ceramic body;
a sixth lead-out portion extended from the second internal electrode to be exposed to the surface opposing the mounting surface of the ceramic body, and disposed between the fourth and fifth lead-out portions; and
an insulating layer disposed on the surface opposing the mounting surface of the ceramic body.
8. The multilayer ceramic capacitor of claim 3, wherein the first internal electrode has fourth and fifth lead-out portions spaced apart from each other in the length direction and exposed to the surface opposing the mounting surface of the ceramic body, and
the second internal electrode has a sixth lead-out portion exposed to the surface opposing the mounting surface of the ceramic body, and formed between the fourth and fifth lead-out portions to be spaced apart from the fourth and fifth lead-out portions,
the multilayer ceramic capacitor further comprising:
fourth and fifth external electrodes formed on the surface opposing the mounting surface of the ceramic body to be spaced apart from each other in the length direction and connected to the fourth and fifth lead-out portions, respectively; and
a sixth external electrode formed on the surface opposing the mounting surface of the ceramic body to be spaced apart from the respective fourth and fifth external electrodes and connected to the sixth lead-out portion.
9. The multilayer ceramic capacitor of claim 8, wherein in the fourth to sixth external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the surface opposing the mounting surface of the ceramic body, and
when an outermost portion of one of the fourth to sixth lead-out portions exposed to the surface opposing the mounting surface of the ceramic body is defined as P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is defined as a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is defined as b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is defined as bp, (b−bp)/a satisfies 0.264≦(b−bp)/a≦0.638.
10. The multilayer ceramic capacitor of claim 9, wherein in the fourth to sixth external electrodes, when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is defined as c, b/c satisfies 0.930≦b/c≦5.391.
11. The multilayer ceramic capacitor of claim 8, wherein the fourth to sixth external electrodes are extended to portions of both side surfaces of the ceramic body in the width direction.
12. The multilayer ceramic capacitor of claim 3, further comprising cover layers formed on both sides of the active layer in the width direction.
13. A multilayer ceramic capacitor comprising:
a ceramic body including a plurality of dielectric layers stacked in a width direction and having first and second main surfaces opposing each other in a thickness direction of the ceramic body, first and second side surfaces opposing each other in the width direction of the ceramic body, and first and second end surfaces opposing each other in a length direction of the ceramic body;
an active layer including a plurality of first and second internal electrodes alternately disposed in the ceramic body, each first and second internal electrodes interposed between the respective dielectric layer, the first internal electrode including first and second lead-out portions spaced apart from each other in the length direction and exposed to the first main surface of the ceramic body, the first internal electrode being spaced apart from the first and second end surfaces, and the second internal electrode including third and fourth lead-out portions exposed to the first main surface of the ceramic body and disposed alternately with the first and second lead-out portions, the second internal electrode being spaced apart from the first and second end surfaces;
cover layers disposed on both sides of the active layer;
first and second external electrodes formed on the first main surface of the ceramic body to be spaced apart from each other in the length direction and connected to the first and second lead-out portions, respectively; and
third and fourth external electrodes formed on the first main surface of the ceramic body to be spaced apart from each other in the length direction and connected to the third and fourth lead-out portions, respectively,
wherein in the first to fourth external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the first main surface of the ceramic body, and
when an outermost portion of one of the first to fourth lead-out portions exposed to the first main surface of the ceramic body is P, a total thickness of the conductive layer, the nickel plating layer, and the tinplating layer in a normal line direction of the conductive layer from P is a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is bp, (b−bp)/a satisfies 0.264≦(b−bp)/a≦0.638.
14. The multilayer ceramic capacitor of claim 13, wherein when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is defined as c, b/c satisfies 0.930≦b/c≦5.391.
15. The multilayer ceramic capacitor of claim 13, wherein the first internal electrode has fifth and sixth lead-out portions spaced apart from each other in the length direction and exposed to the second main surface of the ceramic body, and
the second internal electrode has seventh and eighth lead-out portions exposed to the second main surface of the ceramic body and formed alternately with the fifth and sixth lead-out portions, and
the multilayer ceramic capacitor further comprising:
fifth and sixth external electrodes formed on the second main surface of the ceramic body to be spaced apart from each other in the length direction and connected to the fifth and sixth lead-out portions, respectively; and
seventh and eighth external electrodes formed on the second main surface of the ceramic body to be spaced apart from each other in the length direction and connected to the seventh and eighth lead-out portions, respectively.
16. The multilayer ceramic capacitor of claim 15, wherein in the fifth to eighth external electrodes, a conductive layer, a nickel (Ni) plating layer, and a tin (Sn) plating layer are sequentially stacked on the second main surface of the ceramic body, and
when an outermost portion of one of the fifth to eighth lead-out portions exposed to the second main surface of the ceramic body is defined as P, a total thickness of the conductive layer, the nickel plating layer, and the tin plating layer in a normal line direction of the conductive layer from P is defined as a, a thickness of the conductive layer in the normal line direction of the conductive layer from P is defined as b, and a sum of pore heights of pores existing in the conductive layer in the normal line direction of the conductive layer from P is defined as bp, (b−bp)/a satisfies 0.264≦(b−bp)/a≦0.638.
17. The multilayer ceramic capacitor of claim 16, wherein when a thickness of the nickel plating layer in the normal line direction of the conductive layer from P is defined as c, b/c satisfies 0.930≦b/c≦5.391.
18. A board including a multilayer ceramic capacitor comprising:
a substrate including a plurality of electrode pads formed on the substrate; and
the multilayer ceramic capacitor of claim 1, mounted on the electrode pads of the substrate.
19. A board including a multilayer ceramic capacitor comprising:
a substrate including a plurality of electrode pads formed on the substrate; and
the multilayer ceramic capacitor of claim 3, mounted on the electrode pads of the substrate.
20. A board including a multilayer ceramic capacitor comprising:
a substrate including a plurality of electrode pads formed on the substrate; and
the multilayer ceramic capacitor of claim 13, mounted on the electrode pads of the substrate.
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