US9396879B2 - Multilayer ceramic capacitor and board having the same - Google Patents

Multilayer ceramic capacitor and board having the same Download PDF

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US9396879B2
US9396879B2 US14/527,662 US201414527662A US9396879B2 US 9396879 B2 US9396879 B2 US 9396879B2 US 201414527662 A US201414527662 A US 201414527662A US 9396879 B2 US9396879 B2 US 9396879B2
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ceramic
portions
external electrodes
disposed
capacitor
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US20150114705A1 (en
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Young Ghyu Ahn
Hyun Tae Kim
Hwi Geun IM
Jin Kim
Kyo Kwang LEE
Byoung HWA Lee
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Priority to KR10-2014-0133068 priority
Priority to KR1020140133068A priority patent/KR101514610B1/en
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    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H01G2/065—Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/248—Terminals the terminals embracing or surrounding the capacitive element, e.g. caps

Abstract

There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 μm or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 μm or more.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit of Korean Patent Applications Nos. 10-2013-0129120 filed on Oct. 29, 2013, and 10-2014-0133068 filed on Oct. 2, 2014 with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference.
BACKGROUND
The present disclosure relates to a multilayer ceramic capacitor and a board having the same.
In accordance with the recent trend for the miniaturization and increases in the capacitance of electronic products, demands have increasingly been made for electronic components used in electronic products to be relatively small while having high capacitance.
Among electronic components, in the case of multilayer ceramic capacitors, when equivalent series inductance (hereinafter, referred to as “ESL”) increases, performance of electronic products in which the capacitors are provided may be deteriorated. In addition, in accordance with the miniaturization of the electronic products and increases in the capacitance of the electronic components, increases in ESL of the multilayer ceramic capacitors may have a relatively significant effect on deteriorations in performance of the electronic products.
Particularly, in accordance with increases in the performance of integrated circuits (IC), decoupling capacitors have been increasingly used therein. Therefore, demand for multilayer ceramic capacitors (MLCCs) having a 3-terminal vertical multilayer structure, so-called “low inductance chip capacitors (LICC)”, capable of decreasing inductance in capacitors by decreasing a distance between external terminals to decrease a current flow path, has increased.
In the case of such multilayer ceramic capacitors, reliability and mounting defect rates may be significantly affected by the shapes and sizes of external electrodes.
SUMMARY
An exemplary embodiment in the present disclosure may provide a 3-terminal vertical multilayer capacitor having improved reliability and adhesion strength while low ESL characteristics are maintained, and a board having the same.
According to an exemplary embodiment in the present disclosure, a multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from each other and connected to lead portions of internal electrodes, wherein an interval between adjacent lead portions is 500.7 μm or less, widths of one-side margin portions of the external electrodes in a length direction of the ceramic body that are not in contact with the corresponding lead portions are 20.2 μm or more.
BRIEF DESCRIPTION OF DRAWINGS
The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a perspective view schematically illustrating a multilayer ceramic capacitor according to an exemplary embodiment in the present disclosure in a state in which the multilayer ceramic capacitor is inverted;
FIG. 2 is a perspective view illustrating a ceramic body of the multilayer ceramic capacitor of FIG. 1 in a state in which the ceramic body is inverted;
FIG. 3 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 1 in a state in which external electrodes thereof are omitted;
FIG. 4 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 1;
FIG. 5 is a perspective view illustrating another example of the multilayer ceramic capacitor of FIG. 1 including external electrodes having different shapes;
FIG. 6 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure;
FIG. 7 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 6 in a state in which external electrodes thereof are omitted;
FIG. 8 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure;
FIG. 9 is a perspective view illustrating a ceramic body of the multilayer ceramic capacitor of FIG. 8;
FIG. 10 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 8 in a state in which external electrodes thereof are omitted;
FIG. 11 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 8;
FIG. 12 is a perspective view illustrating another example of the multilayer ceramic capacitor of FIG. 8 including external electrodes having different shapes;
FIG. 13 is a perspective view illustrating a board on which the multilayer ceramic capacitor of FIG. 8 is mounted; and
FIG. 14 is a cross-sectional view illustrating the board on which the multilayer ceramic capacitor of FIG. 8 is mounted.
 DETAILED DESCRIPTION
Exemplary embodiments in the present disclosure will now be described in detail with reference to the accompanying drawings.
The disclosure may, however, be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the drawings, the shapes and dimensions of elements maybe exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements.
Directions of a hexahedral ceramic body will be defined in order to clearly describe exemplary embodiments in the present disclosure. L, W and T directions, provided in the accompanying drawings, refer to a length direction, a width direction, and a thickness direction, respectively. Here, the width direction may be used as having the same meaning as a direction in which dielectric layers are stacked.
Multilayer Ceramic Capacitor
FIG. 1 is a perspective view schematically illustrating a multilayer ceramic capacitor according to an exemplary embodiment in the present disclosure; FIG. 2 is a perspective view illustrating a ceramic body of the multilayer ceramic capacitor of FIG. 1 in a state in which the ceramic body is inverted; FIG. 3 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 1 in a state in which external electrodes thereof are omitted; and FIG. 4 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 1.
Referring to FIGS. 1 through 4, a multilayer ceramic capacitor 100 according to the present exemplary embodiment may include a ceramic body 110 in which a plurality of dielectric layers 111 are stacked in the width direction, an active portion including a plurality of first and second internal electrodes 120 and 130, and first to third external electrodes 141 to 143.
The multilayer ceramic capacitor 100 according to the present exemplary embodiment may be a 3-terminal capacitor having a total of three external terminals.
The ceramic body 110 may have first and second surfaces S1 and S2 opposing each other in the thickness direction, fifth and sixth surfaces S5 and S6 connecting the first and second main surfaces S1 and S2 to each other and opposing each other in the width direction, and third and fourth surfaces S3 and S4 opposing each other in the length direction.
Hereinafter, in the present exemplary embodiment, a mounting surface of the multilayer ceramic capacitor 100 may be the first surface S1 of the ceramic body 110.
The ceramic body 110 may be formed by stacking the plurality of dielectric layers 111 in the width direction and then sintering the stacked dielectric layers 111, and a shape thereof is not particularly limited, but may be hexahedral as illustrated in the accompanying drawings.
However, shape and dimensions of the ceramic body 110 and the number of stacked dielectric layers 111 are not limited to those of the present exemplary embodiment illustrated in the accompanying drawing.
In addition, the plurality of dielectric layers 111 configuring the ceramic body 110 may be in a sintered state, and boundaries between the dielectric layers 111 adjacent to each other may be integrated such that they may not be readily discernible without the use of a scanning electron microscope (SEM).
The ceramic body 110 may include the active portion including the plurality of internal electrodes and contributing to capacitance formation of the capacitor and cover layers 112 and 113 disposed on both side surfaces of the active portion in the width direction as margin portions.
The active portion may be formed by alternately stacking the plurality of first and second internal electrodes 120 and 130 in the width direction, having the dielectric layers 111 interposed therebetween.
In this case, a thickness of the dielectric layers 111 may be optionally changed according to an intended degree of capacitance of the multilayer ceramic capacitor 100, but a thickness of a single dielectric layer may be preferably 0.01 to 1.00 μm after a sintering process. However, the present disclosure is not limited thereto.
Further, the dielectric layers 111 may contain a ceramic powder having high permittivity, for example, a barium titanate (BaTiO3)-based powder or a strontium titanate (SrTiO3)-based powder, or the like, but the material of the dielectric layers is not limited thereto as long as sufficient capacitance may be obtained.
If necessary, a ceramic additive, an organic solvent, a plasticizer, a binder, a dispersant, and the like, may be further added to the dielectric layers 111, in addition to the ceramic powder.
In this case, an average particle size of the ceramic powder used to form the dielectric layers 111 is not particularly limited and may be controlled in order to achieve the objective of the present disclosure. For example, the average particle size of the ceramic powder may be controlled to be 400 nm or less, but is not limited thereto.
The cover layers 112 and 113 may have the same material and configuration as those of the dielectric layers 111 except that internal electrodes are not included therein.
In addition, the cover layers 112 and 113 may be formed by further stacking a single dielectric layer or two or more dielectric layers on both side surfaces of the active portion in the width direction, respectively, and generally preventing the first and second internal electrodes 120 and 130 from being damaged by physical or chemical stress.
The first and second internal electrodes 120 and 130, having different polarities, may be formed in the ceramic body 110 and disposed to face each other, while having the dielectric layers 111 interposed therebetween.
In this case, the first and second internal electrodes 120 and 130 may be electrically insulated from each other by the dielectric layers 111 disposed therebetween.
The first and second internal electrodes 120 and 130 may include capacitance portions formed by overlapping the internal electrodes adjacent thereto and contributing to capacitance formation, and lead portions formed by extending portions of the capacitance portions to be exposed outwardly from the ceramic body 110.
The lead portions are not particularly limited, but may be shorter than the capacitance portion of the internal electrodes.
Further, a thickness of the first and second internal electrodes 120 and 130 may be determined according to an intended use thereof. For example, the thickness of each of the first and second internal electrodes 120 and 130 may be determined to be within a range of 0.2 μm to 1.0 μm in consideration of a size of the ceramic body 110, but is not limited thereto.
In addition, a material for forming the first and second internal electrodes 120 and 130 is not particularly limited. For example, the first and second internal electrodes 120 and 130 may be formed using a conductive paste formed of at least one of a noble metal material such as palladium (Pd), a palladium silver (Pd—Ag) alloy, or the like, nickel (Ni), and copper (Cu).
Further, as a method for printing the conductive paste, a screen printing method, a gravure printing method, or the like, may be used, but the present disclosure is not limited thereto.
In the present exemplary embodiment, the first internal electrode 120 may have first and second lead portions 121 and 122 spaced apart from each other in the length direction and exposed to the first surface S1 of the ceramic body 110, and may be formed to be spaced apart from the third and fourth surfaces S3 and S4 by a predetermined distance.
In addition, the second internal electrode 130 may have a third lead portion 131 exposed to the first surface S1 of the ceramic body 110 and spaced apart from each of the first and second lead portions 121 and 122 by a predetermined distance between the first and second lead portions 121 and 122, and may be formed to be spaced apart from the third and fourth surfaces S3 and S4 by a predetermined distance.
In this case, the larger value of intervals (a1+b1+c1 and a2+b2+2) between the adjacent lead portions may be 500.7 μm or less.
In a case in which the larger value of the intervals (a1+b1+c1 and a2+b2+c2) between the adjacent lead portions is greater than 500.7 μm, it may be difficult to satisfy equivalent series inductance (ESL) of 50 pH or less, such that it may be difficult to achieve low ESL.
In a general multilayer ceramic electronic component, external electrodes may be disposed on both side surfaces of a ceramic body opposing each other in a length direction.
However, in a case in which an alternating current (AC) voltage is applied to the external electrodes, a current path is relatively long, and thus a current loop may be extended, and an intensity of an induced magnetic field may be increased, whereby inductance may be increased.
In order to solve such a defect, according to an exemplary embodiment in the present disclosure, the first and second external electrodes 141 and 142 may be disposed on the first surface S1 of the ceramic body 110, and the third external electrode 143 may be disposed on the first surface S1 between the first and second external electrodes 141 and 142.
In this case, since intervals between the first and second external electrodes 141 and 142 and the third external electrode 143 may be short, the current loop may be decreased, resulting in reduced inductance.
The first and second external electrodes 141 and 142 may be formed on the first surface S1 of the ceramic body 110 to be spaced apart from each other in the length direction and may be connected to first and second lead portions 121 and 122, and the third external electrode 143 may be formed on the first surface S1 of the ceramic body 110 between the first and second external electrodes 141 and 142 to be spaced apart from the first and second external electrodes 141 and 142 by a predetermined distance and may be connected to the third lead portion 131.
In addition, the first to third external electrodes 141 to 143 may be electrically connected to the lead portions of the first and second internal electrodes 120 and 130 and disposed in positions corresponding thereto, respectively, in order to form capacitance, and if necessary, the first to third external electrodes 141 to 143 may be extended to portions of the fifth and sixth surfaces S5 and S6 of the ceramic body 110 in the width direction and the extended portions thereof form bands.
In this case, the smallest value of widths a1, a2, c1, and c2 of one-side margin portions of the first to third external electrodes 141 to 143 in the length direction of the ceramic body that are not in contact with the corresponding lead portions may be 20.2 μm or more.
In a case in which the smallest value of the widths a1, a2, c1, and c2 of the one-side margin portions of the first to third external electrodes 141 to 143 that are not in contact with the corresponding lead portions is less than 20.2 μm, high temperature load reliability and moisture resistance load reliability may be deteriorated.
Further, the smaller value of intervals b1 and b2 between the adjacent external electrodes may be 126.9 μm or more.
In a case in which the smaller value of the intervals b1 and b2 between the adjacent external electrodes is less than 126.9 μm, short-circuits may occur at the time of mounting the multilayer ceramic capacitor on a board.
In addition, heights d of the bands of the first to third external electrodes 141 to 143 may be 73.4 μm or more, respectively.
In this case, the heights d of the bands of the first to third external electrodes 141 to 143 may be equal to or less than the overall height Tc of the capacitor.
Further, in a case in which the heights d of the bands of the first to third external electrodes 141 to 143 are 73.4 μm or more, adhesion strength may be improved to prevent the occurrence of defects, and in a case in which the heights d of the bands of the first to third external electrodes 141 to 143 are less than 73.4 μm, adhesion strength defects may occur in the first to third external electrodes 141 to 143.
Meanwhile, the first to third external electrodes 141 to 143 may have a three-layer structure and include first to third conductive layers 141 a to 143 a in contact with the corresponding lead portions of the internal electrodes, first to third nickel (Ni) plating layers 141 b to 143 b formed to cover the first to third conductive layers 141 a to 143 a, and first to third tin (Sn) plating layers 141 c to 143 c formed to cover the first to third nickel plating layers 141 b to 143 b.
The first to third conductive layers 141 a to 143 a may be formed of the same conductive material as that of the first and second internal electrodes 120 and 130, but are not limited thereto. For example, the first to third conductive layers 141 a to 143 a may be formed of a metal powder such as copper (Cu), silver (Ag), nickel (Ni), and the like, and may be formed by applying a conductive paste prepared by adding a glass frit to the metal powder and then sintering the applied conductive paste.
FIG. 5 is a perspective view illustrating a structure of a multilayer ceramic capacitor 100′ including external electrodes having shapes different from those illustrated in FIG. 1.
Referring to FIG. 5, first to third external electrodes 141′ to 143′ may be electrically connected to the lead portions of the first and second internal electrodes 120 and 130, respectively, in order to form capacitance, and may be extended to portions of the fifth and sixth surfaces S5 and S6 of the ceramic body 110 in the width direction such that the extended portions thereof form first bands, as needed. In addition, the first and second external electrodes 141′ and 142′ may be extended to portions of the third and fourth surfaces S3 and S4 of the ceramic body 110 in the length direction and the extended portions thereof form second bands.
In this case, heights d of the first bands of the first to third external electrodes 141′ to 143′ may be 40.0 μm or more, and heights e of the second bands of the first and second external electrodes 141′ and 142′ may be 30.3 μm or more, respectively.
In this case, the heights d of the first bands of the first to third external electrodes 141′ to 143′ may be equal to or less than the overall height of the capacitor, and the heights e of the second bands of the first and second external electrodes 141′ and 142′ may be equal to or less than the overall height of the capacitor. That is, the sum (d+e) of the heights of the first band and the second band may be equal to or less than two times the overall height of the capacitor.
Further, in a case in which the sum of the heights d of the first bands of the first to third external electrodes 141′ to 143′ and the heights e of the second bands of the first and second external electrodes 141′ and 142′ is less than 64.1 μm, adhesion strength defects may occur in the first to third external electrodes 141′ to 143′.
Experimental Example
Multilayer ceramic capacitors according to Inventive and Comparative Examples were manufactured as follows.
Slurry containing a powder such as a barium titanate (BaTiO3) powder, or the like, was applied to carrier films and then dried to prepare a plurality of ceramic green sheets having a thickness of 1.8 μm.
Next, first and second internal electrodes were formed by applying a conductive paste for nickel internal electrodes to the ceramic green sheets using a screen, each first internal electrode having first and second lead portions exposed to a side (first main surface) of a corresponding ceramic green sheet and each second internal electrode having a third lead portion spaced apart from the first and second lead portions and exposed to a side (first main surface) of a corresponding ceramic green sheet.
Then, about 200 ceramic green sheets were stacked, and one or more ceramic green sheets on which the first and second internal electrodes were not formed were further stacked on both side surfaces of the stacked ceramic green sheets in a width direction, thereby manufacturing a multilayer body. Thereafter, isostatic pressing was performed on the multilayer body at 85° C. and a pressure of 1000 kgf/cm2.
Next, the pressed ceramic multilayer body was cut into individual chips, and each chip was subjected to a debinding process by maintaining at a temperature of 230° C. for 60 hours under air atmosphere.
Next, the chip was sintered at a temperature of about 1200° C. under reducing atmosphere having an oxygen partial pressure of 10−11 to 10−10 atm lower than a Ni/NiO balanced oxygen partial pressure to prevent the internal electrodes from being oxidized, thereby preparing a ceramic body.
A chip size of the multilayer chip capacitor after being sintered was about 1.6 mm×0.8 mm (Length×Width (L×W), 1608 size). Here, a manufacturing tolerance was determined to be within a range of ±0.1 mm (length×width (L×W)).
Thereafter, a process of forming first to third external electrodes was performed on the first surface of the ceramic body so as to correspond to lead portions of the first and second internal electrodes, respectively, to thereby complete a multilayer ceramic capacitor. Then, tests for measuring the presence or absence of defects occurring at the time of high temperature/moisture resistance loading, short defect rates at the time of mounting the capacitor, the presence or absence of adhesion strength defects, and equivalent serial inductance (ESL) were performed. The test results are provided in Table 1. Each of the tests was performed on 100 test samples.
[Table 1]
No a1 a2 b1 b2 c1 c2 d e d + e
 1* 10.4 um 11.3 um 277.2 um 272.5 um 11.8 um 12.4 um 147.2 um 0.0 um 147.2 um
2 21.2 um 20.4 um 258.4 um 254.0 um 20.2 um 22.1 um 147.7 um 0.0 um 147.7 um
3 50.6 um 48.2 um 196.8 um 203.2 um 49.7 um 49.0 um 148.1 um 0.0 um 148.1 um
4 86.4 um 86.1 um 126.9 um 128.1 um 85.4 um 86.0 um 148.2 um 0.0 um 148.2 um
 5* 104.2 um  102.8 um   95.7 um  96.2 um 100.1 um  101.7 um  147.9 um 0.0 um 147.9 um
 6* 10.5 um 11.1 um 377.3 um 372.9 um 11.5 um 12.1 um 148.0 um 0.0 um 148.0 um
7 20.9 um 20.5 um 358.5 um 354.1 um 20.7 um 21.8 um 148.4 um 0.0 um 148.4 um
8 50.8 um 48.0 um 297.1 um 303.4 um 49.5 um 48.6 um 148.3 um 0.0 um 148.3 um
9 86.4 um 86.0 um 227.2 um 228.3 um 85.5 um 85.7 um 148.1 um 0.0 um 148.1 um
10  104.0 um  103.1 um  195.6 um 196.5 um 99.9 um 101.7 um  148.1 um 0.0 um 148.1 um
11* 10.1 um 10.6 um 477.6 um 473.0 um 11.8 um 12.5 um 147.6 um 0.0 um 147.6 um
12  20.6 um 20.7 um 458.6 um 454.1 um 20.6 um 22.1 um 148.3 um 0.0 um 148.3 um
13  50.9 um 48.3 um 397.3 um 403.3 um 49.9 um 48.3 um 148.4 um 0.0 um 148.4 um
14  86.5 um 86.4 um 327.3 um 328.1 um 85.3 um 85.7 um 148.1 um 0.0 um 148.1 um
15  103.7 um  102.6 um  295.9 um 296.2 um 100.0 um  101.9 um  148.2 um 0.0 um 148.2 um
16*  9.7 um 11.0 um 577.3 um 572.7 um 12.3 um 12.8 um 147.5 um 0.0 um 147.5 um
17* 20.3 um 20.4 um 559.1 um 554.2 um 20.4 um 22.5 um 148.0 um 0.0 um 148.0 um
18* 50.7 um 48.2 um 496.9 um 503.4 um 49.7 um 48.6 um 148.1 um 0.0 um 148.1 um
19* 86.4 um 86.3 um 427.7 um 427.6 um 85.4 um 85.9 um 148.1 um 0.0 um 148.1 um
20* 103.2 um  102.8 um  395.8 um 396.2 um 100.3 um  102.0 um  147.8 um 0.0 um 147.8 um
21  50.7 um 48.3 um 196.6 um 203.1 um 49.8 um 49.0 um 110.3 um 0.0 um 110.3 um
22  50.8 um 48.0 um 196.7 um 203.4 um 50.2 um 49.1 um  73.4 um 0.0 um  73.4 um
23* 51.0 um 47.6 um 196.9 um 203.0 um 49.8 um 49.4 um  49.4 um 0.0 um  49.4 um
24* 51.1 um 47.5 um 197.3 um 203.0 um 49.5 um 49.1 um  0.0 um 0.0 um  0.0 um
25* 51.1 um 47.2 um 197.0 um 203.0 um 49.5 um 48.6 um 39.8 um 15.2 um   55.0 um
26  51.4 um 47.3 um 196.7 um 203.2 um 49.1 um 48.3 um 40.0 um 30.3 um   70.3 um
27  51.8 um 46.9 um 196.7 um 202.9 um 48.8 um 47.9 um 39.6 um 66.4 um  106.0 um
28  51.7 um 47.1 um 197.2 um 202.8 um 48.3 um 47.5 um 39.4 um 102.4 um  141.8 um
29  51.2 um 46.9 um 196.9 um 203.0 um 49.2 um 48.7 um 48.8 um 15.3 um   64.1 um
30  50.9 um 47.2 um 196.7 um 202.8 um 49.7 um 48.7 um 48.7 um 30.3 um   78.9 um
31  50.9 um 47.6 um 197.1 um 203.0 um 49.7 um 48.6 um 48.6 um 66.8 um  115.5 um
32  51.0 um 47.8 um 196.7 um 203.2 um 49.6 um 48.8 um 48.8 um 101.9 um  150.7 um
33  51.2 um 47.8 um 196.3 um 203.1 um 49.8 um 48.4 um 72.3 um 15.4 um   87.7 um
34  51.5 um 47.4 um 196.5 um 203.3 um 49.6 um 48.7 um 72.7 um 30.1 um  102.9 um
35  51.5 um 47.8 um 196.9 um 203.0 um 49.8 um 48.2 um 73.0 um 67.3 um  140.2 um
36  51.6 um 47.9 um 197.4 um 202.6 um 49.8 um 48.2 um 73.4 um 101.9 um  175.4 um
NG rate at Time of
High Temperature Short-Circuit Adhesion
max(a1 + b1 + c1, Loading/Moisture Defect Rate at the Strength
No a2 + b2 + c2) min(a1, a2, c1, c2) min(b1, b2) ESL Resistance Loading Time of Mounting NG rate
 1* 299.4 um 10.4 um 272.5 um 38.2 pH 3/800 0/100 0/10
2 299.8 um 20.2 um 254.0 um 38.5 pH 0/800 0/100 0/10
3 300.4 um 48.2 um 196.8 um 38.0 pH 0/800 0/100 0/10
4 300.2 um 85.4 um 126.9 um 38.5 pH 0/800 0/100 0/10
 5* 300.7 um 100.1 um   95.7 um 38.1 pH 0/800 47/100  0/10
 6* 399.3 um 10.5 um 372.9 um 43.7 pH 2/800 0/100 0/10
7 400.0 um 20.5 um 354.1 um 43.6 pH 0/800 0/100 0/10
8 400.1 um 48.0 um 297.1 um 43.5 pH 0/800 0/100 0/10
9 400.0 um 85.5 um 227.2 um 44.0 pH 0/800 0/100 0/10
10  401.3 um 99.9 um 195.6 um 43.7 pH 0/800 0/100 0/10
11* 499.5 um 10.1 um 473.0 um 48.2 pH 5/800 0/100 0/10
12  499.9 um 20.6 um 454.1 um 48.3 pH 0/800 0/100 0/10
13  499.8 um 48.3 um 397.3 um 48.8 pH 0/800 0/100 0/10
14  500.2 um 85.3 um 327.3 um 49.3 pH 0/800 0/100 0/10
15  500.7 um 100.0 um  295.9 um 48.3 pH 0/800 0/100 0/10
16* 599.3 um  9.7 um 572.7 um 57.0 pH 1/800 0/100 0/10
17* 599.8 um 20.3 um 554.2 um 57.4 pH 0/800 0/100 0/10
18* 600.2 um 48.2 um 496.9 um 57.5 pH 0/800 0/100 0/10
19* 599.8 um 85.4 um 427.6 um 58.2 pH 0/800 0/100 0/10
20* 601.0 um 100.3 um  395.8 um 57.3 pH 0/800 0/100 0/10
21  300.3 um 48.3 um 196.6 um 39.1 pH 0/800 0/100 0/10
22  300.4 um 48.0 um 196.7 um 39.2 pH 0/800 0/100 0/10
23* 300.0 um 47.6 um 196.9 um 39.2 pH 0/800 0/100 2/10
24* 299.7 um 47.5 um 197.3 um 39.1 pH 0/800 0/100 10/10 
25* 298.7 um 47.2 um 197.0 um 38.9 pH 0/800 0/100 6/10
26  298.9 um 47.3 um 196.7 um 39.3 pH 0/800 0/100 0/10
27  297.7 um 46.9 um 196.7 um 39.3 pH 0/800 0/100 0/10
28  297.4 um 47.1 um 197.2 um 39.6 pH 0/800 0/100 0/10
29  298.6 um 46.9 um 196.9 um 39.4 pH 0/800 0/100 0/10
30  298.7 um 47.2 um 196.7 um 39.6 pH 0/800 0/100 0/10
31  299.1 um 47.6 um 197.1 um 39.4 pH 0/800 0/100 0/10
32  299.8 um 47.8 um 196.7 um 39.6 pH 0/800 0/100 0/10
33  299.2 um 47.8 um 196.3 um 39.5 pH 0/800 0/100 0/10
34  299.4 um 47.4 um 196.5 um 39.0 pH 0/800 0/100 0/10
35  299.0 um 47.8 um 196.9 um 39.2 pH 0/800 0/100 0/10
36  298.8 um 47.9 um 197.4 um 39.0 pH 0/800 0/100 0/10
Referring to Table 1, it can be seen that preferably, the maximum value (max(a1+b1+c1, a2+b2+c2)) of intervals between the adjacent lead portions was 500.7 μm or less, and in cases of samples 16 to 20 in which the maximum value (max(a1+b1+c1, a2+b2+c2)) of the intervals between the adjacent lead portions was greater than 500.7 μm, ESL was greater than 50 pH, and thus, it was difficult to obtain low ESL.
In this case, the minimum of the smaller value of the intervals a1+b1+c1 and a2+b2+c2 between the adjacent lead portions may be equal to the sum of the minimum of the smaller value of the intervals b1 and b2 between the adjacent external electrodes and the minimum of the smaller value of widths a1+c1 and a2+c2 of the one-side margin portions of the external electrodes in the length direction of the ceramic body that are not in contact with the lead portions. Accordingly, the smaller value of the intervals a1+b1+c1 and a2+b2+c2 between the adjacent lead portions may preferably be 167.3 μm or more.
Further, it can be seen that preferably, the minimum value (min(a1, a2, c1, c2)) of the widths of the one-side margin portions of the first to third external electrodes 141 to 143 that are not in contact with the lead portions was 20.2 μm or more, and in the cases of samples 1, 6, 11, and 16 in which the minimum value (min(a1, a2 , c1, c2)) of the widths of the one-side margin portions of the first to third external electrodes 141 to 143 that are not in contact with the lead portions was less than 20.2 μm, high temperature load reliability and moisture resistance load reliability were deteriorated.
In this case, the maximum of the largest value of the widths a1, a2, c1 and c2 of the one-side margin portions of the external electrodes that are not in contact with the lead portions may be equal to a half of a value obtained by subtracting the minimum of the smaller value of the intervals b1 and b2 between the adjacent external electrodes from the maximum (max(a1+b1+c1, a2+b2+2)) of the larger value of the intervals between the adjacent lead portions.
Accordingly, the largest value of the widths a1, a2, c1, and c2 of the one-side margin portions of the external electrodes that are not in contact with the lead portions may be 186.9 μm or less.
In addition, it can be seen that preferably, the larger value of the intervals b1 and b2 between the adjacent external electrodes was 126.9 μm or more, and in the case of sample 5 in which the larger value of the intervals b1 and b2 between the adjacent external electrodes was less than 126.9 μm, short-circuit defects occurred at the time of mounting the multilayer ceramic capacitor on a board.
In this case, the maximum of the larger value of the intervals b1 and b2 between the adjacent external electrodes may be equal to a value obtained by subtracting a value equal to twice the minimum of the smallest value of the widths a1, a2, c1, and c2 of the one-side margin portions of the external electrodes that are not in contact with the lead portions, from the maximum of the larger value of the intervals a1+b1+c1 and a2+b2+c2 between the adjacent lead portions. Therefore, the maximum of the larger value of the intervals b1 and b2 between the adjacent external electrodes may be 460.3 μm or less.
Further, it can be seen that preferably, the first to third external electrodes 141 to 143 had bands extended to portions of the fifth and sixth surfaces S5 and S6 of the ceramic body 110 in the width direction and the heights d of the bands were preferably 73.4 μm.
In the case of sample 23 in which the heights d of the bands of the first to third external electrodes 141 to 143 were less than 73.4 μm, an adhesion strength defect occurred.
Meanwhile, samples 25 to 36 had structures in which the first to third external electrodes 141 to 143 had first bands extended to portions of the fifth and sixth surfaces S5 and S6 of the ceramic body 110 in the width direction, and the first and second external electrodes 141 and 142 had second bands extended to portions of the third and fourth surfaces S3 and S4 of the ceramic body 110 in the length direction.
In this case, referring to samples 26 to 36, it can be seen that the sum of the heights d of the first bands of the first to third external electrodes 141 to 143 and the heights e of the second bands of the first and second external electrodes 141 and 142 was 64.1 μm or more when the adhesion strength defects of the external electrodes did not occur.
In the case of sample 25 in which the sum (d+e) of the heights of the first band and the second band was less than 64.1 μm, an adhesion strength defect occurred.
Modified Example
FIG. 6 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure, and FIG. 7 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 6 in a state in which external electrodes thereof are omitted.
Here, since the structure of the ceramic body 110 is the same as that in the previous exemplary embodiment, a detailed description thereof will be omitted in order to avoid redundancy, and structures of first and second internal electrodes 120 and 130 different from those in the previous exemplary embodiment and an insulating layer 150 will be described in detail.
Referring to FIGS. 6 and 7, in a multilayer ceramic capacitor 100″ according to the present exemplary embodiment, the insulating layer 150 may be disposed on the second surface S2 of the ceramic body 110 opposing the mounting surface of the ceramic body 110.
The first internal electrode 120 may have fourth and fifth lead portions 123 and 124 exposed to the second surface S2 of the ceramic body 110 to come into contact with the insulating layer 150 formed on the second surface S2 of the ceramic body 110.
The second internal electrode 130 may have a sixth lead portion 132 disposed between the fourth and fifth lead portions 123 and 124 and exposed to the second surface S2 of the ceramic body 110 to come into contact with the insulating layer 150.
FIG. 8 is a perspective view schematically illustrating a multilayer ceramic capacitor according to another exemplary embodiment in the present disclosure; FIG. 9 is a perspective view illustrating a ceramic body of the multilayer ceramic capacitor of FIG. 9; FIG. 10 is an exploded perspective view illustrating the multilayer ceramic capacitor of FIG. 8 in a state in which external electrodes thereof are omitted; and FIG. 11 is a cross-sectional view illustrating the multilayer ceramic capacitor of FIG. 8.
Here, since the structure of the ceramic body 110 is the same as that in the previous exemplary embodiment, a detailed description thereof will be omitted in order to avoid redundancy, and structures of fourth to sixth external electrodes 144 to 146 and first and second internal electrodes 120 and 130 different from those in the previous exemplary embodiment will be described in detail.
Referring to FIGS. 8 through 11, a multilayer ceramic capacitor 1000 according to the present exemplary embodiment, the fourth to sixth external electrodes 144 to 146 may be disposed on the second surface S2 of the ceramic body 110 so as to face the first to third external electrodes 141 to 143.
In this case, the fourth to sixth external electrodes 144 to 146 may be extended to portions of the fifth and sixth surfaces S5 and S6 of the ceramic body 110 in the width direction, as needed.
The fourth to sixth external electrodes 144 to 146 may have a three-layer structure and include fourth to sixth conductive layers 144 a to 146 a in contact with the lead portions of the internal electrodes disposed in positions corresponding to the conductive layers, respectively, fourth to sixth nickel (Ni) plating layers 144 b to 146 b formed to cover the fourth to sixth conductive layers 144 a to 146 a, respectively and fourth to sixth tin (Sn) plating layers 144 c to 146 c formed to cover the fourth to sixth nickel plating layers 144 b to 146 b, respectively.
The first internal electrode 120 may have the fourth and fifth lead portions 123 and 124 exposed to the second surface S2 of the ceramic body 110 to thereby be connected to the fourth and fifth external electrodes 144 and 145 formed on the second surface S2 of the ceramic body 110, respectively.
The second internal electrode 130 may have the sixth lead portion 132 disposed between the fourth and fifth lead portions 123 and 124 and exposed to the second surface S2 of the ceramic body 110 to thereby be connected to the sixth external electrode 146.
As described above, in the case in which the internal and external structures of the multilayer ceramic capacitor 1000 are formed to be vertically symmetrical, directionality of the capacitor may be removed.
That is, the multilayer ceramic capacitor 1000 has a vertically symmetrical structure, such that, a defect occurring when a mounting surface is reversed at the time of mounting the multilayer ceramic capacitor 1000 on a board may be prevented.
Therefore, since any surface of the first and second surfaces S1 and S2 of the multilayer ceramic capacitor 1000 is used as a mounting surface, there is no need to consider a direction of the mounting surface at the time of mounting the multilayer ceramic capacitor 1000 on the board.
In this case, the smallest value of the widths a1, a2, c1, and c2 of one-side margin portions of the fourth to sixth external electrodes 144 to 146 in the length direction of the ceramic body that are not in contact with the corresponding lead portions may be 20.2 μm or more.
In a case in which the smallest value of the widths a1, a2, c1, and c2 of the one-side margin portions of the fourth to sixth external electrodes 144 to 146 that are not in contact with the corresponding lead portions is less than 20.2 μm, high temperature load reliability and moisture resistance load reliability may be deteriorated.
In addition, the smaller value of intervals b1 and b2 between the adjacent external electrodes may be 126.9 μm or more.
In a case in which the smaller value of the intervals b1 and b2 between the adjacent external electrodes less than 126.9 μm, short-circuits may occur at the time of mounting the multilayer ceramic capacitor on a board.
In addition, heights d of bands of the fourth to sixth external electrodes 144 to 146 may be 73.4 μm or more, respectively.
In a case in which the heights d of the bands of the fourth to sixth external electrodes 144 to 146 are 73.4 μm or more, adhesion strength may be improved, such that adhesion strength defects may not occur, and in a case in which the heights d of the bands of the fourth to sixth external electrodes 144 to 146 are less than 73.4 μm, adhesion strength defects may occur in the fourth to sixth external electrodes 144 to 146.
FIG. 12 is a perspective view illustrating a structure of a multilayer ceramic capacitor 1000′ including external electrodes having shapes different from those illustrated in FIG. 8.
Referring to FIG. 12, fourth to sixth external electrodes 144′ to 146′ may be electrically connected to the corresponding lead portions of the first and second internal electrodes 120 and 130, respectively, in order to form capacitance and may be extended to portions of the fifth and sixth surfaces S5 and S6 of the ceramic body 110 in the width direction to form first bands, as needed. In addition, the fourth and fifth external electrodes 144′ and 145′ may be extended to portions of the third and fourth surfaces S3 and S4 of the ceramic body 110 in the length direction to form second bands, as needed.
In this case, heights d of the first bands of the fourth to sixth external electrodes 144′ to 146′ may be 40.0 μm or more, respectively, and heights e of the second bands of the fourth and fifth external electrodes 144′ and 145′ may be 30.3 μm or more, respectively.
In a case in which the sum of the heights d of the first bands of the fourth to sixth external electrodes 144′ to 146′ and the heights e of the second bands of the fourth and fifth external electrodes 144′ and 145′ is less than 64.1 μm, adhesion strength defects may occur in the fourth to sixth external electrodes 144′ to 146′.
Meanwhile, thicknesses of the conductive layers and the plating layers of the first to third external electrodes, the results obtained by testing for the presence or absence of a defect occurring at the time of high temperature/moisture resistance loading, a short defect rate at the time of mounting the capacitor, the presence or absence of adhesion strength defects, and by measuring equivalent serial inductance (ESL), as illustrated in Table 1, may be equally applied to the fourth to sixth external electrodes.
Board Having Multilayer Ceramic Capacitor
FIG. 13 is a perspective view illustrating a board on which the multilayer ceramic capacitor of FIG. 8 is mounted, and FIG. 14 is a cross-sectional view of FIG. 13.
Referring to FIGS. 13 and 14, a board 200 having a multilayer ceramic capacitor according to the present exemplary embodiment may include a circuit board 210 on which the multilayer ceramic capacitor is mounted and first to third electrode pads 221 to 223 formed on the circuit board 210 to be spaced apart from each other.
In this case, the multilayer ceramic capacitor may be electrically connected to the circuit board 210 by solders 230 in a state in which first to third external electrodes 141 to 143 are positioned to contact the first to third electrode pads 221 to 223.
In FIG. 14, reference numeral 224 indicates a ground terminal, and reference numeral 225 indicates a power terminal.
Meanwhile, although the case in which the multilayer ceramic capacitor of FIG. 8 is mounted is described in the present exemplary embodiment, the present disclosure is not limited thereto. For example, the multilayer ceramic capacitors illustrated in FIGS. 1, 5, 8, and 12 may be similarly mounted on a circuit board to thereby configure boards having multilayer ceramic capacitors.
As set forth above, according to exemplary embodiments in the present disclosure, the intervals between adjacent lead portions of the internal electrodes and the widths of the one-side margin portions of the external electrodes that are not in contact with the corresponding lead portions may be controlled, such that low ESL characteristics may be maintained, and reliability and adhesion strength may be improved.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.

Claims (24)

What is claimed is:
1. A multilayer ceramic capacitor, comprising:
a ceramic body in which a plurality of dielectric layers are layered;
an active portion in which a plurality of first and second internal electrodes are alternately disposed, having at least one of the dielectric layers interposed therebetween;
first and second lead portions extended from each of the first internal electrodes so as to be exposed to a mounting surface of the ceramic body, and disposed to be spaced apart from each other in a length direction of the ceramic body;
a third lead portion extended from each of the second internal electrodes so as to be exposed to the mounting surface of the ceramic body, and disposed between the first and second lead portions;
first and second external electrodes disposed on the mounting surface of the ceramic body to be spaced apart from each other in the length direction of the ceramic body, connected to the first and second lead portions, respectively; and
a third external electrode disposed on the mounting surface of the ceramic body between the first and second external electrodes, connected to the third lead portion,
wherein an interval between adjacent lead portions is in a range of 167.3 μm to 500.7 μm,
widths of one-side margin portions of the first to third external electrodes in the length direction of the ceramic body that are not in contact with the corresponding lead portions are in a range of 20.2 μm to 186.9 μm,
an interval between the first or second external electrode and the third external electrode is in a range of 126.9 μm to 458.6 μm,
the first and second external electrodes have first bands extended to portions of both side surfaces of the ceramic body in the width direction, respectively, and
heights of the first bands of the first and second external electrodes are 72.3 μm or more, respectively, and are equal to or less than an overall height of the capacitor.
2. The multilayer ceramic capacitor of claim 1, wherein the first and second internal electrodes are disposed to be spaced apart from both side surfaces of the ceramic body in the length direction.
3. The multilayer ceramic capacitor of claim 1, further comprising:
fourth and fifth lead portions extended from each of the first internal electrodes so as to be exposed to a surface of the ceramic body opposing the mounting surface of the ceramic body, and disposed to be spaced apart from each other in the length direction of the ceramic body;
a sixth lead portion extended from each of the second internal electrodes so as to be exposed to the surface of the ceramic body opposing the mounting surface of the ceramic body, and disposed between the fourth and fifth lead portions; and
an insulating layer disposed on the surface of the ceramic body opposing the mounting surface of the ceramic body.
4. A board having a multilayer ceramic capacitor comprising:
a circuit board on which first to third electrode pads are provided; and
the multilayer ceramic capacitor of claim 3,
wherein the first to third external electrodes are mounted on the first to third electrode pads, respectively.
5. The multilayer ceramic capacitor of claim 1, further comprising:
fourth and fifth external electrodes disposed on a surface of the ceramic body opposing the mounting surface of the ceramic body to be spaced apart from each other in the length direction; and
a sixth external electrode disposed on the surface of the ceramic body opposing the mounting surface of the ceramic body to be spaced apart from the fourth and fifth external electrodes,
wherein each of the first internal electrodes has fourth and fifth lead portions spaced apart from each other in the length direction and exposed to the surface of the ceramic body opposing the mounting surface of the ceramic body,
each of the second internal electrodes has a sixth lead portion exposed to the surface of the ceramic body opposing the mounting surface of the ceramic body and disposed between the fourth and fifth lead portions to be spaced apart from the fourth and fifth lead portions,
the fourth and fifth external electrodes are connected to the fourth and fifth lead portions, respectively, and
the sixth external electrode is connected to the sixth lead portion.
6. The multilayer ceramic capacitor of claim 5, wherein widths of one-side margin portions of the fourth to sixth external electrodes in the length direction of the ceramic body that are not in contact with the corresponding lead portions are in a range of 20.2 μm to 186.9 μm.
7. The multilayer ceramic capacitor of claim 5, wherein an interval between the fourth or fifth external electrode and the sixth external electrode is in a range of 126.9 μm to 458.6 μm.
8. The multilayer ceramic capacitor of claim 5, wherein the fourth and fifth external electrodes have first bands extended to portions of both side surfaces of the ceramic body in the width direction, respectively, and
the fourth and fifth external electrodes have second bands extended to portions of both end surfaces of the ceramic body in the length direction, respectively.
9. The multilayer ceramic capacitor of claim 5, wherein the fourth and fifth external electrodes have second bands extended to portions of both end surfaces of the ceramic body in the length direction, respectively.
10. The multilayer ceramic capacitor of claim 5, wherein the sixth external electrode has first bands extended to portions of both side surfaces of the ceramic body in the width direction.
11. The multilayer ceramic capacitor of claim 1, further comprising cover layers provided on both side surfaces of the active portion in the width direction.
12. A board having a multilayer ceramic capacitor comprising:
a circuit board on which first to third electrode pads are provided; and
the multilayer ceramic capacitor of claim 1,
wherein the first to third external electrodes are mounted on the first to third electrode pads, respectively.
13. The multilayer ceramic capacitor of claim 1, wherein the first and second external electrodes have second bands extended to portions of both end surfaces of the ceramic body in the length direction, respectively.
14. The multilayer ceramic capacitor of claim 1, wherein the third external electrode has first bands extended to portions of both side surfaces of the ceramic body in the width direction.
15. A multilayer ceramic capacitor, comprising:
a ceramic body in which a plurality of dielectric layers are layered;
an active portion in which a plurality of first and second internal electrodes are alternately disposed, having at least one of the dielectric layers interposed therebetween;
first and second lead portions extended from each of the first internal electrodes so as to be exposed to a mounting surface of the ceramic body, and disposed to be spaced apart from each other in a length direction of the ceramic body;
a third lead portion extended from each of the second internal electrodes so as to be exposed to the mounting surface of the ceramic body, and disposed between the first and second lead portions;
first and second external electrodes disposed on the mounting surface of the ceramic body to be spaced apart from each other in the length direction of the ceramic body, connected to the first and second lead portions, respectively, and having first bands extended to portions of both side surfaces of the ceramic body in the width direction and second bands extended to portions of both end surfaces of the ceramic body in the length direction; and
a third external electrode disposed on the mounting surface of the ceramic body between the first and second external electrodes, connected to the third lead portion, and having first bands extended to portions of both side surfaces of the ceramic body,
wherein an interval between adjacent lead portions is in a range of 167.3 μm to 500.7 μm,
widths of one-side margin portions of the first to third external electrodes in the length direction of the ceramic body that are not in contact with the corresponding lead portions are in a range of 20.2 μm to 186.9 μm,
an interval between the first or second external electrode and the third external electrode is in a range of 126.9 μm to 458.6 μm, and
the sum of the heights of the first and second bands of each of the first and second electrodes in a range of 64.1 μm to 175.4 μm.
16. The multilayer ceramic capacitor of claim 15, wherein an interval between the first or second external electrode and the third external electrode is in a range of 126.9 μm to 458.6 μm.
17. The multilayer ceramic capacitor of claim 15, wherein the sum of heights of the first bands and the second bands is equal to or less than twice an overall height of the capacitor.
18. The multilayer ceramic capacitor of claim 15, wherein the first and second internal electrodes are disposed to be spaced apart from both end surfaces of the ceramic body in the length direction.
19. The multilayer ceramic capacitor of claim 15, further comprising:
fourth and fifth lead portions extended from each of the first internal electrodes so as to be exposed to a surface of the ceramic body opposing the mounting surface of the ceramic body, and disposed to be spaced apart from each other in the length direction of the ceramic body;
a sixth lead portion extended from each of the second internal electrodes so as to be exposed to the surface of the ceramic body opposing the mounting surface of the ceramic body, and disposed between the fourth and fifth lead portions; and
an insulating layer disposed on the surface of the ceramic body opposing the mounting surface of the ceramic body.
20. The multilayer ceramic capacitor of claim 15, further comprising:
fourth and fifth external electrodes disposed on a surface of the ceramic body opposing the mounting surface of the ceramic body to be spaced apart from each other in the length direction; and
a sixth external electrode disposed on the surface opposing the mounting surface of the ceramic body to be spaced apart from the fourth and fifth external electrodes,
wherein each of the first internal electrodes has fourth and fifth lead portions spaced apart from each other in the length direction and exposed to the surface of the ceramic body opposing the mounting surface of the ceramic body,
each of the second internal electrodes has a sixth lead portion exposed to the surface of the ceramic body opposing the mounting surface of the ceramic body and disposed between the fourth and fifth lead portions to be spaced apart from the fourth and fifth lead portions,
the fourth and fifth external electrodes are connected to the fourth and fifth lead portions, respectively, and
the sixth external electrode is connected to the sixth lead portion.
21. The multilayer ceramic capacitor of claim 20, wherein widths of one-side margin portions of the fourth to sixth external electrodes in the length direction of the ceramic body that are not in contact with the corresponding lead portions are in a range of 20.2 μm to 186.9 μm.
22. The multilayer ceramic capacitor of claim 20, wherein an interval between the fourth or fifth external electrode and the sixth external electrode is in a range of 126.9 μm to 458.6 μm.
23. The multilayer ceramic capacitor of claim 20, wherein the fourth to sixth external electrodes have first bands extended to portions of both side surfaces of the ceramic body in the width direction,
the fourth and fifth external electrodes further have second bands extended to portions of both end surfaces of the ceramic body in the length direction, and
the sum of heights of the first bands and the second bands is equal to or less than twice an overall height of the capacitor.
24. The multilayer ceramic capacitor of claim 15, further comprising cover layers disposed on both side surfaces of the active portion in the width direction.
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