KR20140038912A - Multi-layered ceramic capacitor and board for mounting the same - Google Patents

Multi-layered ceramic capacitor and board for mounting the same Download PDF

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Publication number
KR20140038912A
KR20140038912A KR1020130117571A KR20130117571A KR20140038912A KR 20140038912 A KR20140038912 A KR 20140038912A KR 1020130117571 A KR1020130117571 A KR 1020130117571A KR 20130117571 A KR20130117571 A KR 20130117571A KR 20140038912 A KR20140038912 A KR 20140038912A
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South Korea
Prior art keywords
lead
ceramic
main
plating layer
thickness
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KR1020130117571A
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Korean (ko)
Inventor
이병화
이교광
박민철
안영규
박상수
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삼성전기주식회사
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Priority to KR1020130117571A priority Critical patent/KR20140038912A/en
Publication of KR20140038912A publication Critical patent/KR20140038912A/en
Priority claimed from KR20140126164A external-priority patent/KR101514607B1/en
Priority claimed from US14/504,000 external-priority patent/US9460855B2/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/005Electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • H01G4/1209Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10015Non-printed capacitor

Abstract

Provided is a multi-layered ceramic capacitor comprising: a plurality of dielectric layers laminated in a width direction; a first and a second main surfaces facing each other; a ceramic body having a first and a second surfaces facing each other and a first and a second side surface facing each other; a first outputting unit exposed to the first main surface of the ceramic body, formed inside of the ceramic body; a second outputting unit exposed to the second main surface of the ceramic body; a first inner electrode formed apart from the first and second surfaces with a certain distance; a third outputting unit formed apart from the first outputting unit, exposed to the first main surface of the ceramic body; a forth outputting unit formed apart from the second outputting unit, exposed to the second main surface of the ceramic body; an active layer including the second inner electrode apart from the first and second surfaces; a top and a bottom cover layer formed on the first and second side surfaces of the active layer; and a fifth and a sixth outer electrode connected to the first to forth outer electrodes and the second inner electrode connected to the first inner electrode. If the width of the active layer is determined ′AT′, a distance between the first and second outputting units or between the second and forth outputting units is determined ′LG′, LG/AT <= 0.5 is satisfied.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multilayer ceramic capacitor,

The present invention relates to a multilayer ceramic capacitor and a mounting substrate thereof.

With the recent miniaturization and high capacity of electronic products, miniaturization and high capacity of electronic components used in electronic products are also required.

In the case of multilayer ceramic capacitors, the equivalent series inductance (“ESL”) increases, which may degrade the performance of electronic products.Increasing the ESL of multilayer ceramic capacitors increases with the miniaturization and high capacity of the applied electronic components. The impact on the performance degradation of the system becomes relatively large.

In particular, as the performance of ICs increases, the use of decoupling capacitors increases, reducing the distance between external terminals, thereby reducing the current flow path, thereby reducing the inductance of capacitors. Demand for low inductance chip capacitors (LICC) is increasing.

Patent Document 1 discloses a multi-terminal stacked chip capacitor having a low ESL.

Korean Patent Publication No. 2008-0110180

In the art, a new method for maximizing low ESL characteristics in a vertically stacked three-terminal capacitor has been required.

According to an aspect of the present invention, a ceramic body having a plurality of dielectric layers stacked in a width direction and having first and second main surfaces facing each other, first and second sides facing each other, and first and second cross sections facing each other ; Is formed in the ceramic body, and has a first lead portion exposed to the first main surface of the ceramic body and a second lead portion exposed to the second main surface of the ceramic body spaced apart from the first and second cross-sections by a predetermined distance. And exposed to the first internal electrode, the first main surface of the ceramic body, the third lead portion formed to be spaced apart from the first lead portion, and the second main surface of the ceramic body. An active layer having a fourth lead portion formed to be spaced apart from each other by a predetermined distance, and including a second internal electrode spaced apart from the first and second end surfaces by a predetermined distance; Upper and lower cover layers formed on first and second side surfaces of the active layer; And first to fourth external electrodes formed on first and second main surfaces of the ceramic body and connected to the first internal electrode and fifth and sixth external electrodes connected to the second internal electrode. When the width of the active layer is defined by the width of the AT, the first or second lead portion and the third or fourth lead portion as LG, provides a multilayer ceramic capacitor that satisfies LG / AT ≤ 0.5 do.

In one embodiment of the present invention, the gap LG of the first or second lead-out portion and the third or fourth lead-out portion may exceed 100 μm.

According to another aspect of the present invention, a ceramic body having a plurality of dielectric layers stacked in a width direction and having first and second main surfaces facing each other, first and second sides facing each other, and first and second cross sections facing each other ; Is formed in the ceramic body, and has a first lead portion exposed to the first main surface of the ceramic body and a second lead portion exposed to the second main surface of the ceramic body spaced apart from the first and second cross-sections by a predetermined distance. And exposed to the first internal electrode, the first main surface of the ceramic body, the third lead portion formed to be spaced apart from the first lead portion, and the second main surface of the ceramic body. An active layer having a fourth lead portion formed to be spaced apart from each other by a predetermined distance, and including a second internal electrode spaced apart from the first and second end surfaces by a predetermined distance; Upper and lower cover layers formed on first and second side surfaces of the active layer; And first to fourth external electrodes formed on first and second main surfaces of the ceramic body and connected to the first internal electrode and fifth and sixth external electrodes connected to the second internal electrode. It includes, and the thickness of the first to sixth external electrode provides a multilayer ceramic capacitor of 10 to 40 ㎛.

In one embodiment of the present invention, the first to sixth external electrodes cover a conductive layer which is in contact with each corresponding lead portion, a nickel plated layer formed to cover the conductive layer, and the nickel plated layer. It may include a tin (Sn) plating layer formed to be.

In this case, the thickness of the conductive layer may be 5 to 25 ㎛.

In addition, the nickel plating layer may have a thickness of 2 μm or more.

In addition, the tin plating layer may have a thickness of 3 μm or more.

In addition, the sum of the thicknesses of the nickel plating layer and the tin plating layer may be 15 μm or less.

In one embodiment of the present invention, the first lead-out portion may be composed of two lead-out portion formed to be spaced apart from the third lead-out portion, respectively.

In one embodiment of the present invention, the second lead-out portion may be composed of two lead-out portion formed to be spaced apart from the fourth lead-out portion, respectively.

According to one embodiment of the present invention, the width of the active layer and the distance between the first or second lead portion and the third or fourth lead portion can be adjusted to maximize the low ESL characteristic.

1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention.
2 is a schematic diagram showing a ceramic body of a multilayer ceramic capacitor according to an embodiment of the present invention.
FIG. 3 is an exploded perspective view of FIG. 2. FIG.
4 is a cross-sectional view illustrating a multilayer ceramic capacitor according to an embodiment of the present invention.
5 is a perspective view showing a state in which the multilayer ceramic capacitor of FIG. 1 is mounted on a printed circuit board.
6 is a cross-sectional view illustrating a multilayer ceramic capacitor of FIG. 4 mounted on a printed circuit board.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below.

Moreover, embodiment of this invention is provided in order to demonstrate this invention more completely to the person with average knowledge in the technical field.

The shape and size of elements in the drawings may be exaggerated for clarity.

In addition, the components with the same functions within the scope of the same idea shown in the drawings of each embodiment will be described using the same reference numerals.

In order to clarify embodiments of the present invention, the direction of the cube is defined, and L, W, and T shown in FIG. 1 represent a length direction, a width direction, and a thickness direction, respectively. Here, the width direction may be used in the same concept as the stacking direction in which the dielectric layers are stacked.

Multilayer Ceramic Capacitors

1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention, FIG. 2 is a schematic view showing a ceramic body of a multilayer ceramic capacitor according to an embodiment of the present invention, and FIG. 3 is an exploded view of FIG. 2. 4 is a perspective view illustrating a multilayer ceramic capacitor according to an exemplary embodiment of the present invention.

1 to 4, the multilayer ceramic capacitor 100 according to the present embodiment includes a ceramic body 110 in which a plurality of dielectric layers 111 are stacked in a width direction, and a plurality of first and second internal electrodes ( An active layer including 121 and 122, upper and lower cover layers 112 and 113, first to fourth external electrodes 131 to 134 serving as power terminals, and fifth and serving as ground terminals. And sixth external electrodes 135 and 136. That is, the multilayer ceramic capacitor 100 of the present embodiment can be viewed as a so-called three-terminal capacitor having a total of three external terminals.

The ceramic body 110 connects the first main surface S1 and the second main surface S2 in the thickness direction facing each other, and the first main surface S1 and the second main surface S2 in the width direction facing each other. The first side surface S5 and the second side surface S6 may have a first end surface S3 and a second end surface S4 in the longitudinal direction facing each other. Hereinafter, in the present embodiment, the mounting surface of the multilayer ceramic capacitor 100 is defined and described as the second main surface S2 of the ceramic body 110.

The ceramic body 110 is formed by laminating a plurality of dielectric layers 111 in the width direction and then firing the shape, and the shape of the ceramic body 110 may be a hexahedron shape as illustrated. However, the shape, the dimensions of the ceramic body 110, and the number of stacked layers of the dielectric layer 111 are not limited to those shown in this embodiment.

The plurality of dielectric layers 111 forming the ceramic body 110 are in a sintered state and the boundaries between the adjacent dielectric layers 111 are such that it is difficult to confirm without using a scanning electron microscope (SEM) Can be integrated.

The ceramic body 110 includes an active layer having internal electrodes as a part contributing to the formation of a capacitor, and upper and lower cover layers 112 and 113 formed on the first and second side surfaces of the active layer as upper and lower margins, respectively. It can be composed of).

The active layer may be formed by repeatedly stacking a plurality of first and second internal electrodes 121 and 122 with a dielectric layer 111 interposed therebetween.

At this time, the thickness of the dielectric layer 111 can be arbitrarily changed according to the capacity design of the multilayer ceramic capacitor 100. The thickness of one layer may be 0.01 to 1.00 m after firing. However, It is not.

In addition, the dielectric layer 111 may include a ceramic powder having a high dielectric constant, for example, barium titanate (BaTiO 3 ) -based or strontium titanate (SrTiO 3 ) -based powder, and the present invention may be obtained as long as sufficient capacitance can be obtained. It is not limited to this.

In addition, a ceramic additive, an organic solvent, a plasticizer, a binder, a dispersant, and the like may be further added to the dielectric layer 111 when necessary.

In addition, the average particle diameter of the ceramic powder used to form the dielectric layer 111 is not particularly limited and may be adjusted to achieve the object of the present invention, for example, may be adjusted to 400 nm or less.

The upper and lower cover layers 112 and 113 may have the same material and configuration as the dielectric layer 111 except that they do not include internal electrodes.

In addition, the upper and lower cover layers 112 and 113 may be formed by stacking a single dielectric layer or two or more dielectric layers in the width direction on the first and second side surfaces S5 and S6 of the active layer, respectively. It may serve to prevent damage to the first and second internal electrodes 121 and 122 due to physical or chemical stress.

The first and second internal electrodes 121 and 122 are electrodes having different polarities and are formed inside the ceramic body 110 and are disposed to face each other with the dielectric layer 111 interposed therebetween. In this case, the first and second internal electrodes 121 and 122 may be electrically insulated from each other by the dielectric layer 111 disposed therebetween.

The first and second internal electrodes 121 and 122 include a capacitor part overlapping with an adjacent internal electrode and contributing to formation of a capacitor, and a lead part extending from the capacitor part to extend out of the ceramic body 110. .

In this case, the lead portion is not particularly limited, but may have a shorter length than the length of the ceramic body 110 of the internal electrode constituting the capacitor portion, for example.

In addition, the thicknesses of the first and second internal electrodes 121 and 122 may be determined according to a use. For example, the thickness of the first and second internal electrodes 121 and 122 may be determined to be within a range of 0.2 to 1.0 μm in consideration of the size of the ceramic body 110. The invention is not limited thereto.

In addition, the material for forming the first and second internal electrodes 121 and 122 is not particularly limited. For example, precious metal materials such as palladium (Pd) and palladium-silver (Pd-Ag) alloys, and nickel (Ni) And a conductive paste made of one or more materials of copper (Cu).

The conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

In the present embodiment, the first internal electrode 121 is exposed to the first main surface S1 of the ceramic body 110 at a position adjacent to the first end surface S1 of the ceramic body 110. ) And a second lead portion 121b exposed to the second main surface S2 of the ceramic body 110, and spaced apart from the first and second end surfaces S3 and S4 of the ceramic body 110 by a predetermined distance. do.

At this time, the first internal electrode 121 is further similar to the first and second lead-out portions 121a and 121b at a position adjacent to the second end surface S2 of the ceramic body 110, and further additional first and second lead-outs are formed. The portions 121a 'and 121b' may be further formed.

The second internal electrode 122 is exposed to the first main surface S1 of the ceramic body 110 but is formed to be spaced apart from the left and right first lead portions 121a and 121a 'by a predetermined distance and the ceramics. Exposed to the second main surface (S2) of the main body 110, and has a fourth lead portion 122b formed to be spaced apart from the left and right second lead portion (121b, 121b ') a predetermined distance, the first of the ceramic body 110 And spaced apart from the second end surfaces S1 and S2 by a predetermined distance.

In general multilayer ceramic electronic components, external electrodes may be disposed in cross sections facing each other in the length direction of the ceramic body.

In this case, since the current path is long when an alternating current is applied to the external electrode, the current loop may be formed larger, and the inductance may be increased by increasing the size of the induced magnetic field.

In order to solve the above problems, according to one embodiment of the present invention, first to second main surfaces S1 and S2 facing each other in the thickness direction of the ceramic body 110 in order to reduce the path of the electric current. Sixth external electrodes 131 to 136 may be disposed.

In this case, the thickness of the first to sixth external electrodes may be 10 to 40 μm. In this case, the ESL of the multilayer ceramic capacitor 100 has a value of 50 pH or less.

In this case, since the length between the first to sixth external electrodes 131 to 136 is small, the current path is shortened, thereby reducing the current loop and thus reducing the inductance.

In addition, the first to sixth external electrodes 131 to 136 are electrically connected to corresponding lead portions of the first and second internal electrodes 121 and 122, respectively, to form a capacitance, and the ceramic body 110 if necessary. It may be formed to extend to a part of the first and second side surfaces (S5, S6) of.

More specifically, the first to fourth external electrodes 131 to 134 may be connected to the first internal electrode 121, and the fifth and sixth external electrodes 135 and 136 may be connected to the second internal electrode 122. Can be connected.

The first to sixth external electrodes 131 to 136 have a triple layer structure, and include first to sixth conductive layers 131a to 136a connected to and in contact with lead portions of the corresponding internal electrodes. And nickel (Ni) plating layers 131b-136b formed to cover the sixth to sixth conductive layers 131a-136a, and tin (Sn) plating layers formed to cover the first to sixth nickel plating layers 131b-136b. .

The first to sixth conductive layers 131a to 136a may be formed of a conductive material having the same material as the first and second internal electrodes 121 and 122, but are not limited thereto. For example, copper (Cu), It may be formed of a metal powder such as silver (Ag) and nickel (Ni), and may be formed by applying a conductive paste prepared by adding a glass frit to the metal powder and then baking the same.

Hereinafter, the relationship between the dimensions, reliability, and ESL of the components included in the multilayer ceramic capacitor according to the present embodiment will be described.

Referring to FIG. 3, the width of the active layer of the ceramic body 110 may be AT, the first lead portions 121a and 121a ', or the second lead portions 121b and 121b' and the third or fourth lead portions 122a, When the interval of 122b) is defined as LG, the ratio LG / AT? In this case, the ESL of the multilayer ceramic capacitor 100 has a value of 50 pH or less.

In addition, it is preferable that the distance LG between the first lead portions 121a and 121a 'or the second lead portions 121b and 121b' and the third or fourth lead portions 122a and 122b exceeds 100 µm.

In this case, when the gap LG between the first lead portions 121a and 121a 'or the second lead portions 121b and 121b' and the third or fourth lead portions 122a and 122b is 100 μm or less, a mounting failure may appear. .

Referring to FIG. 4, the thicknesses of the first to sixth conductive layers 131a-136a are CT, the thicknesses of the first to sixth nickel plating layers 131b-136b are NT, and the first to sixth tin plating layers 131c-136c. ), The sum of the thicknesses of ST, the nickel plating layer and the tin plating layer is defined as PT.

Here, the thickness CT of the first to sixth conductive layers 131a to 136a may be 5 to 25 μm.

In addition, the thickness NT of the first to sixth nickel plating layers 131b to 136b may be 2 μm or more.

In addition, the thickness ST of the first to sixth tin plating layers 131c to 136c may be 3 μm or more.

In addition, the sum PT of the thicknesses of the nickel plating layer and the tin plating layer may be 15 μm or less.

By setting the thickness of the first to sixth external electrodes as described above, it is also possible to prevent a decrease in reliability due to plating liquid penetration. Details of this will be described in the experimental example below.

Experimental Example

The multilayer ceramic capacitor according to the embodiment and the comparative example of the present invention was produced as follows.

A slurry containing a powder such as barium titanate (BaTiO 3 ) is coated on a carrier film and dried to prepare a plurality of ceramic green sheets having a thickness of 1.8 탆.

Next, a first internal electrode having first and second lead portions exposed to first and second main surfaces of the ceramic green sheet by applying a conductive paste for nickel internal electrodes on the ceramic green sheet using a screen. A second internal electrode having a third and fourth lead portions spaced apart from the first and second lead portions is exposed to the first and second main surfaces of the ceramic green sheet.

Next, the ceramic green sheet is laminated in about 200 layers, and the ceramic green sheet, in which the first and second internal electrodes are not formed, is further laminated on both sides to prepare a laminate, and the laminate is manufactured at 85 ° C. at 1000 ° C. Isostatic pressing was carried out under kgf / cm 2 pressure.

Next, the pressed ceramic laminate was cut in the form of individual chips, and the cut chips were kept at about 230 ° C. for 60 hours in an air atmosphere to carry out binder removal.

Next, the ceramic body was prepared by baking in a reducing atmosphere under an oxygen partial pressure of 10 −11 to 10 −10 atm lower than the Ni / NiO equilibrium oxygen partial pressure so as not to oxidize the internal electrode at about 1200 ° C.

The chip size of the laminated chip capacitor after firing was about 1.0 mm × 0.5 mm (L × W, 1005 size) in length × width (L × W). Here, the production tolerance was set within the range of ± 0.1 mm in length × width (L × W).

Next, the multilayer ceramic capacitor is completed by forming the first to sixth external electrodes on the first and second main surfaces of the ceramic body to correspond to the lead portions of the first and second internal electrodes, respectively, to generate a high temperature load. It was shown in Tables 1 to 6 by performing the test, whether or not, reliable bonding, lead or poor, and equivalent series inductance (ESL) measurement test.

Each test was performed on 100 sample samples. At this time, the interval LG of the first or second lead-out portion and the third or fourth lead-out portion was set to 400 μm.

Here, the case where the defective rate is less than 0.01% is very good ◎, the case where the defective rate is less than 0.01 to 1% is good ○, the case where the defective rate is less than 1 to 50% is determined as bad △, the case where the defective rate is 50% or more is determined as very poor x. , The equivalent series inductance (ESL) value was determined to be good when the pH is 50 pH or less.

Conductive layer
thickness
(CT, um)
Ni plating layer
thickness
(NT, um)
Sn plating layer
thickness
(ST, um)
PT
(NT + ST)
TS
(CT + NT + ST)
High temperature load
(105 degrees 2Vr)
responsibility soldering
Bad
ESL
(pH)
3 One 2 3 6 X X X 24 3 4 7 X X 25 5 6 9 X X 27 9 10 13 X X 28 3 2 2 4 7 X X 25 3 5 8 X 25 5 7 10 X 26 9 11 14 X 28 3 3 2 5 8 X X 26 3 6 9 X 27 5 8 11 X 27 9 12 15 X 29 3 5 2 7 10 X X 27 3 8 11 X 27 5 10 13 X 28 9 14 17 X 30 3 9 2 11 14 X X 28 3 12 15 X 29 5 14 17 X 30 9 18 21 X 31

Referring to Table 1, when the thickness of the conductive layer of the external electrode is 3 ㎛ appeared low ESL in all samples, it can be seen that the high temperature load failure appears in all samples regardless of the thickness of the nickel plated layer and tin plated layer. have.

Conductive layer
thickness
(CT, um)
Ni plating layer
thickness
(NT, um)
Sn plating layer
thickness
(ST, um)
PT
(NT + ST)
TS
(CT + NT + ST)
High temperature load
(105 degrees 2Vr)
responsibility Poor soldering ESL
(pH)
5 One 2 3 8 X X 25 3 4 9 X 27 5 6 11 X 28 9 10 15 X 29 5 2 2 4 9 X 27 3 5 10 27 5 7 12 28 9 11 16 30 5 3 2 5 10 X 27 3 6 11 29 5 8 13 28 9 12 17 31 5 5 2 7 12 X 29 3 8 13 29 5 10 15 30 9 14 19 32 5 9 2 11 16 X 30 3 12 17 31 5 14 19 32 9 18 23 33

Referring to Table 2, when the thickness of the conductive layer of the external electrode is 5 ㎛ low ESL in all the samples, it can be seen that the high temperature load failure is also good.

However, all samples having a thickness of 1 μm of the nickel plated layer showed poor reliability, and even when the thickness of the nickel plated layer was 2 μm or more, it could be seen that soldering defects appeared when the thickness of the tin plated layer was 2 μm.

Conductive layer
thickness
(CT, um)
Ni plating layer
thickness
(NT, um)
Sn plating layer
thickness
(ST, um)
PT
(NT + ST)
TS
(CT + NT + ST)
High temperature load
(105 degrees 2Vr)
responsibility Poor soldering ESL
(pH)
7 One 2 3 10 X X 26 3 4 11 X 29 5 6 13 X 29 9 10 17 X 31 7 2 2 4 11 X 29 3 5 12 29 5 7 14 30 9 11 18 32 7 3 2 5 12 X 28 3 6 13 31 5 8 15 30 9 12 19 33 7 5 2 7 14 X 31 3 8 15 30 5 10 17 32 9 14 21 34 7 9 2 11 18 X 32 3 12 19 32 5 14 21 33 9 18 25 35

Referring to Table 3, when the thickness of the conductive layer of the external electrode is 7 ㎛ it can be seen that the ESL is low in all the samples, the high temperature load failure is also very good.

However, all samples having a thickness of 1 μm of the nickel plated layer showed poor reliability, and even when the thickness of the nickel plated layer was 2 μm or more, it could be seen that soldering defects appeared when the thickness of the tin plated layer was 2 μm.

Conductive layer
thickness
(CT, um)
Ni plating layer
thickness
(NT, um)
Sn plating layer
thickness
(ST, um)
PT
(NT + ST)
TS
(CT + NT + ST)
High temperature load
(105 degrees 2Vr)
responsibility soldering
Bad
ESL
(pH)
12 One 2 3 15 X X 30 3 4 16 X 34 5 6 18 X 34 9 10 22 X 35 12 2 2 4 16 X 34 3 5 17 34 5 7 19 35 9 11 23 37 12 3 2 5 17 X 33 3 6 18 36 5 8 20 34 9 12 24 38 12 5 2 7 19 X 35 3 8 20 35 5 10 22 37 9 14 26 38 12 9 2 11 23 X 37 3 12 24 37 5 14 26 38 9 18 30 40

Referring to Table 4, it can be seen that when the thickness of the conductive layer of the external electrode is 12 μm, the ESL was low in all samples, and the high temperature load failure was also very good.

In particular, when the thickness of the nickel plating layer is 3 µm or more, the reliability was also very good.

However, all samples having a thickness of 1 μm of the nickel plated layer showed poor reliability, and even when the thickness of the nickel plated layer was 2 μm or more, it could be seen that soldering defects appeared when the thickness of the tin plated layer was 2 μm.

Conductive layer
thickness
(CT, um)
Ni plating layer
thickness
(NT, um)
Sn plating layer
thickness
(ST, um)
PT
(NT + ST)
TS
(CT + NT + ST)
High temperature load
(105 degrees 2Vr)
responsibility soldering
Bad
ESL
(pH)
25 One 2 3 28 X X 43 3 4 29 X 46 5 6 31 X 45 9 10 35 X 48 25 2 2 4 29 X 45 3 5 30 46 5 7 32 47 9 11 36 48 25 3 2 5 30 X 44 3 6 31 47 5 8 33 46 9 12 37 49 25 5 2 7 32 X 47 3 8 33 48 5 10 35 48 9 14 39 50 25 9 2 11 36 X 49 3 12 37 50 5 14 39 50 9 18 43 52

Referring to Table 5, when the thickness of the conductive layer of the external electrode is 25 ㎛ appeared ESL 40 to about 50, it can be seen that the high temperature load failure is very good.

In particular, when the thickness of the nickel plating layer is 3 µm or more, the reliability was also very good.

However, all samples having a thickness of 1 μm of the nickel plated layer showed poor reliability, and even when the thickness of the nickel plated layer was 2 μm or more, soldering defects appeared when the thickness of the tin plated layer was 2 μm.

In addition, when the thickness of the nickel plating layer is 9 μm, and the thickness of the tin plating layer is 9 μm, it can be seen that the ESL exceeds 50 at 52 pH while the thickness of the entire external electrode exceeds 40 μm.

Conductive layer
thickness
(CT, um)
Ni plating layer
thickness
(NT, um)
Sn plating layer
thickness
(ST, um)
PT
(NT + ST)
TS
(CT + NT + ST)
High temperature load
(105 degrees 2Vr)
responsibility soldering
Bad
ESL
(pH)
34 One 2 3 37 X X 48 3 4 38 X 49 5 6 40 X 50 9 10 44 X 56 34 2 2 4 38 X 49 3 5 39 50 5 7 41 51 9 11 45 57 34 3 2 5 39 X 49 3 6 40 50 5 8 42 52 9 12 46 57 34 5 2 7 41 X 51 3 8 42 52 5 10 44 53 9 14 48 59 34 9 2 11 45 X 57 3 12 46 58 5 14 48 59 9 18 52 61

Referring to Table 6, when the thickness of the conductive layer of the external electrode is 34 ㎛ appeared ESL exceeds the maximum 60 pH in the late 40, it can be seen that the high temperature load failure is very good.

In particular, when the thickness of the nickel plating layer is 3 µm or more, the reliability was also very good.

However, all samples having a thickness of 1 μm of the nickel plated layer showed poor reliability, and even when the thickness of the nickel plated layer was 2 μm or more, soldering defects appeared when the thickness of the tin plated layer was 2 μm.

On the other hand, it can be seen that the ESL exceeds 50 pH in all samples in which the thickness of the entire external electrode exceeds 40 μm.

Referring to Tables 1 to 6, when the overall thickness of the external electrode is lowered, the length of the current path can be reduced to reduce the ESL, but it can be seen that the lowering of reliability due to the penetration of the plating solution may occur.

In addition, it can be seen that when the thickness of the nickel plating layer is lowered, the tin plating layer and the conductive layer may meet, resulting in a problem of poor reliability caused by a lower melting temperature of the conductive layer during soldering.

In addition, it can be seen that when the thickness of the tin plating layer is lowered, there is a risk of solder failure.

Therefore, the thickness CT of the first to sixth conductive layers 131a to 136a may be 5 to 25 μm, and the preferred thickness NT of the first to sixth nickel plating layers 131b to 136b may be 2 μm or more. The preferred thickness ST of the first to sixth tin plating layers 131c-136c may be 3 μm or more, and the sum PT of the thicknesses of the nickel plating layer and the tin plating layer may be 15 μm or less.

Table 7 below shows a high temperature load, reliability bonding, poor soldering, and mounting for the width AT of the active layer of the multilayer ceramic capacitor and the interval LG of the first or second lead portion and the third or fourth lead portion. Defective and equivalent series inductance (ESL) measurement tests are shown.

Active layer
width
(AT)
Internal electrode
Withdrawal
Interval (LG)
LG / AT High temperature load
(105 degrees 2Vr)
responsibility soldering
Bad
Chief
Bad
ESL
(pH)
500 100 0.20 X 40 150 0.30 43 200 0.40 46 300 0.60 51 500 1.00 56 800 100 0.13 X 38 150 0.19 41 200 0.25 43 300 0.38 48 500 0.63 52 1000 100 0.10 X 35 150 0.15 38 200 0.20 41 300 0.30 44 500 0.50 50 1200 100 0.08 X 33 150 0.13 35 200 0.17 38 300 0.25 46 500 0.42 48

Referring to Table 7, when the width of the active layer is defined as AT, the interval between the first or second lead-out portion and the third or fourth lead-out portion as LG, when LG / AT exceeds 0.5, ESL It was found to exceed 50 pH.

In addition, when the gap LG of the first or second lead-out portion of the first internal electrode and the third or fourth lead-out portion of the second internal electrode is 100 μm or less, it can be seen that a mounting failure appears.

As described above, as the LG is smaller, the length of the current path may be reduced to lower the ESL. However, as the gap between the external electrodes is reduced, mounting stability may be lowered.

In this embodiment, when the width of the active layer is defined as AT, the interval between the first or second lead-out portion and the third or fourth lead-out portion is defined as LG, the LG / AT is maintained at 0.5 or less so that the mounting stability is maintained. It can be seen that both and below the ESL 50 pH can be achieved.

The mounting substrate of the multilayer ceramic capacitor

5 is a perspective view illustrating a multilayer ceramic capacitor of FIG. 1 mounted on a printed circuit board, and FIG. 6 is a cross-sectional view illustrating a multilayer ceramic capacitor of FIG. 4 mounted on a printed circuit board.

5 and 6, the mounting board 200 of the multilayer ceramic capacitor 100 according to the present embodiment includes a printed circuit board 210 mounted with the multilayer ceramic capacitor 100 horizontally, and a printed circuit board ( The first to third electrode pads 221, 222, and 223 formed to be spaced apart from each other on the upper surface of the 210 are included.

In this case, the multilayer ceramic capacitor 100 may be soldered in a state in which the third, fourth, and sixth external electrodes 133, 134, and 136 are positioned on the first to third electrode pads 221, 222, and 223, respectively. 230 may be electrically connected to the printed circuit board 210.

In FIG. 6, reference numeral 224 denotes a ground terminal, and reference numeral 225 denotes a power supply terminal.

The present invention is not limited to the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims.

It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

100; A multilayer ceramic capacitor 110; Ceramic body
111; Dielectric layers 112, 113; Upper and lower cover layers
121, 122; First and second internal electrodes 121a and 121a '; First withdrawal unit
121b, 121b '; Second lead portion 122a; 3rd withdrawal part
122b; 4th withdrawal part
131, 132, 133, 134, 135, 136; First to sixth external electrodes
200; A mounting substrate 210; Printed circuit board
221, 222, 223; First to third electrode pads
230; Solder

Claims (12)

  1. A plurality of dielectric layers stacked in the width direction, the ceramic body having first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second cross sections facing each other;
    Is formed in the ceramic body, and has a first lead portion exposed to the first main surface of the ceramic body and a second lead portion exposed to the second main surface of the ceramic body spaced apart from the first and second cross-sections by a predetermined distance. And exposed to the first internal electrode, the first main surface of the ceramic body, the third lead portion formed to be spaced apart from the first lead portion, and the second main surface of the ceramic body. An active layer having a fourth lead portion formed to be spaced apart from each other by a predetermined distance, and including a second internal electrode spaced apart from the first and second end surfaces by a predetermined distance;
    Upper and lower cover layers formed on first and second side surfaces of the active layer; And
    First to fourth external electrodes formed on first and second main surfaces of the ceramic body and connected to the first internal electrode and fifth and sixth external electrodes connected to the second internal electrode; / RTI &gt;
    LG / AT ≦ 0.5 when the width of the active layer is defined as AT, the interval between the first or second lead-out portion and the third or fourth lead-out portion is LG.
  2. The method of claim 1,
    The first lead-out portion is a multilayer ceramic capacitor, characterized in that composed of two lead-out portions formed to be spaced apart from the third lead-out portion, respectively.
  3. The method of claim 1,
    The second lead-out portion is a multilayer ceramic capacitor, characterized in that composed of two lead-out portions formed to be spaced apart from the fourth lead-out portion, respectively.
  4. The method of claim 1,
    And the gap LG of the first or second lead-out portion and the third or fourth lead-out portion exceeds 100 μm.
  5. A plurality of dielectric layers stacked in the width direction, the ceramic body having first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second cross sections facing each other;
    Is formed in the ceramic body, and has a first lead portion exposed to the first main surface of the ceramic body and a second lead portion exposed to the second main surface of the ceramic body spaced apart from the first and second cross-sections by a predetermined distance. And exposed to the first internal electrode, the first main surface of the ceramic body, the third lead portion formed to be spaced apart from the first lead portion, and the second main surface of the ceramic body. An active layer having a fourth lead portion formed to be spaced apart from each other by a predetermined distance, and including a second internal electrode spaced apart from the first and second end surfaces by a predetermined distance;
    Upper and lower cover layers formed on first and second side surfaces of the active layer; And
    First to fourth external electrodes formed on first and second main surfaces of the ceramic body and connected to the first internal electrode and fifth and sixth external electrodes connected to the second internal electrode; / RTI &gt;
    The thickness of the first to sixth external electrodes is 10 to 40 ㎛ multilayer ceramic capacitor.
  6. 6. The method of claim 5,
    The first lead-out portion is a multilayer ceramic capacitor, characterized in that composed of two lead-out portions formed to be spaced apart from the third lead-out portion, respectively.
  7. 6. The method of claim 5,
    The second lead-out portion is a multilayer ceramic capacitor, characterized in that composed of two lead-out portions formed to be spaced apart from the fourth lead-out portion, respectively.
  8. 6. The method of claim 5,
    The first to sixth external electrodes may include a conductive layer connected to each corresponding lead portion, a nickel (Ni) plating layer formed to cover the conductive layer, and a tin (Sn) plating layer formed to cover the nickel plating layer. Include,
    The thickness of the conductive layer is a multilayer ceramic capacitor, characterized in that 5 to 25 ㎛.
  9. 6. The method of claim 5,
    The first to sixth external electrodes may include a conductive layer connected to each corresponding lead portion, a nickel (Ni) plating layer formed to cover the conductive layer, and a tin (Sn) plating layer formed to cover the nickel plating layer. Include,
    The thickness of the nickel plating layer is a multilayer ceramic capacitor, characterized in that 2 ㎛ or more.
  10. 6. The method of claim 5,
    The first to sixth external electrodes may include a conductive layer connected to each corresponding lead portion, a nickel (Ni) plating layer formed to cover the conductive layer, and a tin (Sn) plating layer formed to cover the nickel plating layer. Include,
    The thickness of the tin plating layer is a multilayer ceramic capacitor, characterized in that 3 ㎛ or more.
  11. 6. The method of claim 5,
    The first to sixth external electrodes may include a conductive layer connected to each corresponding lead portion, a nickel (Ni) plating layer formed to cover the conductive layer, and a tin (Sn) plating layer formed to cover the nickel plating layer. Include,
    The sum of the thicknesses of the nickel plating layer and the tin plating layer is 15 µm or less.
  12. A substrate having first and second electrode pads thereon; And
    A multilayer ceramic capacitor according to any one of claims 1 to 11 provided on the substrate; Mounting substrate of the multilayer ceramic capacitor comprising a.
KR1020130117571A 2013-10-01 2013-10-01 Multi-layered ceramic capacitor and board for mounting the same KR20140038912A (en)

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KR20140126164A KR101514607B1 (en) 2013-10-01 2014-09-22 Multi-layered ceramic capacitor and board for mounting the same
TW103133901A TWI552181B (en) 2013-10-01 2014-09-30 Multilayer ceramic capacitor and board having the same
US14/504,000 US9460855B2 (en) 2013-10-01 2014-10-01 Multilayer ceramic capacitor and board having the same
CN201410525000.3A CN104517730B (en) 2013-10-01 2014-10-08 Multilayer ceramic capacitor and the plate with the multilayer ceramic capacitor
CN201810561891.6A CN108682556B (en) 2013-10-01 2014-10-08 Multilayer ceramic capacitor and board having the same
KR20150010240A KR20150039132A (en) 2013-10-01 2015-01-21 Multi-layered ceramic capacitor and board for mounting the same
US14/833,018 US20150364260A1 (en) 2013-10-01 2015-08-21 Multilayer ceramic capacitor and board having the same
US15/865,803 US10269499B2 (en) 2013-10-01 2018-01-09 Multilayer ceramic capacitor and board having the same
US15/865,773 US10340086B2 (en) 2013-10-01 2018-01-09 Multilayer ceramic capacitor and board having the same

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Publication number Priority date Publication date Assignee Title
US9087643B1 (en) 2014-08-13 2015-07-21 Murita Manufacturing Co., Ltd. Multilayer capacitor and installation structure of multilayer capacitor
US9214282B1 (en) 2014-12-08 2015-12-15 Murata Manufacturing Co., Ltd. Three-terminal capacitor
US9330843B2 (en) 2014-08-13 2016-05-03 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component including a pair of side outer electrodes and a center electrode
CN105895369A (en) * 2015-02-13 2016-08-24 Tdk株式会社 Multilayer Capacitor
US9627143B2 (en) 2014-08-13 2017-04-18 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component including a pair of side outer electrodes and a center electrode
US9633787B2 (en) 2014-08-13 2017-04-25 Murata Manufacturing Co., Ltd. Multilayer capacitor and installation structure of multilayer capacitor
US9711285B2 (en) 2014-11-13 2017-07-18 Murata Manufacturing Co., Ltd. Capacitor with a center outer electrode disposed between first and second outer electrodes
US9715967B2 (en) 2014-11-13 2017-07-25 Murata Manufacturing Co., Ltd. Capacitor with center outer electrode disposed between first and second outer electrodes
US9842700B2 (en) 2014-12-04 2017-12-12 Murata Manufacturing Co., Ltd. Three-terminal capacitor
US9947472B2 (en) 2014-08-13 2018-04-17 Murata Manufacturing Co., Ltd. Multilayer capacitor and installation structure of multilayer capacitor
US10170247B2 (en) 2014-08-13 2019-01-01 Murata Manufacturing Co., Ltd. Multilayer capacitor and installation structure of multilayer capacitor

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JP4213744B2 (en) * 2005-12-22 2009-01-21 Tdk株式会社 Multilayer capacitor and its mounting structure
US7920370B2 (en) * 2007-02-05 2011-04-05 Samsung Electro-Mechanics Co., Ltd. Multilayer chip capacitor
JP2012028502A (en) * 2010-07-22 2012-02-09 Ngk Spark Plug Co Ltd Multilayer capacitor and wiring board

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9087643B1 (en) 2014-08-13 2015-07-21 Murita Manufacturing Co., Ltd. Multilayer capacitor and installation structure of multilayer capacitor
US9330843B2 (en) 2014-08-13 2016-05-03 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component including a pair of side outer electrodes and a center electrode
US9947472B2 (en) 2014-08-13 2018-04-17 Murata Manufacturing Co., Ltd. Multilayer capacitor and installation structure of multilayer capacitor
US9627143B2 (en) 2014-08-13 2017-04-18 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component including a pair of side outer electrodes and a center electrode
US9633787B2 (en) 2014-08-13 2017-04-25 Murata Manufacturing Co., Ltd. Multilayer capacitor and installation structure of multilayer capacitor
US10170247B2 (en) 2014-08-13 2019-01-01 Murata Manufacturing Co., Ltd. Multilayer capacitor and installation structure of multilayer capacitor
US9715967B2 (en) 2014-11-13 2017-07-25 Murata Manufacturing Co., Ltd. Capacitor with center outer electrode disposed between first and second outer electrodes
US9711285B2 (en) 2014-11-13 2017-07-18 Murata Manufacturing Co., Ltd. Capacitor with a center outer electrode disposed between first and second outer electrodes
US9842700B2 (en) 2014-12-04 2017-12-12 Murata Manufacturing Co., Ltd. Three-terminal capacitor
US9214282B1 (en) 2014-12-08 2015-12-15 Murata Manufacturing Co., Ltd. Three-terminal capacitor
CN105895369A (en) * 2015-02-13 2016-08-24 Tdk株式会社 Multilayer Capacitor
US10026554B2 (en) 2015-02-13 2018-07-17 Tdk Corporation Multilayer capacitor with (1) an element body having internal electrodes and (2) opposing terminal electrodes

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