KR101514610B1 - Multi-layered ceramic capacitor and board for mounting the same - Google Patents

Multi-layered ceramic capacitor and board for mounting the same Download PDF

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Publication number
KR101514610B1
KR101514610B1 KR1020140133068A KR20140133068A KR101514610B1 KR 101514610 B1 KR101514610 B1 KR 101514610B1 KR 1020140133068 A KR1020140133068 A KR 1020140133068A KR 20140133068 A KR20140133068 A KR 20140133068A KR 101514610 B1 KR101514610 B1 KR 101514610B1
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South Korea
Prior art keywords
ceramic
lead
external electrodes
mounting
lead portions
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KR1020140133068A
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Korean (ko)
Inventor
안영규
임휘근
김현태
김진
이교광
이병화
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삼성전기주식회사
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Priority to KR1020130129120 priority
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Priority claimed from US14/527,662 external-priority patent/US9396879B2/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G2/00Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02Mountings
    • H01G2/06Mountings specially adapted for mounting on a printed-circuit support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/005Electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10636Leadless chip, e.g. chip capacitor or resistor

Abstract

Provided in the present invention are a multi-layered ceramic capacitor and a board for mounting the same in which three external electrodes are arranged on the mounting surface of a ceramic body, the gap between adjacent lead parts is 500.7 μm or less, and the margin not contacting with the lead parts corresponding to the first to third external electrodes in one side longitudinal direction is 20.2 μm or more.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multilayer ceramic capacitor,

The present invention relates to a multilayer ceramic capacitor and a mounting substrate thereof.

Background Art [0002] With the recent miniaturization and high capacity of electronic products, electronic components used in electronic products are also required to be smaller and have higher capacity.

In the case of the multilayer ceramic capacitor, if the equivalent series inductance (hereinafter referred to as " ESL ") is increased, the performance of the electronic product may deteriorate. As the applied electronic component is miniaturized and the capacity is increased, the ESL of the multilayer ceramic capacitor is increased The influence on the performance degradation becomes relatively large.

In particular, the use of decoupling capacitors has been increasing as the performance of ICs has increased, so there is a need for a so-called " MLCC " which is a vertically stacked three terminal MLCC capable of reducing the distance between external terminals, thereby reducing the current flow path and thereby reducing the inductance of the capacitor. LICC (Low Inductance Chip Capacitor) "

The multilayer ceramic capacitor has characteristics in which the reliability of the product and the mounting defect rate are greatly affected by the shape and size of the external electrode.

Korea Patent Publication No. 2009-0117686 Korean Patent No. 0920614

It is an object of the present invention to provide a multilayer ceramic capacitor and its mounting substrate which can improve reliability and bonding strength while maintaining low ESL characteristics in a vertical stacked three-terminal capacitor.

In one aspect of the present invention, three external electrodes are arranged on a mounting surface of a ceramic body so as to be spaced apart from each other, and a distance between adjacent lead portions is 500.7 탆 or less, and lead portions corresponding to the first to third external electrodes And a margin in a longitudinal direction of one side of the multilayer ceramic capacitor not contacted is 20.2 占 퐉 or more.

According to the embodiment of the present invention, it is possible to improve the reliability and the fixing strength while maintaining the low ESL characteristics by adjusting the gap of the adjacent lead portions and the margin in one longitudinal direction which are not in contact with the corresponding lead portions respectively corresponding to the external electrodes It is effective.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention in an inverted manner. FIG.
2 is a perspective view showing the ceramic body of the multilayer ceramic capacitor of FIG. 1 in an inverted state.
3 is an exploded perspective view of the multilayer ceramic capacitor of FIG. 1, in which external electrodes are omitted.
4 is a cross-sectional view showing the multilayer ceramic capacitor of FIG.
5 is a perspective view showing a structure in which the multilayer ceramic capacitor of FIG. 1 has another type of external electrode.
6 is a perspective view schematically showing a multilayer ceramic capacitor according to still another embodiment of the present invention.
FIG. 7 is an exploded perspective view of the multilayer ceramic capacitor of FIG. 6 with external electrodes omitted.
8 is a perspective view schematically showing a multilayer ceramic capacitor according to still another embodiment of the present invention.
9 is a perspective view showing a ceramic body of the multilayer ceramic capacitor of FIG.
10 is an exploded perspective view of the multilayer ceramic capacitor of FIG. 8, in which external electrodes are omitted.
11 is a cross-sectional view showing the multilayer ceramic capacitor of Fig.
12 is a perspective view showing a structure in which the multilayer ceramic capacitor of FIG. 8 has another type of external electrode.
13 is a perspective view showing a state in which the multilayer ceramic capacitor of FIG. 8 is mounted on a substrate.
14 is a cross-sectional view showing a state in which the multilayer ceramic capacitor of FIG. 8 is mounted on a substrate.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below.

Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

The shape and size of elements in the drawings may be exaggerated for clarity.

In the drawings, like reference numerals are used to designate like elements that are functionally equivalent to the same reference numerals in the drawings.

In order to clearly illustrate the embodiments of the present invention, when the directions of the hexahedron are defined, L, W, and T shown in the drawings indicate the longitudinal direction, the width direction, and the thickness direction, respectively. Here, the width direction can be used in the same concept as the lamination direction in which the dielectric layers are laminated.

Multilayer Ceramic Capacitors

FIG. 1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention, FIG. 2 is a perspective view showing a ceramic body of the multilayer ceramic capacitor shown in FIG. 1, FIG. 4 is a cross-sectional view showing the multilayer ceramic capacitor of FIG. 1. FIG.

1 to 4, a multilayer ceramic capacitor 100 according to the present embodiment includes a ceramic body 110 in which a plurality of dielectric layers 111 are stacked in a width direction, a plurality of first and second internal electrodes 120 and 130, and first to third external electrodes 141-143.

The multilayer ceramic capacitor 100 of the present embodiment can be regarded as a three-terminal capacitor having three external terminals in total.

The ceramic body 110 has a first main surface S1 and a second main surface S2 facing each other in the thickness direction and a first main surface S1 and a second main surface S2, Three side surfaces S5 and a fourth side surface S6 and a first side surface S3 and a second side surface S4 facing each other in the longitudinal direction.

Hereinafter, the mounting surface of the multilayer ceramic capacitor 100 will be described as the first main surface S1 of the ceramic body 110 in the present embodiment.

The ceramic body 110 is formed by laminating a plurality of dielectric layers 111 in the width direction and then firing, and the shape is not particularly limited, but may be a hexahedron shape as shown in the figure.

However, the shape and dimensions of the ceramic body 110 and the number of laminated layers of the dielectric layer 111 are not limited to those shown in this embodiment.

The plurality of dielectric layers 111 forming the ceramic body 110 are in a sintered state and the boundaries between the adjacent dielectric layers 111 are such that it is difficult to confirm without using a scanning electron microscope (SEM) Can be integrated.

The ceramic body 110 includes an active layer having a plurality of internal electrodes as a portion contributing to capacity formation of a capacitor and cover layers 112 and 113 arranged on both sides in the width direction of the active layer as a margin portion .

The active layer may be formed by alternately stacking a plurality of first and second inner electrodes 120 and 130 in the width direction with the dielectric layer 111 interposed therebetween.

At this time, the thickness of the dielectric layer 111 can be arbitrarily changed in accordance with the capacity design of the multilayer ceramic capacitor 100, and the thickness of one layer may preferably be 0.01 to 1.00 m after firing. It is not.

The dielectric layer 111 may include a ceramic powder having a high dielectric constant, for example, a barium titanate (BaTiO 3 ) -based or a strontium titanate (SrTiO 3 ) -based powder, and as long as a sufficient electrostatic capacity can be obtained, But is not limited thereto.

If necessary, a ceramic additive, an organic solvent, a plasticizer, a binder, a dispersant, and the like may be further added to the dielectric layer 111 together with the ceramic powder.

At this time, the average particle diameter of the ceramic powder used for forming the dielectric layer 111 is not particularly limited and may be adjusted for achieving the object of the present invention. For example, it may be adjusted to 400 nm or less, But is not limited thereto.

The cover layers 112 and 113 may have the same material and configuration as the dielectric layer 111 except that they do not include internal electrodes.

Further, the cover layers 112 and 113 can be formed by laminating a single dielectric layer or two or more dielectric layers on both sides in the width direction of the active layer. Basically, the first and second internal Thereby preventing the electrodes 120 and 130 from being damaged.

The first and second internal electrodes 120 and 130 are electrodes having different polarities and are formed inside the ceramic body 110 and disposed so as to face each other with the dielectric layer 111 therebetween.

At this time, the first and second internal electrodes 120 and 130 may be electrically insulated from each other by a dielectric layer 111 disposed in the middle.

The first and second internal electrodes 120 and 130 include a capacitor portion that overlaps the neighboring internal electrode and contributes to formation of a capacitor and a lead portion that extends a part of the capacitor portion and is exposed to the outside of the ceramic body 110 .

The lead portion is not particularly limited, but may have a shorter length than the length of the ceramic body 110 of the internal electrode constituting the capacitor.

The thickness of the first and second internal electrodes 120 and 130 may be determined depending on the application. For example, the thickness of the first and second internal electrodes 120 and 130 may be determined to fall within a range of 0.2 to 1.0 탆 considering the size of the ceramic body 110, The invention is not limited thereto.

The material for forming the first and second inner electrodes 120 and 130 is not particularly limited and may be selected from a noble metal material such as palladium (Pd), a palladium-silver (Pd-Ag) alloy, And copper (Cu), or the like.

The conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

The first internal electrodes 120 have first and second lead portions 121 and 122 spaced from each other in the longitudinal direction and exposed to the first main surface S1 of the ceramic body 110, 1 and the second side surfaces S3, S4.

The second internal electrode 130 is exposed to the first main surface S1 of the ceramic body 110 and has a third lead portion 121 formed between the first and second lead portions 121 and 122, 131 and is spaced apart from the first and second sides S3, S4 by a certain distance.

At this time, a larger value among the intervals (a1 + b1 + c1, a2 + b2 + c2) between the adjacent lead portions may be 500.7 탆 or less.

When the larger one of the intervals (a1 + b1 + c1, a2 + b2 + c2) between the adjacent lead portions exceeds 500.7 탆, it is difficult to satisfy the ESL 50 pH or less.

In general laminated ceramic electronic parts, external electrodes may be disposed on both end faces facing each other in the longitudinal direction of the ceramic body.

However, in this case, when AC is applied to the external electrode, since the current path is long, the current loop can be formed larger, and the size of the induced magnetic field becomes larger, and the inductance can be increased.

According to an embodiment of the present invention, first and second external electrodes 141 and 142 and first and second external electrodes 141 and 142 are formed on a first main surface S1 of the ceramic body 110. [ 141, and 142, respectively.

In this case, since the distance between the first and second outer electrodes 141 and 142 and the third outer electrode 143 is small, the current loop is reduced, thereby reducing the inductance.

The first and second external electrodes 141 and 142 are spaced from each other in the longitudinal direction on the first main surface S1 of the ceramic body 110 and are connected to the first and second lead portions 121 and 122, And the third external electrode 143 is connected to the first and second external electrodes 141 and 142 between the first and second external electrodes 141 and 142 on the first main surface S1 of the ceramic body 110, And is connected to and connected to the third lead portion 131. The third lead portion 131 is connected to the third lead portion 131,

The first to third external electrodes 141 to 143 are electrically connected to the corresponding lead portions of the first and second internal electrodes 120 and 130 for the formation of a capacitance, The side bands can be formed to extend to a part of the third and fourth side faces S5 and S6 in the width direction of the light emitting device.

At this time, the smallest value among the longitudinal margins (a1, a2, c1, c2) which are not in contact with the corresponding lead portions in the first to third external electrodes 141-143 may be 20.2 탆 or more.

When the smallest value among the lengthwise margins (a1, a2, c1, c2) of the first to third external electrodes 141-143 and the corresponding lead portions not in contact with each other is less than 20 占 퐉, The reliability of the moisture-proof load may deteriorate.

Further, the smaller of the intervals b1 and b2 of the adjacent external electrodes may be 126.9 占 퐉 or more.

If the spacing (b1, b2) of the adjacent external electrodes is less than 126.9 占 퐉, a short circuit may occur during mounting on the substrate.

The height d of the side band of each of the first to third external electrodes 141 to 143 is preferably 73.4 占 퐉 or more.

At this time, the height d of the side band of the first to third external electrodes 141 to 143 may be less than the chip overall height Tc.

When the height d of the side band of the first to third external electrodes 141 to 143 is 73.4 占 퐉 or more, the bonding strength is improved and defects do not occur, and the first to third external electrodes 141 to 143, If the height d of the side band of the first external electrode 141-143 is less than 73.4 占 퐉, the first to third external electrodes 141-143 may have poor bonding strength.

The first through third external electrodes 141-143 may be formed in a triple layer structure. The first through third conductive layers 141a- First to third nickel (Ni) plating layers 141b to 143b formed to cover the first to third conductive layers 141a to 143a, first to third nickel plating layers 141b to 143b, And first to third tin (Sn) plating layers 141c to 143c formed so as to cover the first to third tin (Sn) plating layers, respectively.

The first to third conductive layers 141a to 143a may be formed of a conductive material having the same material as that of the first and second internal electrodes 120 and 130. However, the present invention is not limited thereto. For example, copper (Cu) Silver (Ag), and nickel (Ni). The conductive paste may be formed by applying a conductive paste prepared by adding glass frit to the metal powder, followed by firing.

5 is a perspective view showing a structure in which the multilayer ceramic capacitor 100 'of FIG. 1 has different external electrodes.

Referring to FIG. 5, the first to third external electrodes 141 to 143 are electrically connected to the corresponding lead portions of the first and second internal electrodes 120 and 130, respectively, The first and second external electrodes 141 and 142 extend to a portion of the third and fourth side faces S5 and S6 in the width direction of the ceramic body 110 to form a first side band, 110 and a second side band extending respectively to portions of the first and second side surfaces S3, S4 in the longitudinal direction of the second side surface 110, respectively.

At this time, the height d of the first side band of each of the first to third external electrodes 141 to 143 is 40.0 탆 or more, and the height d of the second side band of the first and second external electrodes 141 and 142 The height (e) is preferably 30.3 占 퐉 or more.

At this time, the height d of the first side band of the first to third external electrodes 141 to 143 is equal to or smaller than the total height of the chip, and the height of the second side band of the first and second external electrodes 141 and 142 (e) may be less than or equal to the overall height of the chip. That is, the sum (d + e) of the height of the first side band and the height of the second side band may be less than or equal to twice the height of the entire chip.

The sum of the height d of the first side band of the first to third external electrodes 141 to 143 and the height e of the second side band of the second external electrodes 141 and 142 is less than 64.1 占 퐉 The first to third external electrodes 141 to 143 may have poor adhesion strength.

Experimental Example

The multilayer ceramic capacitor according to the embodiment and the comparative example of the present invention was produced as follows.

A slurry containing a powder such as barium titanate (BaTiO 3 ) is coated on a carrier film and dried to prepare a plurality of ceramic green sheets having a thickness of 1.8 탆.

Next, a first internal electrode having first and second lead portions exposed on a first main surface of the ceramic green sheet by applying a conductive paste for a nickel internal electrode on the ceramic green sheet using a screen, and first and second internal electrodes, A second internal electrode having a third lead portion spaced apart from the second lead portion and exposed to a first major surface of the ceramic green sheet is formed.

Next, the ceramic green sheets were laminated with about 200 layers, and ceramic green sheets without the first and second internal electrodes formed were further laminated on both sides in the width direction to prepare a laminate, and this laminate was formed into 85 Isostatic pressing under 1000 kgf / cm 2 pressure condition.

Next, the pressed ceramic laminate was cut into individual chips, and the cut chips were maintained at about 230 DEG C for 60 hours in an atmospheric environment to proceed the binder removal.

Next, the ceramic body was fired in a reducing atmosphere at an oxygen partial pressure of 10 -11 to 10 -10 atm lower than the Ni / NiO equilibrium oxygen partial pressure so that the internal electrodes were not oxidized at about 1,200 ° C.

The chip size of the multilayer chip capacitor after firing had a length x width (L x W) of about 1.6 mm x 0.8 mm (L x W, 1608 size). Here, the manufacturing tolerance was set within the range of 占 0.1 mm in length × width (L 占 W).

Next, the first to third external electrodes are formed on the first main surface of the ceramic body so as to correspond to the lead portions of the first and second internal electrodes, respectively, to complete the multilayer ceramic capacitor. , The short-circuit defect rate, the poor connection strength, and the equivalent series inductance (ESL) measurement test were carried out. Each test was performed on 100 sample samples.

Figure 112014094431493-pat00001

(A1 + b1 + c1, a2 + b2 + c2) is preferably 500.7 占 퐉 or less among the intervals of the adjacent lead portions, + c1, a2 + b2 + c2) exceeding 500.7 mu m, it can be confirmed that ESL exceeds 50 pH and it is difficult to realize low ESL.

In this case, the minimum value among the intervals (a1 + b1 + c1, a2 + b2 + c2) between the adjacent lead portions is smaller than the minimum value among the intervals b1 and b2 of the adjacent external electrodes, (A1 + c1, a2 + c2) in one longitudinal direction which is not in contact with the lead portion. Therefore, it is preferable that the smaller one of the intervals (a1 + b1 + c1, a2 + b2 + c2) between the adjacent lead portions is 167.3 mu m or more.

The minimum values min (a1, a2, c1, c2) of the longitudinal margins not in contact with the corresponding lead portions of the first to third external electrodes 141-143 are preferably 20.2 탆 or more, The samples 1 and 6 having the minimum values min (a1, a2, c1, c2) of less than 20 占 퐉 among the longitudinal margins not in contact with the corresponding lead portions in the first to third external electrodes 141 to 143, , 11 and 16, the reliability of the high-temperature load and the moisture-proof load deteriorates.

At this time, the maximum value of the largest one among the longitudinal margins (a1, a2, c1, c2) which are not in contact with the lead portions corresponding to the respective external electrodes is a large value max (a1 + b1 + c1, a2 + b2 + c2), which is obtained by subtracting the smallest value among the intervals (b1, b2) of adjacent external electrodes (b1, b2)

Therefore, it is preferable that the largest one of the longitudinal margins (a1, a2, c1, c2) which are not in contact with the corresponding lead portions in the external electrodes is 186.9 mu m or less.

In addition, in the case of the sample 5 having the largest of the intervals (b1, b2) of the adjacent external electrodes, the largest among the intervals (b1, b2) of the external electrodes adjacent to each other is 126.9 mu m or less, Can be confirmed.

At this time, the maximum value of the larger one of the intervals (b1, b2) of the adjacent external electrodes is larger than the largest one of the intervals (a1 + b1 + c1, a2 + b2 + c2) Is the same as subtracting the minimum value x 2 of the smallest one of the longitudinal margins (a1, a2, c1, c2) not in contact with the corresponding lead portion. Therefore, it is preferable that the maximum value of the interval (b1, b2) of the external electrodes adjacent to each other is 460.3 mu m or less.

Each of the first to third external electrodes 141 to 143 has a side band extending to a portion of the third and fourth side faces S5 and S6 in the width direction of the ceramic body 110, (d) are preferably 73.4 占 퐉 or more.

In the case of the sample 23 in which the height d of the side band of the first to third external electrodes 141 to 143 was less than 73.4 占 퐉, the bonding strength defect occurred.

On the other hand, in Samples 25 to 36, the first to third external electrodes 141 to 143 each have a first side band extending to a portion of the third and fourth side faces S5 and S6 in the width direction of the ceramic body 110 And the first and second external electrodes 141 and 142 have second side bands extending respectively to portions of the first and second side surfaces S3 and S4 in the longitudinal direction of the ceramic body 110. [

At this time, referring to the samples 26 to 36, the height d of the first side band of the first to third external electrodes 141-143 where the bonding strength defect of the external electrode does not occur, And the sum of the heights e of the second side bands of the electrodes 141 and 142 is 64.1 탆 or more.

In the case of the sample 25 in which the sum (d + e) of the first side band and the second side band was less than 64.1 占 퐉, a poor bonding strength occurred.

Variation example

FIG. 6 is a perspective view schematically showing a multilayer ceramic capacitor according to another embodiment of the present invention, and FIG. 7 is an exploded perspective view showing the multilayer ceramic capacitor of FIG. 6 with external electrodes omitted.

Here, since the structure of the ceramic body 110 is the same as that of the first embodiment described above, a detailed description thereof will be omitted in order to avoid redundancy, and the first and second internal electrodes 120 and 130 And the insulating layer 150 will be described in detail.

6 and 7, the multilayer ceramic capacitor 100 "of the present embodiment can be provided with the insulating layer 150 on the second main surface S2 facing the mounting surface of the ceramic body 110. [

The first internal electrode 120 is exposed through the second main surface S2 of the ceramic body 110 and contacts the insulating layer 150 formed on the second main surface S2 of the ceramic body 110. [ 5 lead portions 123 and 124, respectively.

The second internal electrode 130 is disposed between the third and fourth lead portions 123 and 124 and is exposed through the second main surface S2 of the ceramic body 110 to contact the insulating layer 150, And may have a lead portion 132.

8 is a perspective view schematically showing a multilayer ceramic capacitor according to another embodiment of the present invention, FIG. 9 is a perspective view showing a ceramic body of the multilayer ceramic capacitor of FIG. 8, FIG. 10 is a perspective view of the multilayer ceramic capacitor of FIG. FIG. 11 is a cross-sectional view showing the multilayer ceramic capacitor of FIG. 8. FIG.

Here, since the structure of the ceramic body 110 is the same as that of the embodiment described above, a detailed description thereof will be omitted in order to avoid duplication, and the fourth to sixth external electrodes 144-146 And the first and second internal electrodes 120 and 130 will be described in detail.

8 to 11, the multilayer ceramic capacitor 1000 of the present embodiment is a multilayer ceramic capacitor in which the fourth to sixth external electrodes 144 to 146 are formed on the second main surface S2 of the ceramic body 110, And are disposed to face the third external electrodes 141-143.

At this time, the fourth to sixth external electrodes 141 to 146 may be formed to extend to a part of the third and fourth side faces S5 and S6 in the width direction of the ceramic body 110, if necessary.

The fourth to sixth external electrodes 144 to 146 have a triple layer structure and include fourth to sixth conductive layers 144a to 146a which are in contact with and connected to the lead portions of the corresponding internal electrodes, A fourth through sixth nickel (Ni) plating layers 144b-146b formed to cover the fourth through sixth conductive layers 144a-146a, respectively; and a fourth through sixth nickel plating layers 144b-146b formed to cover the fourth through sixth nickel plating layers 144b- 4 to 6 tin (Sn) plating layers 144c-146c.

The first internal electrode 120 is exposed through the second main surface S2 of the ceramic body 110 to form fourth and fifth external electrodes 144 and 145 formed on the second main surface S2 of the ceramic body 110, And fourth and fifth lead portions 123 and 124, respectively.

The second internal electrode 130 is disposed between the third and fourth lead portions 123 and 124 and is exposed through the second main surface S2 of the ceramic body 110 to be connected to the sixth external electrode 146 And may have a sixth lead portion 132.

If the internal and external structures of the multilayer ceramic capacitor 1000 are formed in a vertically symmetric structure as described above, the directionality of the capacitor can be eliminated.

That is, the multilayer ceramic capacitor 1000 has a vertically symmetrical structure, and it is possible to prevent defects caused by reversing the mounting surface of the substrate during mounting.

Therefore, since any one of the first and second main surfaces S1 and S2 of the multilayer ceramic capacitor 1000 can be provided as a mounting surface, the multilayer ceramic capacitor 1000 can be mounted on a substrate without considering the orientation of the mounting surface .

At this time, the smallest one of the longitudinal margins a1, a2, c1, and c2 not in contact with the corresponding lead portions of the fourth to sixth external electrodes 144-146 may be 20.2 탆 or more.

The smallest one of the longitudinal margins a1, a2, c1, and c2 not in contact with the corresponding lead portions in the fourth to sixth external electrodes 144 to 146 is less than 20 占 퐉, The load reliability may be deteriorated.

Further, the smaller of the intervals b1 and b2 of the adjacent external electrodes may be 126.9 占 퐉 or more.

If the spacing (b1, b2) of the adjacent external electrodes is less than 126.9 占 퐉, a short circuit may occur during mounting on the substrate.

The height d of the side band of each of the fourth to sixth external electrodes 144 to 144 is preferably 73.4 占 퐉 or more.

When the height d of the side band of the fourth to sixth external electrodes 144 to 144 is 73.4 占 퐉 or more, the fixing strength is improved and defects do not occur, and the side faces of the fourth to sixth external electrodes 144 to 146 If the height d of the band is less than 73.4 占 퐉, the adhesion strength of the fourth to sixth external electrodes 144-146 may occur.

12 is a perspective view showing a structure in which the multilayer ceramic capacitor 1000 'of FIG. 8 has another type of external electrode.

12, the fourth to sixth external electrodes 144 to 146 are electrically connected to the corresponding lead portions of the first and second internal electrodes 120 and 130, respectively, for forming a capacitance, The first and second external electrodes 144 and 145 extend to a portion of the third and fourth side faces S5 and S6 in the width direction of the ceramic body 110 to form a first side band, 110 and a second side band extending respectively to portions of the first and second side surfaces S3, S4 in the longitudinal direction of the second side surface 110, respectively.

At this time, the height d of the first side band of each of the fourth to sixth external electrodes 144-146 is 40.0 탆 or more, and the height d of the second side band of the fourth and fifth external electrodes 144, The height (e) is preferably 30.3 占 퐉 or more.

The sum of the height d of the first side band of the fourth to sixth external electrodes 144-146 and the height e of the second side band of the fourth and fifth external electrodes 144 and 145 is 64.1 탆 , The adhesion strength of the fourth to sixth external electrodes 144 to 144 may be poor.

On the other hand, the thicknesses of the conductive layers and the plating layers of the first to third external electrodes shown in Table 1, the presence / absence of high temperature / humidity resistance load, the shipment defective ratio, the poor adhesion strength and the ESL value The same can be applied.

The mounting substrate of the multilayer ceramic capacitor

FIG. 13 is a perspective view showing a state in which the multilayer ceramic capacitor of FIG. 8 is mounted on a substrate, and FIG. 14 is a sectional view of FIG.

13 and 14, a mounting substrate 200 of a multilayer ceramic capacitor according to the present embodiment includes a substrate 210 on which a multilayer ceramic capacitor is mounted, And third electrode pads 221, 222, and 223.

At this time, the multilayer ceramic capacitor is electrically connected to the substrate 210 by the solder 230 in a state where the first to third external electrodes 141 to 143 are in contact with the first to third electrode pads 221, 222 and 223, As shown in FIG.

14, reference numeral 224 denotes a ground terminal, and reference numeral 225 denotes a power supply terminal.

8, but the present invention is not limited to this. For example, as shown in FIGS. 1, 5, 6, and 12, the multilayer ceramic capacitor shown in FIG. A multilayer ceramic capacitor can be mounted on a substrate with a similar structure to form a mounting substrate.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims.

It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

100, 100 ', 100 ",1000; Multilayer Ceramic Capacitors
110; Ceramic body
111; Dielectric layer
112, 113; Cover layer
120; The first internal electrode
121-124; The first to fourth lead portions
130; The second internal electrode
131, 132; The fifth and sixth lead portions
141-146; The first to sixth external electrodes
200; Mounting substrate
210; Board
221, 222, 223; The first to third electrode pads
230; Solder

Claims (29)

  1. A ceramic body in which a plurality of dielectric layers are stacked in a width direction;
    An active layer including a plurality of first and second internal electrodes arranged alternately with the dielectric layer interposed therebetween;
    First and second lead portions extending from the first internal electrode to be exposed through a mounting surface of the ceramic body, the first and second lead portions being spaced apart from each other along a longitudinal direction of the ceramic body;
    A third lead portion extending from the second internal electrode to be exposed through a mounting surface of the ceramic body, the third lead portion being disposed between the first and second lead portions;
    A plurality of side walls extending from the side surface of the ceramic body to extend along the longitudinal direction of the ceramic body and connected to the first and second lead portions, First and second external electrodes having a first electrode and a second electrode; And
    A third external electrode disposed between the first and second external electrodes on the mounting surface of the ceramic body, the third external electrode being connected to the third lead portion and having side bands extending respectively at portions of both sides of the ceramic body; / RTI >
    The distance between adjacent lead portions is not less than 167.3 占 퐉 and not more than 500.7 占 퐉,
    Wherein a margin in a longitudinal direction of one of the first to third external electrodes not in contact with the corresponding lead portion is 20.2 占 퐉 or more and 186.9 占 퐉 or less.
  2. The method according to claim 1,
    Wherein a distance between the first or second external electrode and the third external electrode is 126.9 占 퐉 or more and 460.3 占 퐉 or less.
  3. The method according to claim 1,
    And the side bands of the first to third external electrodes are respectively 73.4 占 퐉 or more and not more than the total chip height.
  4. The method according to claim 1,
    Wherein the first and second internal electrodes are spaced apart from both longitudinal sides of the ceramic body.
  5. The method according to claim 1,
    Wherein the first to third external electrodes include a conductive layer connected to and in contact with each corresponding lead portion, and a plating layer formed to cover the conductive layer.
  6. 6. The method of claim 5,
    Wherein the plating layer includes a nickel (Ni) plating layer formed to cover the conductive layer, and a tin (Sn) plating layer formed to cover the nickel plating layer.
  7. The method according to claim 1,
    Fourth and fifth lead portions extending from the first internal electrode to be exposed through a surface facing the mounting surface of the ceramic body, the fourth and fifth lead portions being spaced apart from each other along the longitudinal direction of the ceramic body;
    A sixth lead portion extending from the second internal electrode to be exposed through a surface facing the mounting surface of the ceramic body, the sixth lead portion being disposed between the fourth and fifth lead portions; And
    An insulating layer disposed on a surface facing the mounting surface of the ceramic body; And a capacitor.
  8. The method according to claim 1,
    Wherein the first internal electrodes are spaced apart from each other in the longitudinal direction and have fourth and fifth lead portions exposed on a surface facing the mounting surface of the ceramic body,
    The second internal electrode is exposed at a surface facing the mounting surface of the ceramic body and has a sixth lead portion spaced apart from the fourth and fifth lead portions,
    Fourth and fifth external electrodes formed to be spaced apart from each other in a longitudinal direction on a surface facing a mounting surface of the ceramic body and connected to the fourth and fifth lead portions, respectively; And
    A sixth external electrode formed separately from the fourth external electrode and the fifth external electrode on a surface facing the mounting surface of the ceramic body, the sixth external electrode connected to the sixth lead portion; And a capacitor.
  9. 9. The method of claim 8,
    Wherein the one or more longitudinal margins not in contact with the corresponding lead portions of the fourth to sixth external electrodes are 20.2 占 퐉 or more and 186.9 占 퐉 or less.
  10. 9. The method of claim 8,
    And a distance between the fourth or fifth outer electrode and the sixth outer electrode is not less than 126.9 占 퐉 and not more than 460.3 占 퐉.
  11. 9. The method of claim 8,
    Each of the fourth to sixth external electrodes has a side band extending to a portion of both sides in the width direction of the ceramic body, and the height of the side band is not less than 73.4 占 퐉 and not more than the entire height of the chip.
  12. 9. The method of claim 8,
    Wherein the fourth to sixth external electrodes include a conductive layer connected to and in contact with each corresponding lead portion, and a plating layer formed to cover the conductive layer.
  13. 13. The method of claim 12,
    Wherein the plating layer includes a nickel (Ni) plating layer formed to cover the conductive layer, and a tin (Sn) plating layer formed to cover the nickel plating layer.
  14. The method according to claim 1,
    And a cover layer formed on both sides in the width direction of the active layer.
  15. A ceramic body in which a plurality of dielectric layers are stacked in a width direction;
    An active layer including a plurality of first and second internal electrodes arranged alternately with the dielectric layer interposed therebetween;
    First and second lead portions extending from the first internal electrode to be exposed through a mounting surface of the ceramic body, the first and second lead portions being spaced apart from each other along a longitudinal direction of the ceramic body;
    A third lead portion extending from the second internal electrode to be exposed through a mounting surface of the ceramic body, the third lead portion being disposed between the first and second lead portions;
    A plurality of first and second lead portions which are respectively disposed on a mounting surface of the ceramic body so as to be spaced apart from each other along a longitudinal direction of the ceramic body and which are respectively connected to the first and second lead portions, First and second external electrodes each having a side band and a second side band extending respectively at portions of both longitudinal sides of the ceramic body; And
    And a third external electrode disposed between the first and second external electrodes on a mounting surface of the ceramic body and connected to the third lead portion and having a first side band extending to a portion of both sides of the ceramic body, ; / RTI >
    The distance between adjacent lead portions is not less than 167.3 占 퐉 and not more than 500.7 占 퐉,
    Wherein a margin in a longitudinal direction of one of the first to third external electrodes not in contact with the corresponding lead portion is 20.2 占 퐉 or more and 186.9 占 퐉 or less.
  16. 16. The method of claim 15,
    Wherein a distance between the first or second external electrode and the third external electrode is 126.9 占 퐉 or more and 460.3 占 퐉 or less.
  17. 16. The method of claim 15,
    Wherein the sum of the heights of the first side band and the second side band is not less than 64.1 占 퐉 and not more than twice the overall height of the chip.

  18. 16. The method of claim 15,
    Wherein the first and second internal electrodes are spaced apart from both longitudinal sides of the ceramic body.
  19. 16. The method of claim 15,
    Wherein the first to third external electrodes include a conductive layer connected to and in contact with each corresponding lead portion, and a plating layer formed to cover the conductive layer.
  20. 20. The method of claim 19,
    Wherein the plating layer includes a nickel (Ni) plating layer formed to cover the conductive layer, and a tin (Sn) plating layer formed to cover the nickel plating layer.
  21. 16. The method of claim 15,
    Fourth and fifth lead portions extending from the first internal electrode to be exposed through a surface facing the mounting surface of the ceramic body, the fourth and fifth lead portions being spaced apart from each other along the longitudinal direction of the ceramic body;
    A sixth lead portion extending from the second internal electrode to be exposed through a surface facing the mounting surface of the ceramic body, the sixth lead portion being disposed between the fourth and fifth lead portions; And
    An insulating layer disposed on a surface facing the mounting surface of the ceramic body; And a capacitor.
  22. 16. The method of claim 15,
    Wherein the first internal electrodes are spaced apart from each other in the longitudinal direction and have fourth and fifth lead portions exposed on a surface facing the mounting surface of the ceramic body,
    The second internal electrode is exposed at a surface facing the mounting surface of the ceramic body and has a sixth lead portion spaced apart from the fourth and fifth lead portions,
    Fourth and fifth external electrodes formed to be spaced apart from each other in a longitudinal direction on a surface facing a mounting surface of the ceramic body and connected to the fourth and fifth lead portions, respectively; And
    A sixth external electrode formed separately from the fourth external electrode and the fifth external electrode on a surface facing the mounting surface of the ceramic body, the sixth external electrode connected to the sixth lead portion; And a capacitor.
  23. 23. The method of claim 22,
    Wherein the one or more longitudinal margins not in contact with the corresponding lead portions of the fourth to sixth external electrodes are 20.2 占 퐉 or more and 186.9 占 퐉 or less.
  24. 23. The method of claim 22,
    And a distance between the fourth or fifth outer electrode and the sixth outer electrode is not less than 126.9 占 퐉 and not more than 460.3 占 퐉.
  25. 23. The method of claim 22,
    The fourth to sixth external electrodes each have a first side band extending to a portion of both widthwise sides of the ceramic body,
    The fourth and fifth external electrodes further have second side bands extending respectively at portions of both longitudinal sides of the ceramic body,
    Wherein the sum of the heights of the first side band and the second side band is not less than 64.1 占 퐉 and not more than twice the overall height of the chip.
  26. 23. The method of claim 22,
    Wherein the fourth to sixth external electrodes include a conductive layer connected to and in contact with each corresponding lead portion, and a plating layer formed to cover the conductive layer.
  27. 27. The method of claim 26,
    Wherein the plating layer includes a nickel (Ni) plating layer formed to cover the conductive layer, and a tin (Sn) plating layer formed to cover the nickel plating layer.
  28. 16. The method of claim 15,
    And a cover layer formed on both sides in the width direction of the active layer.
  29. A substrate having first to third electrode pads on an upper surface thereof; And
    The multilayer ceramic capacitor of any one of claims 1 to 28, wherein first to third external electrodes are disposed on the first to third electrode pads, respectively. And a capacitor connected to the capacitor.
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CN201810198872.1A CN108400014B (en) 2013-10-29 2014-10-29 Multilayer ceramic capacitor and board having the same
US14/527,662 US9396879B2 (en) 2013-10-29 2014-10-29 Multilayer ceramic capacitor and board having the same
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KR20150050520A (en) 2015-05-08

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