JP2003217969A - Manufacturing method of laminated ceramic capacitor - Google Patents

Manufacturing method of laminated ceramic capacitor

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Publication number
JP2003217969A
JP2003217969A JP2002015161A JP2002015161A JP2003217969A JP 2003217969 A JP2003217969 A JP 2003217969A JP 2002015161 A JP2002015161 A JP 2002015161A JP 2002015161 A JP2002015161 A JP 2002015161A JP 2003217969 A JP2003217969 A JP 2003217969A
Authority
JP
Japan
Prior art keywords
external electrode
ceramic capacitor
electrode layer
manufacturing
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002015161A
Other languages
Japanese (ja)
Inventor
Yohei Watabe
洋平 渡部
Masaaki Nakamura
政昭 仲村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
NEC Tokin Hyogo Ltd
Original Assignee
NEC Tokin Corp
NEC Tokin Ceramics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Tokin Corp, NEC Tokin Ceramics Corp filed Critical NEC Tokin Corp
Priority to JP2002015161A priority Critical patent/JP2003217969A/en
Publication of JP2003217969A publication Critical patent/JP2003217969A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a laminated ceramics capacitor for forming an external electrode terminal, wherein remaining stress due to contraction of a Cu paste is reduced, without degrading adhesion to a dielectric ceramics in a sintering process, while not allowing voltage-resistance and insulation property to degrade and no inter-layer peeling occurs in a plating process. <P>SOLUTION: An internal electrode 2 comprising Ni is laminated alternately on a dielectric ceramics 1, whose main component is BaTiO<SB>3</SB>. At both ends of a chip, a first Cu external electrode 3 is formed for electrical connection with the internal electrode. A second Ag external electrode 4 is baked on the first Cu external electrode 3, over which a plating layer 5 is formed, to obtain a laminated ceramic capacitor 10. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、内部電極に卑金属
を用いた積層セラミックコンデンサの製造方法に関し、
特に、外部電極の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a monolithic ceramic capacitor using a base metal for internal electrodes,
In particular, it relates to a method of forming an external electrode.

【0002】[0002]

【従来の技術】従来の積層セラミックコンデンサは、次
のようにして製造される。まず、チタン酸バリウムを主
成分とする誘電体セラミック粉末と樹脂等のバインダー
を、有機溶剤中に分散、混合させたスラリーを、ドクタ
ーブレード法等で一定の厚みに成膜し、グリーンシート
を作製する。次にスクリーン印刷法により、銅(C
u)、ニッケル(Ni)等の低抵抗金属と有機ビヒクル
からなる内部電極ぺーストを、上記のグリーンシート上
へ印刷して内部電極を形成する。
2. Description of the Related Art A conventional monolithic ceramic capacitor is manufactured as follows. First, a dielectric ceramic powder containing barium titanate as a main component and a binder such as a resin are dispersed and mixed in an organic solvent, and a slurry is formed into a film having a certain thickness by a doctor blade method or the like to produce a green sheet. To do. Next, copper (C
u), an internal electrode paste made of a low resistance metal such as nickel (Ni) and an organic vehicle is printed on the green sheet to form internal electrodes.

【0003】さらに、内部電極が交互に対向する電極と
したこのグリーンシートを打ち抜き、金型内へ積層し、
熱プレス等で圧着して積層体を得る。この積層体を一個
一個のコンデンサ素子に切断し、脱バインダー、焼成を
行い、積層セラミックコンデンサ素子を得る。こうして
得られた積層セラミックコンデンサ素子の対向する内部
電極の各々の電極引き出し部が露出する両端面に、外部
電極端子を形成し、積層セラミックコンデンサが完成す
る。
Further, this green sheet, which is an electrode in which the internal electrodes are alternately opposed to each other, is punched out and laminated in a mold,
A laminated body is obtained by pressure bonding with a hot press or the like. This laminated body is cut into individual capacitor elements, debindered and fired to obtain laminated ceramic capacitor elements. External electrode terminals are formed on both end faces of the thus obtained multilayer ceramic capacitor element, where the electrode lead-out portions of the opposing internal electrodes are exposed, and the multilayer ceramic capacitor is completed.

【0004】従来、内部電極にPdあるいはAg−Pd
を用いた積層セラミックコンデンサの外部電極にはAg
が用いられていたが、大気中で焼き付けるため、内部電
極にCuやNi等を用いた積層セラミックコンデンサに
適用した場合、内部電極と外部電極の接続部が酸化して
必要な電気特性が得られなくなってしまう。
Conventionally, Pd or Ag-Pd is used as the internal electrode.
Ag is used for the external electrode of the monolithic ceramic capacitor using
However, when it is applied to a laminated ceramic capacitor that uses Cu, Ni, or the like for the internal electrodes, it burns in the air, and the connection between the internal and external electrodes is oxidized to obtain the required electrical characteristics. It's gone.

【0005】そのため、外部電極形成工程での内部電極
層の酸化を防止し、良好な電気的接続性と強固な密着性
を得ることが重要である。
Therefore, it is important to prevent oxidation of the internal electrode layers in the step of forming external electrodes to obtain good electrical connectivity and strong adhesion.

【0006】卑金属材料を用いた内部電極層を有する積
層セラミックコンデンサの外部電極組成物として、特公
昭63−14856号や特公平8−4055号公報に
は、銅粉末が50重量%以上80重量%以下の範囲、ガ
ラスフリット5重量%以上20重量%以下の範囲及び有
機ビヒクル10重量%以上30重量%以下の範囲からな
る銅ペーストを塗布し、還元雰囲気中で焼き付け形成す
ることが開示されている。この還元雰囲気での焼き付け
は、600〜900℃の温度でN雰囲気中で行われ、
チップ部品を炉に挿入してから炉出し時間は60分前後
で行われている。ここでは、ぺースト中の有機ビヒクル
成分を効率良く分解するために、特開平5−24308
3号公報や特開平11−195553号公報等で開示さ
れているように、300〜600℃温度ゾーンにおい
て、N雰囲気中に100ppm以下の微量な酸素をド
ープして焼き付けを行っている。
As an external electrode composition of a monolithic ceramic capacitor having an internal electrode layer using a base metal material, Japanese Patent Publication No. 63-14856 and Japanese Patent Publication No. 8-4055 disclose that copper powder is 50% by weight or more and 80% by weight or more. It is disclosed that a copper paste having the following range, a glass frit in the range of 5% by weight to 20% by weight and a range of the organic vehicle in the range of 10% to 30% by weight is applied and baked in a reducing atmosphere. . The baking in this reducing atmosphere is performed in a N 2 atmosphere at a temperature of 600 to 900 ° C.,
After the chip parts are inserted into the furnace, the furnace removal time is about 60 minutes. Here, in order to efficiently decompose the organic vehicle component in the paste, JP-A-5-24308 is used.
As disclosed in Japanese Unexamined Patent Publication No. 3 (1999), Japanese Unexamined Patent Publication (Kokai) No. 11-195553, etc., in a temperature zone of 300 to 600 ° C., a small amount of oxygen of 100 ppm or less is doped in N 2 atmosphere and baking is performed.

【0007】[0007]

【発明が解決しようとする課題】従来、Cuによる外部
電極焼き付けは、Cuの酸化による内部電極層との電気
的接続性の劣化を防止するためと誘電体セラミックとの
密着性を得るために低酸素濃度で行っている。
Conventionally, the external electrode baking with Cu is low in order to prevent the deterioration of the electrical connection with the internal electrode layer due to the oxidation of Cu and to obtain the adhesion with the dielectric ceramic. Oxygen concentration is used.

【0008】しかしながら、外部電極を焼き付けるため
の処理量が増加した場合、有機ビヒクルを分解する脱バ
インダのためのゾーンで、数10ppmの酸素を含む雰
囲気では脱バインダは十分でなく、分解されなかった有
機ビヒクル成分がCu外部電極内に残ってしまうと、ガ
ラスフリットの溶融温度においてもビヒクルの分解にお
ける酸素分圧の変化により、誘電体セラミックとの密着
性が低下したり、Cuぺーストの収縮率が大きくなり残
留応力が残るため、高温負荷、耐湿試験及び基板実装後
の信頼性に問題があった。
However, when the amount of processing for baking the external electrode was increased, the binder was not decomposed in the zone for binder removal for decomposing the organic vehicle in an atmosphere containing several tens of ppm of oxygen and was not decomposed. If the organic vehicle component remains in the Cu external electrode, the adhesiveness with the dielectric ceramic is reduced due to the change in oxygen partial pressure during the decomposition of the vehicle even at the melting temperature of the glass frit, and the contraction rate of the Cu paste is reduced. Becomes large and residual stress remains, so there were problems in high temperature load, humidity resistance test, and reliability after mounting on the board.

【0009】また、ガラスフリットにホウ珪酸亜鉛系な
どの亜鉛を含んだものを使用した場合、焼き付け後のめ
っき工程においてSnめっきを施す際、ウィスカを防止
するためにNiめっきを施す必要がある。しかし、ワッ
ト浴等のNiめっきは、酸性であるため、Niめっき液
が外部電極内に浸透しやすくなり、耐電圧、絶縁性の劣
化及び層間剥離(デラミネーション)を引き起こすなど
の問題点があった。
When glass frit containing zinc such as zinc borosilicate is used, it is necessary to perform Ni plating in order to prevent whiskers when Sn plating is applied in the plating step after baking. However, since the Ni plating such as Watt bath is acidic, the Ni plating solution easily penetrates into the external electrode, which causes problems such as deterioration of withstand voltage, insulation, and delamination. It was

【0010】そこで、本発明の技術的課題は、焼き付け
工程において、誘電体セラミックとの密着性を低下させ
ず、Cuぺーストの収縮による残留応力を緩和するとと
もに、めっき工程においても耐電圧、絶縁性の劣化及び
層間剥離を生じない、外部電極端子を形成することがで
きる積層セラミックコンデンサの製造方法を提供するこ
とにある。
Therefore, the technical problem of the present invention is to reduce the residual stress due to the contraction of the Cu paste without lowering the adhesion with the dielectric ceramic in the baking process, and also to withstand the voltage and insulation in the plating process. It is an object of the present invention to provide a method for manufacturing a monolithic ceramic capacitor capable of forming an external electrode terminal without causing deterioration of properties and delamination.

【0011】[0011]

【課題を決するための手段】本発明によれば、誘電体セ
ラミック層とNiを主成分とした内部電極層とを交互に
複数層積み重ねて形成する積層体に外部電極を設けてな
る積層セラミックコンデンサの製造方法において、Ni
を主成分とした内部電極層と電気的に接続される第1の
外部電極層として、Cuを主成分とする導電ぺーストを
還元雰囲気及び真空雰囲気の内の少なくとも一方の雰囲
気で焼き付けた後、第1の外部電極層の上に第2の外部
電極層をCu、Ni、Ag等の低抵抗導電ペーストの内
の少なくとも1種類を第1の外部電極層より低い温度で
還元雰囲気及び真空雰囲気の少なくとも一方の雰囲気で
焼き付けた後、その上に中性のNiめっき及びSnめっ
きを施した2層以上の電極層で外部電極が構成されてい
る積層セラミックコンデンサの製造方法が得られる。
According to the present invention, a laminated ceramic capacitor having external electrodes provided on a laminated body formed by alternately stacking a plurality of dielectric ceramic layers and internal electrode layers containing Ni as a main component is formed. In the manufacturing method of
After baking a conductive paste containing Cu as a main component in at least one of a reducing atmosphere and a vacuum atmosphere as a first external electrode layer electrically connected to the internal electrode layer containing A second external electrode layer is formed on the first external electrode layer by applying at least one of low-resistance conductive pastes such as Cu, Ni, and Ag at a temperature lower than that of the first external electrode layer in a reducing atmosphere and a vacuum atmosphere. It is possible to obtain a method for manufacturing a laminated ceramic capacitor in which external electrodes are formed by two or more electrode layers which are neutral Ni-plated and Sn-plated after baking in at least one atmosphere.

【0012】本発明によれば、Niを主成分とした内部
電極層と電気的に接続される第1の外部電極層のCuを
主成分とする導電ぺーストとして、Cu金属粉末とホウ
珪酸亜鉛及びホウ珪酸鉛を含まないガラスフリットと有
機ビヒクルから構成され、粒径が異なる2種類以上のC
u金属粉末を使用することによって、還元雰囲気及び真
空雰囲気の少なくとも一方の雰囲気で焼き付けた際に、
第1の外部電極層内の空孔状態が5〜20%になるよう
にした積層セラミックコンデンサの製造方法が得られ
る。
According to the present invention, Cu metal powder and zinc borosilicate are used as the conductive paste containing Cu as a main component of the first external electrode layer electrically connected to the internal electrode layer containing Ni as a main component. And two or more types of C composed of glass frit not containing lead borosilicate and organic vehicle and having different particle sizes
By using u metal powder, when baked in at least one of a reducing atmosphere and a vacuum atmosphere,
A method of manufacturing a monolithic ceramic capacitor in which the void state in the first external electrode layer is 5 to 20% is obtained.

【0013】即ち、本発明は、誘電体セラミック層とN
iを主成分とした内部電極層とを交互に複数層積み重ね
て形成する積層体に外部電極を設け、該外部電極上にめ
っきを施した積層セラミックコンデンサの製造方法にお
いて、前記内部電極層と電気的に接続される第1の外部
電極層として、Cuを主成分とする導電ペーストを還元
雰囲気及び真空雰囲気の内の少なくとも一方の雰囲気で
焼き付けた後、前記第1の外部電極層の上に第2の外部
電極層として低抵抗導電ぺーストのうち少なくとも1種
類を前記第1の外部電極層より低い温度で還元雰囲気及
び真空雰囲気のうち少なくとも一方の雰囲気で焼き付け
ることを特徴とする積層セラミックコンデンサの製造方
法である。
That is, according to the present invention, the dielectric ceramic layer and the N
In a method for manufacturing a laminated ceramic capacitor, in which external electrodes are provided on a laminated body formed by alternately stacking a plurality of internal electrode layers containing i as a main component, and the external electrodes are plated, the internal electrode layers and the As a first external electrode layer to be electrically connected, a conductive paste containing Cu as a main component is baked in at least one of a reducing atmosphere and a vacuum atmosphere, and then a first external electrode layer is formed on the first external electrode layer. A multilayer ceramic capacitor, wherein at least one kind of low resistance conductive paste is baked as a second external electrode layer at a temperature lower than that of the first external electrode layer in at least one atmosphere of a reducing atmosphere and a vacuum atmosphere. It is a manufacturing method.

【0014】また、本発明は、上記の積層セラミックコ
ンデンサの製造方法において、前記内部電極層と前記第
1の外部電極層に用いられる導電ぺーストとして、Cu
粉末とZn及びPbを含まないガラスフリットと有機ビ
ヒクルから構成され、前記Cu粉末に粒径が異なる2種
類以上を使用し、還元雰囲気及び真空雰囲気のうち少な
くとも一方の雰囲気で焼き付け、前記第1の外部電極層
内の空孔率が5〜20%であることを特徴とする積層セ
ラミックコンデンサの製造方法である。
Further, according to the present invention, in the above-mentioned method for manufacturing a monolithic ceramic capacitor, Cu is used as a conductive paste used for the internal electrode layers and the first external electrode layers.
Powder, glass frit not containing Zn and Pb, and an organic vehicle, two or more kinds of Cu powders having different particle sizes are used, and baked in at least one atmosphere of a reducing atmosphere and a vacuum atmosphere. A method of manufacturing a monolithic ceramic capacitor, wherein the porosity in the external electrode layer is 5 to 20%.

【0015】[0015]

【発明の実施の形態】以下に本発明の実施の形態つい
て、図面を参照しながら説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【0016】図1は、本発明における電極端子形成方法
により製造した一実施の形態の積層セラミックコンデン
サの断面図である。図1に示すように、チタン酸バリウ
ム(BaTiO)を主成分とする誘電体セラミック1
にNiからなる内部電極2が交互に積層され、チップ両
端に内部電極と電気的接続を得るための第1のCu外部
電極3が形成され、第1のCu外部電極3上に第2のA
g外部電極4を焼き付け形成した上にめっき層5を施し
て、積層セラミックコンデンサ10が形成されている。
FIG. 1 is a cross-sectional view of a monolithic ceramic capacitor of an embodiment manufactured by the electrode terminal forming method of the present invention. As shown in FIG. 1, a dielectric ceramic 1 containing barium titanate (BaTiO 3 ) as a main component 1
Internal electrodes 2 made of Ni are alternately laminated, first Cu external electrodes 3 for obtaining electrical connection with the internal electrodes are formed at both ends of the chip, and second A external electrodes 3 are formed on the first Cu external electrodes 3.
g A laminated ceramic capacitor 10 is formed by applying a plating layer 5 on the external electrodes 4 by baking.

【0017】図2は、本発明における電極端子形成方法
により製造した他の実施の形態の積層セラミックコンデ
ンサの断面図である。図2に示すように、BaTiO
を主成分とする誘電体セラミック1にNiからなる内部
電極2が交互に積層され、チップ両端に内部電極と電気
的接続を得るための第1のCu外部電極3が形成され、
第1のCu外部電極3上に第2のCu外部電極6を焼き
付け形成した上にめっき層5を施して、積層セラミック
コンデンサ20が形成されている。
FIG. 2 is a sectional view of a laminated ceramic capacitor of another embodiment manufactured by the electrode terminal forming method of the present invention. As shown in FIG. 2, BaTiO 3
Internal electrodes 2 made of Ni are alternately laminated on a dielectric ceramic 1 containing as a main component, and first Cu external electrodes 3 for electrically connecting to the internal electrodes are formed at both ends of the chip.
The second Cu external electrode 6 is formed on the first Cu external electrode 3 by baking, and the plating layer 5 is formed on the second Cu external electrode 6 to form the monolithic ceramic capacitor 20.

【0018】第2のCu外部電極6は、第1のCu外部
電極3とガラスフリット添加量を変え、焼き付け温度を
50℃下げたものを使用した。
The second Cu external electrode 6 used was one in which the amount of glass frit added was changed from that of the first Cu external electrode 3 and the baking temperature was lowered by 50 ° C.

【0019】図1の場合、めっき層5は、第2のAg外
部電極4と実装時のはんだ濡れ性を確保するためのSn
めっきとの拡散による特性劣化を防ぐため、中性の無電
解Niめっきを2μm以上3μm以下の範囲の厚みを、
Cu外部電極上に被覆した後、中性の電解Snめっきを
6μm以上12μm以下の範囲の厚みを施した。
In the case of FIG. 1, the plating layer 5 is Sn for ensuring solder wettability at the time of mounting with the second Ag external electrode 4.
In order to prevent characteristic deterioration due to diffusion with plating, neutral electroless Ni plating with a thickness in the range of 2 μm to 3 μm is used.
After coating on the Cu external electrode, neutral electrolytic Sn plating was applied to a thickness in the range of 6 μm to 12 μm.

【0020】ここで、Niめっきが2μm未満である
と、剥離強度が低下し、また3μmを超えると、Niめ
っきによる引っ張り応力が大きくなるので、Niめっき
を2μm以上3μm以下の範囲の厚みとした。また、S
nめっきが6μm未満であると、はんだとの濡れ性が不
十分となり、はんだ接合のばらつきが大きくなり、ま
た、12μmを超えると、めっき時間が大きくなるの
で、Snめっきを6μm以上12μm以下の範囲とし
た。
Here, if the Ni plating is less than 2 μm, the peel strength is lowered, and if it exceeds 3 μm, the tensile stress due to the Ni plating becomes large. Therefore, the Ni plating has a thickness in the range of 2 μm or more and 3 μm or less. . Also, S
When the n plating is less than 6 μm, the wettability with solder becomes insufficient, and the solder joint variation becomes large, and when it exceeds 12 μm, the plating time becomes long. Therefore, Sn plating is performed in the range of 6 μm to 12 μm. And

【0021】図1及び図2に示す本発明の積層セラミッ
クコンデンサ10、20を、次のように製造した。誘電
体セラミックとしてBaTiO粉末を主成分とし、有
機バインダ、分散剤、可塑剤及び有機溶剤を秤量、混錬
しスラリー化して、ドクターブレード法などを用いてグ
リーンシート化を行った後、Ni粉末と有機ビヒクルを
混錬した内部電極2用のぺーストをスクリーン印刷法に
より、グリーンシート上に形成したものを積層、熱プレ
スによって得られた積層体を所定のチップサイズになる
ように切断してセラミックコンデンサチップ素子が得ら
れる。このセラミックコンデンサチップ素子を雰囲気中
で焼成した後に,電気的な接続を得るためにCu粉末、
ガラスフリット及び有機ビヒクルからなる第1の外部電
極3となる端子用ぺーストを塗布した。
The monolithic ceramic capacitors 10 and 20 of the present invention shown in FIGS. 1 and 2 were manufactured as follows. BaTiO 3 powder as a main component as a dielectric ceramic, an organic binder, a dispersant, a plasticizer, and an organic solvent are weighed, kneaded to form a slurry, and a green sheet is formed using a doctor blade method or the like, and then Ni powder The paste for the internal electrode 2 obtained by kneading and the organic vehicle was laminated on the green sheet by screen printing, and the laminate obtained by hot pressing was cut into a predetermined chip size. A ceramic capacitor chip element is obtained. After firing the ceramic capacitor chip element in the atmosphere, Cu powder, in order to obtain an electrical connection,
A terminal paste to be the first external electrode 3 made of glass frit and an organic vehicle was applied.

【0022】ここで、本発明の実施の形態における外部
電極端子用ペーストの焼き付けの一例を図3を参照して
説明する。図3に示すように、炉内焼き付け時間を80
分とし、第1の一定温度保持区間の温度を300℃、1
0分間保持し、その後、第2の一定温度保持区間の温度
900℃、10分間保持を行った。焼き付け雰囲気とし
てN中で行い、第1の保持区間の酸素濃度は、20p
pmとし、他の区間の酸素濃度は5ppmになるように
設定を行い外部電極を焼き付けた。
An example of baking the external electrode terminal paste in the embodiment of the present invention will be described with reference to FIG. As shown in FIG. 3, the baking time in the furnace is 80
Minutes, the temperature of the first constant temperature holding section is 300 ° C., 1
After holding for 0 minutes, the temperature in the second constant temperature holding section was held at 900 ° C. for 10 minutes. The baking is performed in N 2 as a baking atmosphere, and the oxygen concentration in the first holding section is 20 p.
pm, and the oxygen concentration in other sections was set to 5 ppm, and the external electrodes were baked.

【0023】次に、第2の外部電極4または6となる端
子用ぺーストを塗布した後、第1の外部電極端子の焼き
付けと同じ焼き付けプロファイルで焼き付けを行った。
ただし、焼き付けプロファイルの第2の一定温度保持区
間の温度は800〜850℃で行った。焼き付け後、中
性のNiめっき(電解あるいは無電解どちらでも良い)
をバレルで行った後、中性のSnめっきを施して積層セ
ラミックチップコンデンサが得られた。
Next, after a terminal paste to be the second external electrodes 4 or 6 was applied, baking was performed with the same baking profile as the baking of the first external electrode terminals.
However, the temperature in the second constant temperature holding section of the baking profile was 800 to 850 ° C. Neutral Ni plating after baking (either electrolytic or electroless is acceptable)
Was performed in the barrel, and then neutral Sn plating was performed to obtain a multilayer ceramic chip capacitor.

【0024】次に、本発明の実施の形態における外部電
極端子用ペーストについて説明する。第1の外部電極端
子用ぺーストは、粒径の異なる2種類以上の金属粉末を
使用し、外部電極焼き付け後の電極層の空孔7状態を変
化させた。無機成分として、平均粒径1μmの球状銅粉
末及びこの粉末粒径より大きく平均粒径が10μm以下
の球状銅粉末とBa、Si系のガラスフリットを配合
し、この無機成分を80〜95重量%とし、残部に有機
ビヒクルを加え100重量%にしたものを3本ロールミ
ルにより混練し、外部電極用ぺーストを作製した。
Next, the external electrode terminal paste according to the embodiment of the present invention will be described. For the first external electrode terminal paste, two or more kinds of metal powders having different particle sizes were used, and the state of the holes 7 in the electrode layer after baking the external electrode was changed. As the inorganic component, spherical copper powder having an average particle size of 1 μm and spherical copper powder having an average particle size of 10 μm or less, which is larger than the powder particle size, and Ba or Si-based glass frit are blended, and 80 to 95% by weight of this inorganic component is mixed. After that, an organic vehicle was added to the rest to make 100% by weight, and the mixture was kneaded with a three-roll mill to prepare a paste for external electrodes.

【0025】第2の外部電極端子用ぺーストにおいて、
外部電極溶融温度を第1の外部電極より低くするため球
状粉末の粒径は1μm以下とし、Ba、Si系のガラス
フリットを配合し、この無機成分を80〜95重量%と
し、残部に有機ビヒクルを加え100重量%にしたもの
を3本ロールミルにより混練し、外部電極用ぺーストを
作製した。
In the second external electrode terminal paste,
In order to make the melting temperature of the external electrode lower than that of the first external electrode, the spherical powder has a particle size of 1 μm or less, and is mixed with Ba and Si based glass frit, and the inorganic component is 80 to 95% by weight, and the balance is an organic vehicle. Was added to 100% by weight and kneaded with a three-roll mill to prepare a paste for external electrodes.

【0026】本発明の実施の形態による外部端子焼き付
け条件にて焼き付けを行った積層セラミックコンデンサ
の外部電極端子の模式図を図4に示す。
FIG. 4 shows a schematic diagram of the external electrode terminals of the laminated ceramic capacitor baked under the external terminal baking conditions according to the embodiment of the present invention.

【0027】図4に示すように、誘電体セラミック1層
とNi内部電極2層からなるチップに第1のCu外部電
極3が形成され、第1のCu外部電極上3に第2のAg
外部電極4を焼き付け形成した上にめっき層5を施して
あり、第1のCu外部電極3は、有機ビヒクルの脱バイ
ンダと金属粉末粒径の差によって生じる金属粉末溶融状
態の変化により、空孔7を形成している。
As shown in FIG. 4, a first Cu external electrode 3 is formed on a chip composed of one layer of dielectric ceramic and two layers of Ni internal electrode, and a second Ag external electrode 3 is formed on the first Cu external electrode 3.
The external electrode 4 is baked and formed with a plating layer 5, and the first Cu external electrode 3 has pores due to the change in the metal powder molten state caused by the binder removal of the organic vehicle and the difference in the metal powder particle size. Forming 7.

【0028】このぺーストを積層セラミックコンデンサ
チップに塗布し、先に示した本発明の実施の形態による
外部端子焼き付け条件にて焼き付けを行い、電気的特
性、機械的特性(密着強度)及び信頼性について試験し
た。
This paste is applied to a laminated ceramic capacitor chip and baked under the external terminal baking conditions according to the above-described embodiment of the present invention to obtain electrical characteristics, mechanical characteristics (adhesion strength) and reliability. Was tested.

【0029】なお、積層セラミックコンデンサチップ
は、長さ3.2×幅1.6×厚み1.0mmで静電容量が
1μFとなる設計を使用した。得られた積層セラミック
コンデンサについて、電気特性は、LCRメータを用い
て、静電容量(C)を測定した。接合強度については、
引っ張り圧縮試験機を用い、外部電極端子上にφ1mm
のピンを垂直にはんだで接合したものを固定し、引っ張
って測定をした。判定の基準として、静電容量は、容量
ばらつきが±10%以内とし、密着強度は、はんだによ
る基板実装時に外部電極が剥がれない1.5kgf/m
以上を良品とした。外部電極空孔状態については、
積層セラミックコンデンサチップを樹脂に埋め込み、研
磨した後、画像解析装置を用いて外部電極層内の空孔率
を測定した。信頼性については、温度125℃で定格電
圧の4倍を印加する方法で500時間放置した後の絶縁
抵抗の変化で合否を判定する高温負荷試験、温度85℃
及び湿度85%RHの耐湿負荷試験を行った。その結果
を表1に示す。
The multilayer ceramic capacitor chip was designed to have a length of 3.2 × width of 1.6 × thickness of 1.0 mm and a capacitance of 1 μF. Regarding the electrical characteristics of the obtained multilayer ceramic capacitor, the capacitance (C) was measured using an LCR meter. For joint strength,
Φ1mm on the external electrode terminal using the tensile compression tester
The pin was vertically joined with solder and fixed, and pulled to measure. As a criterion for determination, the capacitance variation is within ± 10%, and the adhesion strength is 1.5 kgf / m at which the external electrodes do not peel off when mounted on the board by soldering.
m 2 or more was regarded as a good product. For the external electrode hole state,
The laminated ceramic capacitor chip was embedded in resin and polished, and then the porosity in the external electrode layer was measured using an image analyzer. Regarding the reliability, a high temperature load test for judging pass / fail by a change in insulation resistance after leaving for 500 hours by applying a voltage four times the rated voltage at a temperature of 125 ° C, a temperature of 85 ° C
And a humidity resistance load test with a humidity of 85% RH was performed. The results are shown in Table 1.

【0030】[0030]

【表1】 [Table 1]

【0031】表1の結果より、第1のCu外部電極層の
空孔率が5%未満の場合、電気特性及び密着強度は良好
であるが、第1のCu外部電極層と積層セラミックコン
デンサチップとの密着が強固であり、空孔率が少ないた
め高温負荷試験において、チップヘのCu焼き付け時の
収縮ストレスとチップの焼成時の内部応力が緩和され
ず、絶縁抵抗劣化による不良発生率が高くなっている。
From the results of Table 1, when the porosity of the first Cu external electrode layer is less than 5%, the electrical characteristics and the adhesion strength are good, but the first Cu external electrode layer and the laminated ceramic capacitor chip are good. In the high temperature load test, the shrinkage stress when Cu is baked on the chip and the internal stress when the chip is baked are not relaxed because the adhesion with the film is strong and the porosity is small, and the failure occurrence rate due to insulation resistance deterioration increases. ing.

【0032】また、第1のCu外部電極層の空孔率が3
1%以上の場合、内部電極層のNiとの電気的接続が確
保されず、電気特性のばらつきが大きくなるとともに、
密着強度も電気特性と同様にばらつきが大きくなり、密
着強度も低くなった。
Further, the porosity of the first Cu external electrode layer is 3
If it is 1% or more, the electrical connection with Ni of the internal electrode layer is not secured, and the variation of the electrical characteristics becomes large, and
Similar to the electrical characteristics, the adhesion strength also varied greatly, and the adhesion strength also decreased.

【0033】比較のために作製した、第2の外部電極層
を形成していないチップ(従来例)については、第1の
外部電極層の空孔率が5〜20%の範囲内でも、めっき
液の浸透によって、耐湿負荷特性が悪くなっていた。
For the chip (conventional example) prepared for comparison, in which the second external electrode layer was not formed, even if the porosity of the first external electrode layer was within the range of 5 to 20%, plating was performed. Due to the permeation of the liquid, the moisture resistance load characteristic was deteriorated.

【0034】本発明の実施の形態における積層セラミッ
クコンデンサの製造方法によって、電気特性及び密着強
度の高い外部電極を形成すると共に、高い信頼性が得ら
れた。
By the method for manufacturing a monolithic ceramic capacitor according to the embodiment of the present invention, an external electrode having high electric characteristics and adhesion strength was formed, and high reliability was obtained.

【0035】以上説明したように、本発明の実施の形態
において、導電ペースト組成としてCu金属粉末とホウ
珪酸亜鉛及びホウ珪酸鉛を除いたガラスフリットと有機
ビヒクルから構成されていることより、チップの鉛フリ
ー化ができるとともに、Snめっきのウィスカ防止及び
Niめっきの応力緩和のための熱処理を不要にすること
ができる。
As described above, in the embodiment of the present invention, the conductive paste composition is composed of Cu metal powder, glass frit excluding zinc borosilicate and lead borosilicate, and an organic vehicle. In addition to being lead-free, heat treatment for preventing whiskers of Sn plating and stress relaxation of Ni plating can be eliminated.

【0036】また、還元雰囲気及び真空雰囲気での焼き
付けにおいて炉温が導電ぺースト内の有機ビヒクル成分
を分解する脱バインダ温度まで、昇温させる第1の昇温
段階と脱バインダを目的とする300〜400℃範囲に
おける一定の温度保持の第1段階を有することによって
外部電極内のバインダが十分に除去できるとともに、第
1の外部電極層の空孔率を制御することによって、電気
的な接続及び密着性が良好で信頼性の高い積層セラミッ
クコンデンサを提供できる。
Further, in baking in a reducing atmosphere and a vacuum atmosphere, the furnace temperature is raised to the binder removal temperature at which the organic vehicle component in the conductive paste is decomposed, and the first temperature raising step and binder removal are aimed at. By having the first step of maintaining a constant temperature in the range of 400 to 400 ° C., the binder in the external electrode can be sufficiently removed, and by controlling the porosity of the first external electrode layer, electrical connection and It is possible to provide a multilayer ceramic capacitor having good adhesion and high reliability.

【0037】[0037]

【発明の効果】以上説明したように、本発明によれば、
焼き付け工程において、誘電体セラミックとの密着性を
低下させず、Cuぺーストの収縮による残留応力を緩和
するとともに、めっき工程においても耐電圧、絶縁性の
劣化及び層間剥離を生じない、外部電極端子を形成する
ことができる積層セラミックコンデンサの製造方法を提
供することができた。
As described above, according to the present invention,
External electrode terminals that do not reduce the adhesion with the dielectric ceramic during the baking process, alleviate the residual stress due to the contraction of the Cu paste, and do not cause deterioration of withstand voltage, insulation and delamination during the plating process. It was possible to provide a method for manufacturing a monolithic ceramic capacitor capable of forming.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明における製造方法により製造した一実施
の形態の積層セラミックコンデンサの断面図。
FIG. 1 is a sectional view of a monolithic ceramic capacitor manufactured by a manufacturing method according to an embodiment of the present invention.

【図2】本発明における製造方法により製造した他の実
施の形態の積層セラミックコンデンサの断面図。
FIG. 2 is a sectional view of a laminated ceramic capacitor of another embodiment manufactured by the manufacturing method of the present invention.

【図3】本発明における外部電極端子焼き付け温度プロ
ファイルを示す図。
FIG. 3 is a diagram showing an external electrode terminal baking temperature profile in the present invention.

【図4】本発明における製造方法により製造した実施の
形態の積層セラミックコンデンサの模式図。
FIG. 4 is a schematic view of a monolithic ceramic capacitor according to an embodiment manufactured by a manufacturing method according to the present invention.

【符号の説明】 1 誘電体セラミック 2 内部電極 3 第1の(Cu)外部電極 4 第2の(Ag)外部電極 5 めっき層 6 第2の(Cu)外部電極 7 空孔 10,20 積層セラミックコンデンサ[Explanation of symbols] 1 Dielectric ceramic 2 internal electrodes 3 First (Cu) external electrode 4 Second (Ag) external electrode 5 plating layer 6 Second (Cu) external electrode 7 holes 10, 20 Multilayer ceramic capacitors

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E082 AB03 BC33 EE04 EE23 EE35 FG26 GG10 GG11 GG28 JJ03 JJ12 JJ23 LL01 MM24 PP10   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5E082 AB03 BC33 EE04 EE23 EE35                       FG26 GG10 GG11 GG28 JJ03                       JJ12 JJ23 LL01 MM24 PP10

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 誘電体セラミック層とNiを主成分とし
た内部電極層とを交互に複数層積み重ねて形成する積層
体に外部電極を設け、該外部電極上にめっきを施した積
層セラミックコンデンサの製造方法において、前記内部
電極層と電気的に接続される第1の外部電極層として、
Cuを主成分とする導電ペーストを還元雰囲気及び真空
雰囲気の内の少なくとも一方の雰囲気で焼き付けた後、
前記第1の外部電極層の上に第2の外部電極層として低
抵抗導電ぺーストのうち少なくとも1種類を前記第1の
外部電極層より低い温度で還元雰囲気及び真空雰囲気の
うち少なくとも一方の雰囲気で焼き付けることを特徴と
する積層セラミックコンデンサの製造方法。
1. A laminated ceramic capacitor having external electrodes provided on a laminate formed by alternately stacking a plurality of dielectric ceramic layers and internal electrode layers containing Ni as a main component, and the external electrodes being plated. In the manufacturing method, as the first external electrode layer electrically connected to the internal electrode layer,
After baking the conductive paste containing Cu as a main component in at least one of a reducing atmosphere and a vacuum atmosphere,
At least one kind of low-resistance conductive paste is used as a second external electrode layer on the first external electrode layer at a temperature lower than that of the first external electrode layer and at least one of a reducing atmosphere and a vacuum atmosphere. A method for manufacturing a monolithic ceramic capacitor, which is characterized by being baked by.
【請求項2】 請求項1記載の積層セラミックコンデン
サの製造方法において、前記内部電極層と前記第1の外
部電極層に用いられる導電ぺーストとして、Cu粉末と
Zn及びPbを含まないガラスフリットと有機ビヒクル
から構成され、前記Cu粉末に粒径が異なる2種類以上
を使用し、還元雰囲気及び真空雰囲気のうち少なくとも
一方の雰囲気で焼き付け、前記第1の外部電極層内の空
孔率を5〜20%とすることを特徴とする積層セラミッ
クコンデンサの製造方法。
2. The method for manufacturing a monolithic ceramic capacitor according to claim 1, wherein the conductive paste used for the internal electrode layer and the first external electrode layer is Cu powder and a glass frit containing no Zn or Pb. Two or more kinds of Cu powders having different particle sizes are used, which are made of an organic vehicle, and baked in at least one of a reducing atmosphere and a vacuum atmosphere, and the porosity in the first external electrode layer is 5 to 5%. 20% of the manufacturing method of the laminated ceramic capacitor.
JP2002015161A 2002-01-24 2002-01-24 Manufacturing method of laminated ceramic capacitor Pending JP2003217969A (en)

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