US20150076566A1 - Semiconductor device and a manufacturing method thereof - Google Patents

Semiconductor device and a manufacturing method thereof Download PDF

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Publication number
US20150076566A1
US20150076566A1 US14/481,977 US201414481977A US2015076566A1 US 20150076566 A1 US20150076566 A1 US 20150076566A1 US 201414481977 A US201414481977 A US 201414481977A US 2015076566 A1 US2015076566 A1 US 2015076566A1
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film
semiconductor region
gate electrode
region
forming
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Takeshi Kamino
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H01L27/14647—Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and is preferably applicable to a semiconductor device including, for example, a solid-state image sensing element, and a manufacturing method thereof.
  • CMOS image sensor As a solid-state image sensing element, a CMOS image sensor using a CMOS (Complementary Metal Oxide Semiconductor) has been under development.
  • the CMOS image sensor includes a plurality of pixels each having a photodiode and a transfer transistor.
  • the photodiode and the transfer transistor are formed in the pixel region of a semiconductor substrate.
  • transistors forming a logic circuit namely, logic transistors.
  • the manufacturing steps of a semiconductor device including a CMOS image sensor as a solid-state image sensing element have a step of doping ions into a semiconductor substrate in order to form a photodiode in a pixel region.
  • a step of doping ions into a semiconductor substrate for example, into a p type well formed on the upper surface side of the semiconductor substrate, for example, n type impurity ions are doped from the upper surface side of the semiconductor substrate, thereby to form an n type well in the inside of the p type well. This results in the formation of a photodiode having a pn junction between the p type well and the n type well.
  • the manufacturing steps of a semiconductor device including a CMOS image sensor have a step of forming silicide layers in the pixel region and a peripheral circuit region.
  • silicide layer formation step after forming the photodiode in the pixel region, in the peripheral circuit region, silicide layers are formed at the upper surface of the gate electrode of a logic transistor and the upper surfaces of the source/drain regions on the opposite sides of the gate electrode.
  • Patent Document 1 discloses the following technology: with the resist pattern left over the gate electrode of a transfer transistor in a pixel region as a mask, ions are doped into a semiconductor substrate, thereby to form a photodiode.
  • Patent Document 1
  • the pn junction of the photodiode is desirably arranged at a position deep from the upper surface of the semiconductor substrate. Therefore, of the p type well and the n type well forming the pn junction of the photodiode, for the n type well formed at the upper layer part of the p type well, the lower surface of the n type well is desirably arranged at a position as deep as possible.
  • the ions when ions are doped in alignment with the gate electrode, the ions may penetrate through the gate electrode, to be doped into a gate insulation film and a semiconductor substrate under the gate electrode. Under such circumstances, in order to prevent or inhibit ions from being doped into the gate insulation film and the semiconductor substrate under the gate electrode, for example, it can be considered that ions are doped with an insulation film formed over the gate electrode.
  • silicide layers are formed at the upper surface of the gate electrode, and the upper surfaces of the source/drain regions. For this reason, after doping ions and forming a photodiode, it is necessary to remove the insulation film over the gate electrode in the peripheral circuit region.
  • an element isolation region or a gate insulation film may be partially removed. Therefore, it is difficult to remove the insulation film over the gate electrode in the peripheral circuit region after forming the photodiode.
  • n type impurity ions cannot be doped to a position deep from the upper surface of the semiconductor substrate in the photodiode forming region.
  • the photodiode is formed at a position shallow from the upper surface of the semiconductor substrate. Accordingly, impurity ions in a p type semiconductor region formed in the vicinity of the upper surface of the semiconductor substrate are diffused into the inside of the photodiode. Then, the number of saturated electrons in the photodiode is reduced, which may reduce the sensitivity of the CMOS image sensor, resulting in the degradation of the performances of the semiconductor device.
  • the photodiode when the photodiode includes therein a large number of crystal defects, the photodiode is determined as being irradiated with a light despite not being irradiated with a light. As a result, erroneous lighting is caused, so that white points are formed.
  • the portion in the vicinity of the upper surface of the semiconductor substrate includes therein a large number of crystal defects. For this reason, the photodiode is formed at a position shallow from the upper surface of the semiconductor substrate. This results in an increase in frequency of the formation of white points with no light applied thereto, namely, the formation of pixel defects. This may degrade the performances of the CMOS image sensor, resulting in the degradation of the performances of the semiconductor device.
  • a semiconductor device has a photodiode and a transfer transistor formed in a pixel region on the upper surface side of a semiconductor substrate. Further, the semiconductor device has a transistor formed in a peripheral circuit region on the upper surface side of the semiconductor substrate.
  • the transfer transistor includes a first gate electrode, and a first film part formed of a thick hard mask film formed over the first gate electrode.
  • the transistor formed in the peripheral circuit region includes a second gate electrode, source/drain regions, and silicide layers formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions. Further, the semiconductor device has an interlayer insulation film formed in such a manner as to cover the transfer transistor.
  • a first film part formed of a thick hard mask film formed over a conductive film is formed; and in a peripheral circuit region on the upper surface side of the semiconductor substrate, a second film part formed of a thin hard mask film formed over the conductive film is formed. Then, by etching the conductive film, the conductive film covered with the first film part is left, thereby to form a first gate electrode, and the conductive film covered with the second film part is left, thereby to form a second gate electrode.
  • an n type well is formed in alignment with the first gate electrode by an ion implantation method, thereby to form a photodiode including the p type well and the n type well.
  • the second film part is removed.
  • a drain region is formed, thereby to form a transfer transistor including the first gate electrode, the drain region, and the first film part.
  • source/drain regions are formed, thereby to form a transistor including the second gate electrode and the source/drain regions.
  • silicide layers are formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions.
  • FIG. 1 is a circuit block diagram showing a configuration example of a semiconductor device of First Embodiment
  • FIG. 2 is a circuit diagram showing a configuration example of a pixel
  • FIG. 3 is a cross sectional view showing the configuration of a semiconductor device of First Embodiment
  • FIG. 4 is a cross sectional view showing the configuration of the semiconductor device of First Embodiment
  • FIG. 5 is a manufacturing process flowchart showing some of the manufacturing steps of the semiconductor device of First Embodiment
  • FIG. 6 is a manufacturing process flowchart showing others of the manufacturing steps of the semiconductor device of First Embodiment
  • FIG. 7 is across sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 8 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 9 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 10 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 11 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 12 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 13 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 14 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 15 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 16 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 17 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 18 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 19 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 20 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 21 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 22 is a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step
  • FIG. 23 is a cross sectional view showing the configuration of a semiconductor device of Comparative Example 1;
  • FIG. 24 is a cross sectional view showing the semiconductor device of Comparative Example 1 during a manufacturing step
  • FIG. 25 is a cross sectional view showing the semiconductor device of Comparative Example 1 during a manufacturing step
  • FIG. 26 is a cross sectional view showing the semiconductor device of Comparative Example 1 during a manufacturing step
  • FIG. 27 is a cross sectional view showing the configuration of a semiconductor device of Second Embodiment.
  • FIG. 28 is a cross sectional view showing the configuration of the semiconductor device of Second Embodiment.
  • FIG. 29 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step
  • FIG. 30 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step
  • FIG. 31 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step
  • FIG. 32 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step
  • FIG. 33 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step
  • FIG. 34 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step
  • FIG. 35 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step
  • FIG. 36 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step
  • FIG. 37 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step.
  • FIG. 38 is a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step.
  • the number of elements is not limited to a specific number, but may be greater than or less than the specific number, unless otherwise specified, or except the case where the number is apparently limited to the specific number in principle.
  • each part does not correspond to that of an actual device.
  • a specific part may be shown on a relatively enlarged scale.
  • FIG. 1 is a circuit block diagram showing a configuration example of a semiconductor device of First Embodiment.
  • FIG. 2 is a circuit diagram showing the configuration example of a pixel.
  • FIG. 1 shows 16 pixels arranged in an array of 4 rows and 4 columns.
  • the semiconductor device of First Embodiment is applied to an electronic device such as a camera, for example, several hundreds of pixels are provided.
  • a plurality of pixels PU are arranged in an array.
  • driving circuits such as a vertical scanning circuit 102 and a horizontal scanning circuit 105 .
  • the semiconductor device of the present First Embodiment has a pixel array including a plurality of pixels PU arranged in an array therein.
  • the semiconductor device of the present First Embodiment has a plurality of pixels PU arranged in an array.
  • Respective pixels PU are arranged at points of intersection of selection lines SL and output lines OL, respectively.
  • the selection lines SL are coupled with the vertical scanning circuit 102
  • the output lines OL are coupled with column circuits 103 , respectively.
  • the column circuits 103 are coupled with an output amplifier 104 via switches Sw, respectively.
  • switches Sw are coupled with the horizontal scanning circuit 105 , and are controlled by the horizontal scanning circuit 105 .
  • an electrical signal read from the pixel PU selected by the vertical scanning circuit 102 and the horizontal scanning circuit 105 is outputted via the output line OL and the output amplifier 104 .
  • the pixel PU includes, for example, as shown in FIG. 2 , a photodiode PD and four MOSFETs.
  • the MOSFETs are of an n channel type.
  • RST is a reset transistor
  • TX is a transfer transistor
  • SEL is a selection transistor
  • AMI is an amplification transistor.
  • the transfer transistor TX transfers electrical charges generated by the photodiode PD.
  • other than these transistors other transistors or elements such as capacitive elements may be incorporated. Further, as the coupling forms of the transistors, various modified examples can be used.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • FET Field Effect Transistor
  • the photodiode PD and the transfer transistor TX are coupled in series between the ground potential GND and a node n 1 .
  • the reset transistor RST is coupled between the node n 1 and a power supply potential VDD.
  • the power supply potential VDD is the electrical potential of a power supply potential line.
  • the selection transistor SEL and the amplification transistor AMI are coupled in series between the power supply potential VDD and the output line OL.
  • the gate electrode of the amplification transistor AMI is coupled with the node n 1 .
  • the gate electrode of the reset transistor RST is coupled with the reset line LRST.
  • the gate electrode of the selection transistor SEL is coupled with the selection line SL
  • the gate electrode of the transfer transistor TX is coupled with the transfer line LTX.
  • the transfer line LTX and the reset line LRST are raised and set at a H level, so that the transfer transistor TX and the reset transistor RST are put in an ON state.
  • the electrical charges in the photodiode PD are extracted, and depleted.
  • the transfer transistor TX is rendered in an OFF state.
  • the shutter such as a mechanical shutter of an electronic device such as a camera is opened.
  • the photodiode PD electrical charges are generated by an incident light, and are accumulated.
  • the photodiode PD receives an incident light, and generates electrical charges.
  • the reset line LRST is lowered, and is set at a L level, so that the reset transistor RST is rendered in an OFF state.
  • the selection line SL and the transfer line LTX are raised, and are set at a H level, so that the selection transistor SEL and the transfer transistor TX are rendered in an ON state.
  • the electrical charges generated by the photodiode PD are transferred to the end on the node n 1 side of the transfer transistor TX (a floating diffusion FD shown in FIG. 3 described later).
  • the signal from the floating diffusion FD namely, the electrical potential thereof changes into a value corresponding to the electrical charges transferred from the photodiode PD.
  • the value of the signal is amplified by the amplification transistor AMI, and is outputted to the output line OL.
  • the signal from the output line OL namely, the electrical potential thereof serves as an electrical signal (light receiving signal), and is read as an output signal from the output amplifier 104 via the column circuit 103 and the switch Sw.
  • FIGS. 3 and 4 are each a cross sectional view showing the configuration of the semiconductor device of First Embodiment. Incidentally, in FIGS. 3 and 4 , the element structure of the pixel region and the element structure of the peripheral circuit region are shown together. Whereas, in FIG. 4 , the portion above the interlayer insulation film IL 1 of FIG. 3 is not shown.
  • the semiconductor device of the present First Embodiment has a semiconductor substrate 1 S, active regions AcTP, AcAS, and AcR which are semiconductor regions formed in the pixel region 1 A formed on the side of the upper surface as the main surface of the semiconductor substrate 1 S, and active regions AcH and AcL which are semiconductor regions formed in the peripheral circuit region 2 A formed on the upper surface side of the semiconductor substrate 1 S.
  • the semiconductor device of the present First Embodiment has, in the pixel region 1 A, the photodiode PD, the transfer transistor TX, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST.
  • the photodiode PD is formed in the active region AcTP, and generates electrical charges by photoelectric conversion.
  • the transfer transistor TX is formed in the active region AcTP, and transfers the electrical charges generated by the photodiode PD.
  • the amplification transistor AMI is formed in the active region AcAS, and amplifies a signal according to the electrical charges transferred by the transfer transistor TX.
  • the selection transistor SEL is formed in the active region AcAS, and selects the pixel PU including the photodiode PD and the transfer transistor TX (see FIGS. 1 and 2 ). In other words, the selection transistor SEL selects the amplification transistor AMI.
  • the reset transistor RST is formed in the active region AcR, and erases the electrical charges in the photodiode PD.
  • the semiconductor device of the present First Embodiment has a transistor LTH and a transistor LTL as logic transistors forming a logic circuit in the peripheral circuit region 2 A.
  • the logic circuit in the peripheral circuit region 2 A includes an n channel type MISFET using electrons as carriers, and a p channel type MISFET using holes as carriers.
  • FIG. 3 as examples thereof, there are shown the transistors LTH and LTL which are n channel type MISFETs of the transistors forming the logic circuit in the peripheral circuit region 2 A.
  • the transistor LTH is formed in the active region AcH, and the transistor LTL is formed in the active region AcL.
  • the driving voltage of the transistor LTH is larger than the driving voltage of the transistor LTL.
  • the driving voltage of the transistor LTH is, for example, 3.3 V, and the driving voltage of the transistor LTL is, for example, 1.5 V.
  • the peripheral circuit region 2 A there are formed a plurality of types of n channel type transistors having different driving voltages.
  • the peripheral circuit region 2 A there may be formed a plurality of types of p channel type transistors having different driving voltages.
  • the semiconductor substrate 1 S is a single crystal silicon containing n type impurities such as phosphorus (P) or arsenic (As).
  • n type impurities such as phosphorus (P) or arsenic (As).
  • element isolation regions LCS At respective outer edges of the active regions AcTP, AcAS, AcR, AcH, and AcL, there are arranged element isolation regions LCS.
  • respective portions surrounded by the element isolation regions LCS on the upper surface side of the semiconductor substrate 1 S serve as active regions such as the active regions AcTP, AcAS, AcR, AcH, and AcL.
  • a p type well PW 1 as a semiconductor region doped with p type impurities such as boron (B).
  • a p type well PW 2 as a semiconductor region doped with p type impurities such as boron (B).
  • a p type well PW 3 as a semiconductor region doped with p type impurities such as boron (B).
  • p type impurities such as boron (B).
  • the p type well PW 1 and the p type well PW 2 are collectively defined as a semiconductor region PW.
  • the p type impurity concentration of each of the p type wells PW 1 , PW 2 , and PW 3 has no particular restriction, and can be set at a given value.
  • the p type impurity concentration in the p type well PW 3 of the active region AcH can be set different from the p type impurity concentration in the p type well PW 3 of the active region AcL.
  • a gate electrode GEt is formed across over the p type well PW 1 to over the p type well PW 2 via a gate insulation film GOX 1 .
  • the gate electrode GEt is a gate electrode of the transfer transistor TX.
  • the photodiode PD In a plan view, on one side of the gate electrode GEt (the left-hand side of FIG. 3 ), there is formed the photodiode PD.
  • the floating diffusion FD having a function as a charge accumulation part or a floating diffusion layer.
  • the photodiode PD includes the p type well PW 1 formed in the active region AcTP, and the n type well NW formed in the inside of the p type well PW 1 . Further, the photodiode PD includes the pn junction between the p type well PW 1 and the n type well NW.
  • a p + type semiconductor region PR In a part of the upper surface of the n type well NW, there is formed a p + type semiconductor region PR.
  • the p + type semiconductor region PR is formed for the purpose of suppressing the generation of electrons based on a large number of interface states formed at the upper surface of the semiconductor substrate 1 S. Namely, at the portion in the vicinity of the upper surface of the semiconductor substrate 1 S, under the influence of the interface states, electrons may be generated even while not being irradiated with light, thereby causing an increase in dark current. For this reason, in the upper surface of the n type well NW using electrons as majority carriers, there is formed the p + type semiconductor region PR using holes as majority carriers.
  • the photodiode PD has the p + type semiconductor region PR formed in a part of the upper surface of the n type well NW.
  • a film part FPt Over the gate electrode GEt, there is formed a film part FPt.
  • the film part FPt includes a film part FPt 1 formed of a thick hard mask HM 1 (see FIG. 13 described later) as an insulation film and sidewalls SWt as sidewall parts each formed of a thin hard mask film HM 2 formed at the side surfaces of the film part FPt 1 (see FIG. 13 described later).
  • the film thickness TH 5 of the hard mask film HM 1 is, for example, about 200 to 300 nm.
  • the film thickness TH 6 of the hard mask film HM 2 is, for example, about 20 nm.
  • each thickness of the film part FPt and the film part FPt 1 is equal to the film thickness TH 5 of the hard mask film HM 1 (see FIG. 13 described later).
  • the width of the sidewall SWt is equal to the film thickness TH 6 of the hard mask film HM 2 (see FIG. 13 described later).
  • the film part FPt there is formed the film part FPt.
  • the impurity ions can be prevented or inhibited from penetrating through the gate electrode GEt, and being doped into the gate insulation film GOX 1 and the p type well PW 1 under the gate electrode GEt.
  • n type ion impurity ions can be doped to a position deep from the upper surface of the p type well PW 1 , so that an n type well NW can be formed at a position deep from the upper surface of the p type well PW 1 .
  • the distance TH 7 from the upper surface of the semiconductor substrate 1 S to the lower surface of the n type well NW, namely, the surface of the semiconductor substrate 1 S opposite to the upper surface side thereof in the n type well NW (see FIG. 15 described later) may be larger than the film thickness TH 4 of the gate electrode GEt (see FIG. 15 described later).
  • the impurity ions when, for example, n type impurity ions are doped in order to form the n type well NW, the impurity ions can be prevented or inhibited from penetrating through the gate electrode GEt, and being doped into the gate insulation film GOX 1 and the p type well PW 1 under the gate electrode GEt.
  • the film thickness TH 4 of the gate electrode GEt is, for example, about 200 nm.
  • the thick hard mask film HM 1 forming the film part FPt there can be used an insulation film which is a monolayer film including one, or a lamination film including two or more of a silicon oxide (SiO 2 ) film, a silicon nitride (SiN) film, and a silicon oxynitride (SiON) film.
  • the film part FPt can be prevented or inhibited from being altered or modified as compared with, for example, the case using a resist film in place of the film part FPt.
  • the thick hard mask film HM 1 forming the film part FPt there can be used a silicon oxide film. As a result, even when the hard mask film HM 1 is thick, patterning can be performed with ease.
  • the thin hard mask film HM 2 forming the film part FPt there can be used an insulation film which is a monolayer film including one, or a lamination film including two or more of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the film part FPt may have a step part STP (see FIG. 18 described later).
  • the film thickness of a portion of the film part FPt opposite to the photodiode PD side thereof from the step part STP is smaller than the film thickness TH 5 of a portion of the film part FPt on the photodiode PD side from the step part STP (see FIG. 13 described later).
  • a cap insulation film CAP is formed across from the upper surface of the p + type semiconductor region PR to the upper surface of the film part FPt.
  • the cap insulation film CAP is formed for keeping favorable the characteristics at the upper surfaces of the n type well NW and the p + type semiconductor region PR.
  • the cap insulation film CAP also functions as an antireflection film ARF.
  • the photodiode PD has the antireflection film ARF formed over the n type well NW and the p + type semiconductor region PR.
  • a sidewall SW formed of an insulation film is formed at the side surface of the gate electrode GEt opposite to the photodiode PD side thereof, and the side surface of the film part FPt opposite to the photodiode PD side thereof.
  • n type high concentration semiconductor region NR doped with n type impurities such as phosphorus (P) or arsenic (As).
  • the n type high concentration semiconductor region NR is a semiconductor region as a floating diffusion FD, and is also a drain region of the transfer transistor TX.
  • the transfer transistor TX includes the gate electrode GEt formed over the active region AcTP, and the n type high concentration semiconductor region NR which is the drain region formed in alignment with the gate electrode GEt in the upper layer part of the active region AcTP.
  • a gate electrode GEa and a gate electrode GEs are formed via gate insulation films GOX 1 , respectively.
  • the gate electrode GEa is the gate electrode of the amplification transistor AMI.
  • the gate electrode GEs is the gate electrode of the selection transistor SEL.
  • Over the gate electrode GEa there is formed a film part FPa, and over the gate electrode GEs, there is formed a film part FPs.
  • the film part FPa includes a film part FPa 1 formed of a thick hard mask film HM 1 (see FIG.
  • the film part FPs includes a film part FPs 1 formed of a thick hard mask film HM 1 (see FIG. 13 described later) as an insulation film and sidewalls SWs as sidewall parts each formed of a thin hard mask film HM 2 formed at the side surfaces of the film part FPa 1 (see FIG. 13 described later).
  • the film part FPs includes a film part FPs 1 formed of a thick hard mask film HM 1 (see FIG. 13 described later) as an insulation film and sidewalls SWs as sidewall parts each formed of a thin hard mask film HM 2 formed at the side surfaces of the film part FPs 1 (see FIG. 13 described later).
  • the hard mask film HM 1 forming the film part FPa 1 is an insulation film formed at the same layer as the hard mask film HM 1 forming the film part FPt 1 (see FIG. 13 described later).
  • the hard mask film HM 2 forming the sidewall SWa is an insulation film formed at the same layer as the hard mask film HM 2 forming the sidewall SWt (see FIG. 13 described later).
  • the hard mask film HM 1 forming the film part FPs 1 is an insulation film formed at the same layer as the hard mask film HM 1 forming the film part FPt (see FIG. 13 described later).
  • the hard mask film HM 2 forming the sidewall SWs is an insulation film formed at the same layer as the hard mask film HM 2 forming the sidewall SWt (see FIG. 13 described later).
  • the source/drain regions SD of the amplification transistor AMI are formed in alignment with the gate electrode GEa.
  • the source/drain regions have a LDD (Lightly Doped Drain) structure, and are each formed of an n type low concentration semiconductor region NM, namely, an n ⁇ type semiconductor region NM, and an n type high concentration semiconductor regions NR, namely, an n + type semiconductor regions NR.
  • a silicide layer SIL formed of a metal silicide layer such as nickel silicide. Namely, in the upper layer part of each n type high concentration semiconductor region NR, there is formed the silicide layer SIL.
  • the source/drain region SD means a semiconductor region which is a source region or a drain region.
  • the source/drain regions SD of the selection transistor SEL are formed in alignment with the gate electrode GEs.
  • the source/drain regions SD have a LDD structure, and are each formed of an n type low concentration semiconductor region NM, and an n type high concentration semiconductor region NR.
  • the selection transistor SEL and the amplification transistor AMI are coupled in series with each other, and hence have one source/drain region SD in common.
  • a gate electrode GEr is formed via a gate insulation film GOX 1 .
  • the gate electrode GEr is the gate electrode of the reset transistor RST.
  • a film part FPr is formed over the gate electrode GEr.
  • the film part FPr includes a film part FPr 1 formed of a thick hard mask film HM 1 (see FIG. 13 described later) as an insulation film and sidewalls SWr as sidewall parts each formed of a thin hard mask film HM 2 formed at the side surfaces of the film part FPr 1 (see FIG. 13 described later).
  • the hard mask film HM 1 forming the film part FPr 1 is an insulation film formed at the same layer as the hard mask film HM 1 forming the film part FPt (see FIG. 13 described later).
  • the hard mask film HM 2 forming the sidewall SWr is an insulation film formed at the same layer as the hard mask film HM 2 forming the sidewall SWt (see FIG. 13 described later).
  • the source/drain regions SD are formed in alignment with the gate electrode GEr.
  • the source/drain regions SD have a LDD structure, and are each formed of an n type low concentration semiconductor region NM, and an n type high concentration semiconductor region NR.
  • a silicide layer SIL formed of a metal silicide layer such as nickel silicide. Namely, in the upper layer part of the n type high concentration semiconductor region NR, there is formed the silicide layer SIL.
  • the amplification transistor AMI has the gate electrode GEa, the source/drain regions SD, the film part FPa, and the silicide layers SIL respectively formed at the upper surfaces of the source/drain regions SD.
  • the selection transistor SEL has the gate electrode GEs, the source/drain regions SD, the film part FPs, and the silicide layers SIL respectively formed at the upper surfaces of the source/drain regions SD.
  • the reset transistor RST has the gate electrode GEr, the source/drain regions SD, the film′part FPr, and the silicide layers SIL respectively formed at the upper surfaces of the source/drain regions SD.
  • a gate electrode GEH is formed via a gate insulation film GOX 2 .
  • the gate electrode GEH is the gate electrode of the transistor LTH.
  • the sidewalls SW formed of an insulation film At the side surfaces on the opposite sides of the gate electrode GEH, there are formed the sidewalls SW formed of an insulation film.
  • a gate electrode GEL is formed via a gate insulation film GOX 3 .
  • the gate electrode GEL is the gate electrode of the transistor LTL.
  • the sidewalls SW formed of an insulation film At the side surfaces on the opposite sides of the gate electrode GEL, there are formed the sidewalls SW formed of an insulation film.
  • the film thickness TH 2 of the gate insulation film GOX 2 is larger than the film thickness TH 3 of the gate insulation film GOX 3 (see FIG. 9 described later).
  • the driving voltage of the transistor LTH can be set larger than the driving voltage of the transistor LTL.
  • the film thickness TH 1 of the gate insulation film GOX 1 can be set equal to, for example, the film thickness TH 2 of the gate insulation film GOX 2 (see FIG. 9 described later).
  • the source/drain regions SD are formed in alignment with the gate electrode GEH.
  • the source/drain regions SD are formed in alignment with the gate electrode GEL.
  • the source/drain regions have a LDD structure, and are each formed of an n type low concentration semiconductor region NM and an n type high concentration semiconductor region NR.
  • the silicide layers SIL each formed of a metal silicide layer such as nickel silicide.
  • the silicide layers SIL there are formed the silicide layers SIL, respectively.
  • the transistor LTH has the gate electrode GEH, the source/drain regions SD, the silicide layer SIL formed at the upper surface of the gate electrode GEH, and the silicide layers SIL formed at the upper surfaces of the source/drain regions SD.
  • the transistor LTL has the gate electrode GEL, the source/drain regions SD, the silicide layer SIL formed at the upper surface of the gate electrode GEL, and the silicide layers SIL formed at the upper surfaces of the source/drain regions SD.
  • a silicide layer SIL may be formed at the upper surface of the n type high concentration semiconductor region NR which is a floating diffusion FD. Namely, at the upper layer part of the n type high concentration semiconductor region NR which is a floating diffusion FD, a silicide layer SIL may be formed at the upper layer part of the n type high concentration semiconductor region NR which is a floating diffusion FD. Alternatively, at the surface of the n type high concentration semiconductor region NR which is a floating diffusion FD, a silicide layer need not be formed.
  • the gate electrode GEt of the transfer transistor TX there is not formed a silicide layer.
  • the distance between the portion of the gate electrode GEt arranged over the p type wells PW 1 and PW 2 and the portion thereof to be coupled with a plug is short, the resistance between the portion of the gate electrode GEt arranged over the p type wells PW 1 and PW 2 and the portion thereof to be coupled with a plug is small. Therefore, even when a silicide layer is not formed at the upper surface of the gate electrode GEt of the transfer transistor TX, the gate electrode GEt and the plug can be coupled at a low resistance.
  • an interlayer insulation film IL 1 is formed in such a manner as to cover the active region AcTP including the transfer transistor TX and the photodiode PD.
  • the interlayer insulation film IL 1 is formed over the film part FPt.
  • the interlayer insulation film IL 1 is formed in such a manner as to cover the active region AcAS including the amplification transistor AMI and the selection transistor SEL.
  • the interlayer insulation film IL 1 is formed over the film part FPa, and over the film part FPs.
  • the interlayer insulation film IL 1 there is formed a plug PGs penetrating through the interlayer insulation film IL 1 , and reaching the n type high concentration semiconductor region NR opposite to the gate electrode GEa across the gate electrode GEs.
  • the interlayer insulation film IL 1 is formed in such a manner as to cover the active region AcR including the reset transistor RST.
  • the interlayer insulation film IL 1 is formed over the film part FPr.
  • plugs PGr penetrating through the interlayer insulation film IL 1 and reaching the n type high concentration semiconductor regions NR on the opposite sides of the gate electrode GEr.
  • FIG. 3 there is shown only the plug PGr reaching the n type high concentration semiconductor region NR on one side of the gate electrode GEr (the right-hand side of FIG. 3 ).
  • an interlayer insulation film IL 1 is formed in such a manner as to cover the active region AcH including the transistor LTH.
  • the silicide layer SIL formed at the upper surface of the gate electrode GEH and the interlayer insulation film IL 1 there is not formed a film part formed of an insulation film formed at the same layer as the hard mask film HM 1 forming the film part FPt (see FIG. 13 described later).
  • the interlayer insulation film IL 1 there are formed plugs PGH penetrating through the interlayer insulation film IL 1 , and reaching the n type high concentration semiconductor regions NR on the opposite sides of the gate electrode GEH.
  • FIG. 3 there is shown only the plug PGH reaching the n type high concentration semiconductor region NR on one side of the gate electrode GEH (the right-hand side of FIG. 3 ).
  • an interlayer insulation film IL 1 is formed in such a manner as to cover the active region AcL including the transistor LTL.
  • the silicide layer SIL formed at the upper surface of the gate electrode GEL and the interlayer insulation film IL 1 there is not formed a film part formed of an insulation film formed at the same layer as the hard mask film HM 1 forming the film part FPt (see FIG. 13 described later).
  • the interlayer insulation film IL 1 there are formed plugs PGL penetrating through the interlayer insulation film IL 1 , and reaching the n type high concentration semiconductor regions NR on the opposite sides of the gate electrode GEL.
  • FIG. 3 there is shown only the plug PGL reaching the n type high concentration semiconductor region NR on one side of the gate electrode GEL (the right-hand side of FIG. 3 ).
  • the interlayer insulation film IL 1 is formed of a silicon oxide (SiO 2 ) film using, for example, TEOS (Tetra Ethyl Ortho Silicate) as a raw material.
  • TEOS Tetra Ethyl Ortho Silicate
  • contact holes CHt, CHa, CHs, CHr, CHH, and CHL there are embedded a barrier conductor film formed of, for example, a titanium film and a titanium nitride film formed over the titanium film, and a main conductor film formed of a tungsten film formed over the barrier conductor film.
  • the plugs, PGt, PGa, PGs, PGr, PGH, and PGL are respectively formed.
  • an interlayer insulation film IL 2 is formed in the pixel region 1 A and the peripheral circuit region 2 A.
  • an interlayer insulation film IL 2 is formed in the interlayer insulation film IL 2 .
  • the interlayer insulation film IL 2 there is formed a wire M 1 .
  • the plugs PGt, PGa, PGs, PGr, PGH, and PGL are coupled with the wire M 1 .
  • the interlayer insulation film IL 2 is formed of, for example, a lamination film of a silicon nitride (SiN) film and a silicon oxide (SiO 2 ) film, but is not limited thereto, and can also be formed of, for example, a low dielectric constant film lower in dielectric constant than the silicon oxide film. Examples of the low dielectric constant film may include a carbon-containing silicon oxide (SiOC) film.
  • the wire M 1 is formed of, for example, a copper wire, and can be formed by, for example, a damascene method. Incidentally, the wire M 1 is not limited to a copper wire, and can also be formed of an aluminum wire.
  • an interlayer insulation film IL 3 formed of, for example, a silicon oxide film or a low dielectric constant film.
  • a wire M 2 In the interlayer insulation film IL 3 , there is formed a wire M 2 .
  • an interlayer insulation film IL 4 is formed in the interlayer insulation film IL 4 .
  • a wire M 3 In the interlayer insulation film IL 4 , there is formed a wire M 3 .
  • the wires M 1 to M 3 form a wiring layer.
  • the plugs PGt, PGa, PGs, PGr, PGH, and PGL are coupled by the wiring layer formed of the wires M 1 to M 3 . As a result, it is possible to form the circuit shown in FIGS. 1 and 2 .
  • the wires M 1 to M 3 are formed so as not to overlap the photodiode in a plan view. This is for preventing a light incident upon the photodiode from being blocked by the wires M 1 to M 3 .
  • a microlens ML in the pixel region 1 A, over the interlayer insulation film IL 4 including the wire M 3 formed therein, there is mounted a microlens ML.
  • a passivation film PF and a color filter CL may be formed sequentially from the semiconductor substrate 1 S side.
  • the passivation film PF in the pixel region 1 A, there may be provided the passivation film PF.
  • the incident light passes through the microlens ML. Then, the light passes through the interlayer insulation films IL 4 to IL 1 transparent to a visible light, and then, is made incident upon the antireflection film ARF. At the antireflection film ARF, the reflection of the incident light is suppressed, so that a sufficient light quantity of incident light is made incident upon the photodiode PD. In the photodiode PD, the energy of the incident light is larger than the bandgap of silicon. For this reason, the incident light is absorbed by photoelectric conversion, resulting in the formation of hole electron pairs. The electrons formed at this step are accumulated in the n type well NW.
  • the transfer transistor TX is turned ON. Specifically, the gate electrode GEt of the transfer transistor TX is applied with a voltage equal to, or larger than the threshold voltage. Then, in the portions of the p type well PW 1 and PW 2 under the gate insulation film GOX 1 , there is formed a channel region. This results in an electrical conduction between the n type well NW which is the source region of the transfer transistor TX and the n type high concentration semiconductor region NR which is the drain region of the transfer transistor TX. As a result, the electrons accumulated in the n type well NW pass through the channel region, reaches the drain region, and are extracted from the drain region to the outside through the wiring layer.
  • FIGS. 5 and 6 are each a manufacturing process flowchart showing some of the manufacturing steps of the semiconductor device of First Embodiment.
  • FIGS. 7 to 22 are each a cross sectional view showing the semiconductor device of First Embodiment during a manufacturing step. Incidentally, in FIGS. 7 to 22 , the manufacturing steps in the pixel region 1 A and the manufacturing steps in the peripheral circuit region 2 A are shown together.
  • a semiconductor substrate 1 S is provided (Step S 11 of FIG. 5 ).
  • the semiconductor substrate 1 S there is provided an n type single crystal silicon substrate containing n type impurities such as phosphorus (P) or arsenic (As).
  • the element isolation region LCS is formed of a thermal oxide film.
  • regions to be active regions such as the active regions AcTP, AcAS, AcR, AcH, and AcL are covered with a silicon nitride (SiN) film, and are thermally oxidized, thereby to form element isolation regions LCS each formed of an insulation member such as a silicon oxide (SiO 2 ) film.
  • Such an element isolation method is referred to as a LOCOS (Local oxidation of silicon) method.
  • the element isolation regions LCS define, namely, form the active regions such as the active regions AcTP, AcAS, AcR, AcH, and AcL.
  • the active regions AcTP, AcAS, and AcR are formed in the pixel region 1 A, and the active regions AcH and AcL are formed in the peripheral circuit region 2 A.
  • the element isolation regions may be formed by using the STI (Shallow Trench Isolation) method in place of the LOCOS method.
  • the element isolation region is formed of an insulation member embedded in the trench in the semiconductor substrate 1 S.
  • the semiconductor substrate 1 S is etched, thereby to form an isolation trench.
  • an insulation film such as a silicon oxynitride film is embedded in the inside of the isolation trench, thereby to form an element isolation region.
  • Step S 12 in the pixel region 1 A, in one portion (the portion on the left-hand side of FIG. 8 ) of the active region AcTP, there is formed the p type well PW 1 .
  • Step S 12 in the pixel region 1 A, in the other portion (the portion on the right-hand side of FIG. 8 ) of the active region AcTP, and the active regions AcAS and AcR, there is formed the p type well PW 2 .
  • Step S 12 in the peripheral circuit region 2 A, in the active regions AcH and AcL, there is formed the p type well PW 3 .
  • the p type impurity concentration in each of the p type wells PW 1 , PW 2 , and PW 3 has no particular restriction, and can be set at a given value. Further, the p type impurity concentration in the p type well PW 3 of the active region AcH can be set different from the p type impurity concentration in the p type well PW 3 of the active region AcL.
  • Step S 13 of FIG. 5 the gate insulation films GOX 1 , GOX 2 , and GOX 3 , and a conductive film CF 1 are formed (Step S 13 of FIG. 5 ).
  • the semiconductor substrate 1 S is thermally oxidized.
  • a gate insulation film GOX 1 formed of a silicon oxide (SiO 2 ) film, and having a film thickness TH 1 .
  • the semiconductor substrate 1 S is thermally oxidized.
  • the peripheral circuit region 2 A at the upper surface of the p type well PW 3 in the active region AcH, there is formed a gate insulation film GOX 2 formed of a silicon oxide film, and having a film thickness TH 2 . Further, the semiconductor substrate 1 S is thermally oxidized. As a result, in the peripheral circuit region 2 A, at the upper surface of the p type well PW 3 in the active region AcL, there is formed a gate insulation film GOX 3 formed of a silicon oxide film, and having a film thickness TH 3 .
  • the film thickness TH 2 of the gate insulation film GOX 2 is larger than the film thickness TH 3 of the gate insulation film GOX 3 .
  • the driving voltage of transistor LTH (see FIG. 19 described later) can be set larger than the driving voltage of the transistor LTL (see FIG. 19 described later).
  • the gate insulation films GOX 1 , GOX 2 , and GOX 3 there may be used silicon nitride (SiN) films, silicon oxynitride (SiON) films, or the like.
  • silicon nitride (SiN) films silicon nitride (SiON) films, or the like.
  • high dielectric constant films such as hafnium type insulation films obtained by doping a hafnium oxide (HfO 2 ) film with lanthanum oxide (La 2 O 3 ), namely, films higher in dielectric constant than a silicon nitride film.
  • the films can be formed using, for example, a CVD (Chemical Vapor Deposition) method.
  • a conductive film CF 1 for example, a polycrystal silicon film is formed using a CVD method or the like.
  • Step S 14 of FIG. 5 there is formed a thick hard mask film HM 1 (Step S 14 of FIG. 5 ).
  • the hard mask film HM 1 as an insulation film is formed by, for example, a CVD method.
  • the thickness TH 5 of the hard mask film HM 1 is larger than the film thickness TH 6 of the hard mask film HM 2 (see FIG. 12 described later).
  • the hard mask film HM 1 there can be formed an insulation film which is a monolayer film formed of one, or a lamination film formed of two or more of a silicon oxide (SiO 2 ) film, a silicon nitride (SiN) film, and a silicon oxynitride (SiON) film.
  • a silicon oxide (SiO 2 ) film a silicon oxide (SiO 2 ) film
  • SiN silicon nitride
  • SiON silicon oxynitride
  • a silicon oxide film can be formed. As a result, even when the hard mask film HM 1 is thick, the hard mask film HM 1 can be patterned with ease.
  • the thick hard mask film HM 1 is patterned (Step S 15 of FIG. 5 ).
  • the thick hard mask film HM 1 is patterned in the pixel region 1 A.
  • the film parts FPt 1 , FPa 1 , FPs 1 , and FPr 1 each formed of the thick hard mask film HM 1 are formed, and in the peripheral circuit region 2 A, the thick hard mask film HM 1 is removed.
  • a photoresist film (not shown) is formed, and is subjected to exposure and development treatments using a photolithography technology.
  • the photoresist film is also referred to as a resist film.
  • the photoresist film is not left.
  • the photoresist film is left in regions in which the film parts FPt 1 , FPa 1 , FPs 1 , and FPr 1 are formed.
  • the thick hard mask film HM 1 is etched.
  • the thick hard mask film HM 1 is left, thereby to form the film part FPt 1 .
  • the thick hard mask film HM 1 is left, thereby to form the film parts FPa 1 and FPs 1 .
  • the thick hard mask film HM 1 is left, thereby to form the film part FPr 1 .
  • the photoresist film is removed by ashing or the like. Such a step from the formation to the removal of the photoresist film is referred to as patterning.
  • the film part FPt 1 is formed continuously from over the p type well PW 1 to over the p type well PW 2 in the active region AcTP.
  • a thin hard mask film HM 2 is formed (Step S 16 of FIG. 5 ).
  • the hard mask film HM 2 as an insulation film is formed by, for example, a CVD method.
  • the film thickness TH 6 of the hard mask film HM 2 is smaller than the film thickness TH 5 of the hard mask film HM 1 .
  • the hard mask film HM 2 there can be formed an insulation film which is a monolayer film formed of one, or a lamination film formed of two or more of a silicon oxide (SiO 2 ) film, a silicon nitride (SiN) film, and a silicon oxynitride (SiON) film.
  • the film thickness TH 5 of the hard mask film HM 1 is, for example, about 200 to 300 nm
  • the film thickness TH 6 of the hard mask film HM 2 is, for example, about 20 nm.
  • the thin hard mask film HM 2 is patterned (Step S 17 of FIG. 5 ).
  • the thin hard mask film HM 2 is patterned, thereby to form the film parts FPH and FPL formed of the thin hard mask film HM 2 .
  • the photoresist film (not shown) is formed, and is subjected to exposure and development treatments using a photolithography technology. As a result, in the pixel region 1 A, the photoresist film is not left. However, in the peripheral circuit region 2 A, the photoresist film is left in regions in which the film parts FPH and FPL are formed. Then, using the photoresist film as a mask, the thin hard mask film HM 2 is etched. As a result, in the peripheral circuit region 2 A, over the conductive film CF 1 , the thin hard mask film HM 2 is left, thereby to form the film parts FPH and FPL.
  • the thin hard mask film HM 2 is etched back.
  • the thin hard mask film HM 2 is left, thereby to form sidewalls SWt.
  • the conductive film CF 1 there is formed a film part FPt formed of the film part FPt 1 and the sidewalls SWt.
  • the thin hard mask film HM 2 is left, thereby to form sidewalls SWr.
  • the conductive film CF 1 there is formed a film part FPr formed of the film part FPr 1 and the sidewalls SWr.
  • the film part FPt is formed continuously from over the p type well PW 1 to over the p type well PW 2 .
  • the gate electrodes GEt, GEa, GEs, GEr, GEH, and GEL are formed (Step S 18 of FIG. 5 ).
  • the Step S 18 in the pixel region 1 A, the gate electrodes GEt, GEa, GEs, and GEr are formed.
  • the gate electrodes GEH and GEL are formed in the peripheral circuit region 2 A.
  • the conductive film CF 1 is etched.
  • the gate insulation films GOX 1 , GOX 2 , and GOX 3 are etched.
  • the portions of the conductive film CF 1 and the gate insulation film GOX 1 not covered with any of the film parts FPt, FPa, FPs, and FPr are removed.
  • the portions of the conductive film CF 1 and the gate insulation film GOX 1 covered with the film part FPt are left.
  • the gate electrode GEt formed of the conductive film CF 1 is formed via the gate insulation film GOX 1 .
  • the portions of the conductive film CF 1 and the gate insulation film GOX 1 covered with the film part FPa are left.
  • the gate electrode GEa formed of the conductive film CF 1 is formed via the gate insulation film GOX 1 .
  • the portions of the conductive film CF 1 and the gate insulation film GOX 1 covered with the film part FPs are left.
  • the gate electrode GEs formed of the conductive film CF 1 is formed via the gate insulation film GOX 1 .
  • the portions of the conductive film CF 1 and the gate insulation film GOX 1 covered with the film part FPr are left.
  • the gate electrode GEr formed of the conductive film CF 1 is formed via the gate insulation film GOX 1 .
  • the portions of the conductive film CF 1 , and the gate insulation films GOX 2 and GOX 3 not covered with any of the film parts FPH and FPL are removed.
  • the portions of the conductive film CF 1 and the gate insulation film GOX 2 covered with the film part FPH are left.
  • the gate electrode GEH formed of the conductive film CF 1 is formed via the gate insulation film GOX 2 .
  • the portions of the conductive film CF 1 and the gate insulation film GOX 3 covered with the film part FPL are left.
  • the gate electrode GEL formed of the conductive film CF 1 is formed via the gate insulation film GOX 3 .
  • the gate electrode GEt is formed continuously from over the p type well PW 1 to over the p type well PW 2 .
  • the n type well NW is formed (Step S 19 of FIG. 5 ).
  • the n type well NW is formed by an ion implantation method.
  • a photoresist film R 1 is formed, and is subjected to exposure and development treatments using a photolithography technology.
  • an opening OP 1 penetrating through the photoresist film R 1 and reaching a portion arranged on one side (the left-hand side of FIG. 15 ) of the gate electrode GEt, namely, the p type well PW 1 in the active region AcTP.
  • the p type well PW 1 which is the portion of the active region AcTP in which the n type well NW is formed is exposed at the bottom of the opening OP 1 .
  • the p type well PW 2 which is the portion of the active region AcTP in which the n type well NW is not formed, and the p type well PW 2 of the active regions AcAS and AcR are covered with the photoresist film R 1 so as to be prevented from being doped with n type impurity ions.
  • the p type well PW 3 of the active regions AcH and AcL is covered with the photoresist film R 1 so as not be doped with n type impurity ions.
  • n type impurity ions IM 1 are doped using the photoresist film R 1 including the opening OP 1 formed therein as a mask.
  • n type impurity ions IM 1 are doped into the upper layer part of the p type well PW 1 , thereby to form the n type well NW.
  • the n type well NW in the inside of the p type well PW 1 , there is formed the n type well NW.
  • the pn junction between the p type well PW 1 and the n type well NW forms the photodiode PD.
  • the direction in which the n type impurity ions IM 1 are exposed is tilted at an angle ⁇ 1 with respect to the normal direction to the main surface of the semiconductor substrate 1 S so that the n type impurity ions IM 1 are exposed to the side surface on the photodiode PD side of the gate electrode GEt.
  • the angle ⁇ 1 is, for example, about 30°.
  • the n type impurity ions IM 1 may be doped twice by vertical ion implantation and oblique ion implantation by an angle ⁇ 1.
  • the angle for the vertical ion implantation is preferably in the range of 0° to 7°.
  • the impurity ions IM 1 are doped in a direction tilted in the normal direction to the main surface of the semiconductor substrate 1 S so that the n type impurity ions IM 1 are applied to the side surface on the photodiode PD side of the gate electrode GEt.
  • the n type well NW can be formed in such a manner as to overlap the gate electrode GEt in a plan view.
  • a part of the n type well NW and the gate electrode GEt overlap each other in a plan view. This allows the n type well NW to also function as the source region of the transfer transistor TX (see FIG. 19 described later).
  • the distance TH 7 from the upper surface of the semiconductor substrate 1 S to the lower surface of the n type well NW may be larger than the film thickness TH 4 of the gate electrode GEt.
  • the impurity ions when, for example, n type impurity ions are doped in order to form the n type well NW, the impurity ions can be prevented or inhibited from penetrating through the gate electrode GEt, and being doped into the gate insulation film GOX 1 and the p type well PW 1 under the gate electrode GEt.
  • the film thickness TH 4 of the gate electrode GEt is, for example, about 200 nm.
  • the opening OP 1 is formed in consideration of the alignment precision for exposure so that the portion of the p type well PW 1 adjacent to the gate electrode GEt is exposed at the bottom of the opening OP 1 with reliability in a plan view.
  • the opening OP 1 is formed in such a manner as to penetrate through the photoresist film R 1 , and to reach the end on one side (the left-hand side of FIG. 15 ) of the film part FPt.
  • n type impurity ions can be doped with reliability to form the n type well NW.
  • a photoresist film R 2 is formed, and is subjected to exposure and development treatments using a photolithography technology.
  • an opening OP 2 penetrating through the photoresist film R 2 and reaching the n type well NW in the active region AcTP.
  • the n type well NW which is the portion of the active region AcTP in which the p + type semiconductor region PR is formed is exposed at the bottom of the opening OP 2 .
  • the p type well PW 2 which is the portion of the active region AcTP in which the p + type semiconductor region PR is not formed, and the p type well PW 2 in the active regions AcAS and AcR are covered with the photoresist film R 2 so as not to be doped with p type impurity ions.
  • the p type well PW 3 in the active regions AcH and AcL is covered with the photoresist film R 2 so as not be doped with p type impurity ions.
  • p type impurity ions IM 2 are doped.
  • the upper layer part of the n type well NW is doped with the p type impurity ions IM 2 , thereby to form the p + type semiconductor region PR.
  • the direction in which the p type impurity ions IM 2 are exposed is tilted at an angle ⁇ 2 with respect to the normal direction to the upper surface of the semiconductor substrate 1 S so as to prevent n type impurity ions from being applied to the side surface on the photodiode PD side of the gate electrode GEt.
  • the angle ⁇ 2 is, for example, about 10 to 30°.
  • the portion of the upper layer part of the n type well NW away from the gate electrode GEt is doped with p type impurity ions. Therefore, the p + type semiconductor region PR is formed in the portion of the upper layer part of the n type well NW away from the gate electrode GEt.
  • the photoresist film R 2 there may be used the photoresist film R 1 (see FIG. 15 ) as it is.
  • Step S 21 of FIG. 6 n type low concentration semiconductor regions NM are formed (Step S 21 of FIG. 6 ).
  • Step S 21 in the pixel region 1 A, in the active region AcAS, in the portions of the p type well PW 2 on the opposite sides of the gate electrode GEa, and the portions of the p type well PW 2 on the opposite sides of the gate electrode GEs, there are formed n type low concentration semiconductor regions NM.
  • n type low concentration semiconductor regions NM in the pixel region 1 A, in the active region AcR, in the portions of the p type well PW 2 on the opposite sides of the gate electrode GEr, there are formed n type low concentration semiconductor regions NM.
  • n type low concentration semiconductor regions NM in the peripheral circuit region 2 A, in the active region AcH, in the portions of the p type well PW 3 on the opposite sides of the gate electrode GEH, there are formed n type low concentration semiconductor regions NM. In the active region AcL, in the portions of the p type well PW 3 on the opposite sides of the gate electrode GEL, there are formed n type low concentration semiconductor regions NM.
  • the photoresist film R 3 is formed, and is subjected to exposure and development treatments using a photolithography technology.
  • the photoresist film R 3 is patterned so that the gate electrodes GEa, GEs, and GEr, and the p type well PW 2 are exposed.
  • the photoresist film R 3 is patterned so that the gate electrodes GEH and GEL, and the p type well PW 3 are exposed.
  • the n type well NW and the p + type semiconductor region PR are covered with the photoresist film R 3 so as not to be doped with n type impurity ions.
  • n type impurity ions are doped.
  • the pixel region 1 A in the portions of the p type well PW 2 on respective opposite sides of the gate electrodes GEa, GEs and GEr, there are formed n type low concentration semiconductor regions NM, respectively.
  • the peripheral circuit region 2 A in the portions of the p type well PW 3 on respective opposite sides of the gate electrodes GEH and GEL, there are formed n type low concentration semiconductor regions NM, respectively.
  • the n type low concentration semiconductor region NM In the exposed portion of the p type well PW 2 , there may be formed the n type low concentration semiconductor region NM.
  • Step S 21 the following procedure is also acceptable: first, in the active regions AcAS, AcR, and AcH, under given conditions, n type impurity ions are doped to form n type low concentration semiconductor regions NM; then, in the active region AcL, under other conditions, n type impurity ions are doped to form n type low concentration semiconductor regions NM.
  • p type impurity ions such as boron (B) may be doped, thereby to form p type low concentration semiconductor regions.
  • the cap insulation film CAP is formed and patterned (Step S 22 of FIG. 6 ).
  • an insulation film CAP 1 which is a monolayer film formed of one, or a lamination film formed of two or more of a silicon oxide (SiO 2 ) film, a silicon nitride (SiN) film, and a silicon oxynitride (SiON) film is formed using, for example, a CVD method.
  • the insulation film CAP 1 is patterned.
  • a photoresist film R 4 is formed, and is subjected to exposure and development treatments using a photolithography technology.
  • the portions of the photoresist film R 4 over the film part FPt, over the n type well NW, and over the p + type semiconductor region PR are left, and other portions of the photoresist film R 4 are removed.
  • the insulation film CAP 1 over each of the active regions AcAS and AcR is anisotropically etched by a RIE (Reactive Ion Etching) method or the like. Further, in the peripheral circuit region 2 A, the insulation film CAP 1 over each of the active regions AcH and AcL is anisotropically etched by a RIE method or the like.
  • the insulation film CAP 1 is left, thereby to form a cap insulation film CAP.
  • the cap insulation film CAP functions as the antireflection film ARF.
  • the insulation film CAP 1 is etched back, so that the film parts FPH and FPL are exposed. Further, the exposed film parts FPH and FPL are removed. Then, at each side surface of the gate electrodes GEH and GEL, the insulation film CAP 1 is left, thereby to form a sidewall SW. Namely, the sidewall SW is formed of the insulation film CAP 1 .
  • the insulation film CAP 1 is etched back, so that the film parts FPa, FPs, and FPr are exposed.
  • the film thickness TH 5 of the film parts FPa, FPs, and FPr is larger than the film thickness TH 6 of the film parts FPH and FPL (see FIG. 13 ). Therefore, even when the film parts FPa, FPs, and FPr are etched back until the film parts FPH and FPL are removed, the film parts FPa, FPs, and FPr can be left without being fully removed.
  • the insulation films CAP 1 are left, thereby to form sidewalls SW, respectively. Further, at the side surfaces of the gate electrode GEs, and the side surfaces of the left film part FPs, the insulation films CAP 1 are left, thereby to form sidewalls SW. Further, at the side surfaces of the gate electrode GEr, and the side surfaces of the left film part FPr, the insulation films CAP 1 are left, thereby to form sidewalls SW.
  • the photoresist film R 4 over the end of the film part FPt opposite to the photodiode PD side thereof is removed so that, in a plan view, the portion of the p type well PW 2 adjacent to the gate electrode GEt is exposed with reliability.
  • the insulation film CAP 1 is etched back, so that the end of the film part FPt opposite to the photodiode PD side thereof is exposed.
  • the end of the film part FPt opposite to the photodiode PD side thereof is etched back until the film parts FPH and FPL are removed, the end of the film part FPt opposite to the photodiode PD side thereof can be left without being fully removed.
  • the insulation films CAP 1 are left, thereby to form sidewalls SW, respectively.
  • the film part FPt may have a step part STP.
  • the film thickness of the portion of the film part FPt opposite to the photodiode PD side thereof from the step part STP is smaller than the film thickness TH 5 of the portion of the film part FPt on the photodiode PD side from the step part STP (see FIG. 13 ).
  • n type high concentration semiconductor regions NR are formed (Step S 23 of FIG. 6 ).
  • Step S 23 in the pixel region 1 A, in the active region AcTP, using the cap insulation film CAP as the antireflection film ARF, and the gate electrode GEt as a mask, n type impurity ions such as phosphorus (P) or arsenic (As) are doped.
  • n type impurity ions such as phosphorus (P) or arsenic (As) are doped.
  • P phosphorus
  • As arsenic
  • the n type high concentration semiconductor region NR is also a semiconductor region which is the drain region of the transfer transistor TX, and serves as a floating diffusion FD. Namely, there is formed the transfer transistor TX including the gate electrode GEt, the n type high concentration semiconductor region NR which is the drain region, and the film part FPt.
  • Step S 23 in the pixel region 1 A, in the active region AcAS, using the gate electrode GEa, and the sidewalls SW formed at the side surfaces on the opposite sides of the gate electrode GEa as a mask, n type impurity ions are doped.
  • n type high concentration semiconductor regions NR there are formed in the portions of the p type well PW 2 on the opposite sides of the combined body formed of the gate electrode GEa, and the sidewalls SW formed at the side surfaces on the opposite sides of the gate electrode GEa.
  • the amplification transistor AMI including the gate electrode GEa, the n type high concentration semiconductor regions NR which are source/drain regions SD, and the film part FPa.
  • n type impurity ions are doped.
  • the portions of the p type well PW 2 on the opposite sides of the combined body formed of the gate electrode GEs, and the sidewalls SW formed at the side surfaces on the opposite sides of the gate electrode GEs there are formed n type high concentration semiconductor regions NR, respectively.
  • the selection transistor SEL including the gate electrode GEs, the n type high concentration semiconductor regions NR which are source/drain regions SD, and the film part FPs.
  • n type impurity ions are doped.
  • the active region AcR in the portions of the p type well PW 2 on the opposite sides of the combined body formed of the gate electrode GEr, and the sidewalls SW formed at the side surfaces on the opposite sides of the gate electrode GEr, there are formed n type high concentration semiconductor regions NR, respectively.
  • the reset transistor RST including the gate electrode GEr, the n type high concentration semiconductor regions NR which are source/drain regions SD, and the film part FPr.
  • Step S 23 in the peripheral circuit region 2 A, in the active region AcH, using the gate electrode GEH, and the sidewalls SW formed at the side surfaces on the opposite sides of the gate electrode GEH as a mask, n type impurity ions are doped.
  • n type high concentration semiconductor regions NR in the portions of the p type well PW 3 on the opposite sides of the combined body formed of the gate electrode GEH, and the sidewalls SW formed at the side surfaces on the opposite sides of the gate electrode GEH, there are formed n type high concentration semiconductor regions NR, respectively.
  • n type impurity ions are doped.
  • the portions of the p type well PW 3 on the opposite sides of the combined body formed of the gate electrode GEL, and the sidewalls SW formed at the side surfaces on the opposite sides of the gate electrode GEL there are formed n type high concentration semiconductor regions NR, respectively.
  • the transistor LTL including the gate electrode GEL, and the n type high concentration semiconductor regions NR which are source/drain regions SD there is formed.
  • p type impurity ions such as boron (B) may be doped, thereby to form p type high concentration semiconductor regions serving as the source/drain regions of the p channel type MISFET.
  • the order of doping of respective impurities is not restricted by the order of the steps. Further, a plurality of the same conductivity type semiconductor regions can be doped with impurities at the same time in one step, so that the doping steps of respective impurities can be adjusted. Incidentally, also after activation annealing, the p + type semiconductor region PR is formed in the portion of the upper layer part of the n type well NW apart from the gate electrode GEt.
  • silicide layers SIL are formed (Step S 24 of FIG. 6 ).
  • a silicide blocking film (not shown).
  • the regions in each of which the silicide layer SIL is formed such as the gate electrodes GEH and GLH, and the n type high concentration semiconductor regions NR, a silicide blocking film (not shown) is not formed over the semiconductor substrate 1 S.
  • a metal film (not shown) formed of, for example, a nickel (Ni) film is formed using a sputtering method or the like.
  • a metal film such as a titanium (Ti) film, a cobalt (Co) film, or a platinum (Pt) film, and an alloy film formed of the metals,
  • the semiconductor substrate 1 S is subjected to a heat treatment, thereby to effect the reaction between the metal film (not shown), and silicon forming the gate electrodes GEH and GLH, and silicon forming the n type high concentration semiconductor regions NR.
  • the unreacted portions of the metal film (not shown) are removed.
  • a silicide layer is not formed in the pixel region 1 A.
  • silicide layer SIL in the active region AcTP, at the upper surface of the n type high concentration semiconductor region NR, there is formed a silicide layer SIL, and in the active regions AcAS and AcR, at each upper surface of the n type high concentration semiconductor regions NR, a silicide layer SIL is formed.
  • a silicide layer SIL in the peripheral circuit region 2 A, in the active regions AcH and AcL, at each upper surface of the n type high concentration semiconductor regions NR, and each upper surface of the gate electrodes GEH and GEL, there is formed a silicide layer SIL.
  • the silicide layers can reduce the coupling resistance between respective regions and plugs.
  • the silicide layer SIL need not be formed at the upper surface of the n type high concentration semiconductor region NR which is the drain region of the transfer transistor TX.
  • a silicide blocking film (not shown) is also formed at the upper surface of the n type high concentration semiconductor region NR which is the drain region of the transfer transistor TX.
  • an interlayer insulation film IL 1 is formed (Step S 25 of FIG. 6 ).
  • the interlayer insulation film IL 1 is formed in such a manner as to cover the photodiode PD, the transfer transistor TX, the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST, and the transistors LTH and LTL.
  • a silicon oxide film is deposited by a CVD method using a TEOS gas as a raw material gas. Thereafter, if required, the upper surface of the interlayer insulation film IL 1 is planarized using a CMP (Chemical Mechanical Polishing) method or the like.
  • CMP Chemical Mechanical Polishing
  • Step S 26 of FIG. 6 the interlayer insulation film IL 1 is patterned, thereby to form the contact holes CHt, CHa, CHs, CHr, CHH, and CHL.
  • n type high concentration semiconductor region NR of the transfer transistor TX there is formed the contact hole CHt penetrating through the interlayer insulation film IL 1 , and reaching the n type high concentration semiconductor region NR.
  • the contact hole CHa penetrating through the interlayer insulation film IL 1 there is formed the contact hole CHa penetrating through the interlayer insulation film IL 1 , and reaching the silicide layer SIL formed at the upper surface of the n type high concentration semiconductor region NR.
  • the contact hole CHs penetrating through the interlayer insulation film IL 1 there is formed the contact hole CHs penetrating through the interlayer insulation film IL 1 , and reaching the silicide layer SIL formed at the upper surface of the n type high concentration semiconductor region NR.
  • n type high concentration semiconductor region NR of the transistor LTH Over the n type high concentration semiconductor region NR of the transistor LTH, there is formed the contact hole CHH penetrating through the interlayer insulation film IL 1 , and reaching the silicide layer SIL formed at the upper surface of the n type high concentration semiconductor region NR. Over the n type high concentration semiconductor region NR of the transistor LTL, there is formed the contact hole CHL penetrating through the interlayer insulation film IL 1 , and reaching the silicide layer SIL formed at the upper surface of the n type high concentration semiconductor region NR. At this step, also over the gate electrodes GEt, GEa, GEs, GEr, GEH, and GEL, there are formed contact holes (not shown).
  • Step S 27 of FIG. 6 plugs PGt, PGa, PGs, PGr, PGH, and PGL are formed (Step S 27 of FIG. 6 ).
  • Step S 27 conductive films are filled in respective insides of the contact holes CHt, CHa, CHs, CHr, CHH, and CHL, thereby to form the plugs PGt, PGa, PGs, PGr, PGH, and PGL, respectively.
  • the barrier conductor film is formed of a titanium film and a titanium nitride film formed over the titanium film, and can be formed using, for example, a sputtering method.
  • the barrier conductor film has a so-called diffusion barrier property of preventing, for example, tungsten which is a material for the main conductor film to be embedded in a later step from being diffused into silicon.
  • a main conductor film formed of a tungsten film is formed over the barrier conductor film in such a manner as to fill each of the contact holes CHt, CHa, CHs, CHr, CHH, and CHL.
  • the main conductor film can be formed using, for example, a CVD method.
  • unnecessary portions of the main conductor film and the barrier conductor film formed over the interlayer insulation film IL 1 are removed by, for example, a CVD method.
  • a CVD method As a result, it is possible to form each of the plugs PGt, PGa, PGs, PGr, PGH, and PGL.
  • interlayer insulation films IL 2 to IL 4 there are formed interlayer insulation films IL 2 to IL 4 , and wires M 1 to M 3 .
  • interlayer insulation film IL 1 As the interlayer insulation film IL 2 , a lamination film of a silicon nitride (SiN) film and a silicon oxide (SiO 2 ) film is formed by a CVD method or the like. Then, there is formed a contact hole penetrating through the interlayer insulation film IL 2 , and reaching the wire M 1 .
  • a barrier film As a barrier film, a lamination film of a tantalum (Ta) film, and a tantalum nitride (TaN) film thereover is deposited by a sputtering method or the like.
  • a seed film As a seed film (not shown), a thin copper (Cu) film is deposited by a sputtering method or the like.
  • the copper film is deposited over the seed film.
  • unnecessary portions of the barrier film, the seed film, and the copper film over the interlayer insulation film IL 2 are removed by a CMP method or the like.
  • the wire M 1 can be formed (single damascene method).
  • the interlayer insulation film IL 3 over the interlayer insulation film IL 2 including the wire M 1 formed therein, there is formed the interlayer insulation film IL 3 .
  • the wire M 2 In the interlayer insulation film IL 3 , there is formed the wire M 2 .
  • the interlayer insulation film IL 4 Over the interlayer insulation film IL 3 including the wire M 2 formed therein, there is formed the interlayer insulation film IL 4 .
  • the wire M 3 In the interlayer insulation film IL 4 , there is formed the wire M 3 .
  • the wire M 1 and the wire M 2 are each formed of a copper wire by a damascene method.
  • the wire M 1 and the wire M 2 may be formed using aluminum by a patterning method.
  • a microlens ML is formed in a region over the interlayer insulation film IL 4 at the uppermost layer, and including the pixel region 1 A in a plan view.
  • the microlens ML as an on-chip lens is formed in such a manner as to overlap the n type well NW forming the photodiode PD in a plan view.
  • a passivation film PF and a color filter CL sequentially from the bottom.
  • the semiconductor device of the present First Embodiment can be manufactured.
  • respective conductivity types of the semiconductor substrate 1 S, the p type wells PW 1 , PW 2 , and PW 3 , the n type well NW, the p + type semiconductor region PR, the n type low concentration semiconductor region NM, and the n type high concentration semiconductor region NR may be changed to the opposite conductivity types, respectively (the same also applies to Second Embodiment).
  • FIG. 23 is a cross sectional view showing the configuration of the semiconductor device of Comparative Example 1.
  • FIGS. 24 to 26 are each a cross sectional view showing the semiconductor device of Comparative Example 1 during a manufacturing step. Incidentally, in FIG. 23 , the portion above the interlayer insulation film IL 1 is not shown.
  • the film parts FPt 100 , FPa 100 , FPs 100 , and FPr 100 formed by patterning the thin hard mask film HM 2 as a mask the conductive film CF 1 , and the gate insulation films GOX 1 , GOX 2 , and GOX 3 are etched.
  • the gate electrode GEt formed of the conductive film CF 1 is formed via the gate insulation film GOX 1 .
  • the gate electrode GEa formed of the conductive film CF 1 is formed via the gate insulation film GOX 1
  • the gate electrode GEs formed of the conductive film CF 1 is formed via the gate insulation film GOX 1 .
  • the gate electrode GEr formed of the conductive film CF 1 is formed via the gate insulation film GOX 1 .
  • Step S 20 and subsequent steps are performed, thereby to form the semiconductor device of Comparative Example 1.
  • Comparative Example 1 in the step of forming the n type well NW shown in FIG. 26 , in the pixel region 1 A and the peripheral circuit region 2 A, over the semiconductor substrate 1 S, there is formed a photoresist film R 1 . Then, in the pixel region 1 A, an opening OP 1 is formed so that the p type well PW 1 that is the portion of the active region AcTP in which the n type well NW is formed is exposed at the bottom of the opening OP 1 . Then, using the photoresist film R 1 including the opening OP 1 formed therein as a mask, n type impurity ions IM 1 are doped.
  • the opening OP 1 is formed in consideration of the alignment precision for exposure so that the portion of the p type well PW 1 adjacent to the gate electrode GEt is exposed at the bottom of the opening OP 1 with reliability in a plan view. Namely, the opening OP 1 is formed in such a manner as to penetrate through the photoresist film R 1 , and to reach the end on one side (the left-hand side of FIG. 26 ) of the film part FPt 100 . Whereas, in Comparative Example 1, over the gate electrode GEt, the film part FPt 100 including only the thin hard mask film HM 2 (see FIG. 25 ) is formed, but the film part FPt including the thick hard mask film HM 1 (see FIG. 15 ) is not formed. Therefore, ions may penetrate through film part FPt 100 , the gate electrode GEt, and the gate insulation film GOX 1 , to be doped into the p type well PW 1 immediately under the gate insulation film GOX 1 .
  • ions are doped to a position deep from the upper surface of the semiconductor substrate 1 S in self-alignment with the gate electrode GEt, thereby to form the photodiode PD.
  • the reason why ions are doped in self-alignment with the gate electrode GEt is as follows: if a deviations is caused in positional relationship between the gate electrode GEt and the photodiode PD, the characteristics for transferring the electrons generated in the photodiode PD are deteriorated.
  • the pn junction of the photodiode PD is desirably arranged at a position deep from the upper surface of the semiconductor substrate 1 S. Therefore, for the n type well of the p type well PW 1 and the n type well NW forming the pn junction of the photodiode PD, the lower surface of the n type well NW is arranged at a position as deep as possible.
  • the ions when ions are doped in alignment with the gate electrode GEt, the ions may penetrate through the gate electrode GEt, to be doped into the gate insulation film GOX 1 and the semiconductor substrate 1 S under the gate electrode GEt.
  • the ions in order to prevent or inhibit the gate insulation film GOX 1 and the semiconductor substrate 1 S under the gate electrode GEt from being doped with ions, for example, it can be considered that ions are doped with an insulation film formed over the gate electrode GEt.
  • the thick insulation film over each of the gate electrodes GEH and GEL in the peripheral circuit region 2 A is removed by, for example, wet etching, the element isolation region LCS or the gate insulation films GEH and GEL may be partially removed. Therefore, it is difficult to remove the insulation film over each of the gate electrodes GEH and GEL in the peripheral circuit region 2 A after forming the photodiode PD.
  • n type impurity ions cannot be doped into a position deep from the upper surface of the semiconductor substrate 1 S.
  • the photodiode PD is formed at a position shallow from the upper surface of the semiconductor substrate 1 S. Accordingly, the impurity ions in the p + type semiconductor region PR formed for compensating for crystal defects in the portion in the vicinity of the upper surface of the semiconductor substrate 1 S are diffused in the inside of the photodiode PD. Then, the diffusion of the impurity ions from the p + type semiconductor region PR in the inside of the photodiode PD reduces the number of saturated electrons in the photodiode PD. This may reduce the sensitivity of the CMOS image sensor, resulting in the degradation of the performances of the semiconductor device.
  • CMOS image sensor when a dark current increases while not being irradiated with a light, a light is determined as being exposed thereto despite the light not being exposed thereto. As a result, false lighting is caused, resulting in the formation of white points.
  • One of the probable causes for the dark current is the crystal defects formed in the semiconductor region forming the photodiode PD. Particularly, the portion in the vicinity of the upper surface of the semiconductor substrate 1 S includes a large number of crystal defects.
  • the formation of the photodiode PD at a position shallow from the upper surface of the semiconductor substrate 1 S may increase the frequency of the formation of white points with no light exposed thereto, namely, the formation of pixel defects, resulting in the reduction of the sensitivity of the CMOS image sensor. This reduces the performances of the semiconductor device.
  • the film part FPt formed of the thick hard mask film HM 1 . Further, when, for example, n type impurity ions are doped in order to form the photodiode PD, the impurity ions are doped in self-alignment with the gate electrode GEt covered with the film part FPt.
  • n type impurity ions can be doped to a position deep from the upper surface of the p type well PW 1 . Accordingly, the n type well NW can be formed at a position deep from the upper surface of the p type well PW 1 .
  • the photodiode PD can be formed at the portion distant from the portion in the vicinity of the upper surface of the p type well PW 1 including a large number of crystal defects. Therefore, it is possible to reduce the frequency of the formation of white points with no light exposed thereto, namely, the formation of pixel defects. Thus, it is possible to improve the sensitivity of the CMOS image sensor. As a result, it is possible to improve the performances of the semiconductor device.
  • the present First Embodiment as distinct from Second Embodiment described later, also over respective gate electrodes GEa, GEs, and GEr of transistors other than the transfer transistor TX in the pixel region 1 A, there are formed the film parts FPa, FPs, and FPr each formed of the thick hard mask film HM 1 , respectively. Therefore, during the manufacturing steps of the semiconductor device, it is not necessary to perform the step of removing the film parts over the gate electrodes GEa, GEs, and GEr of transistors other than the transfer transistor TX in the pixel region 1 A while leaving the film part over the gate electrode GEt of the transfer transistor TX in the inside of the pixel region 1 A. Therefore, as compared with Second Embodiment described later, the semiconductor device can be manufactured with ease.
  • First Embodiment a description has been given to the example in which the film parts each including the thick hard mask film are also formed over the gate electrodes of transistors other than the transfer transistor in the pixel region, in addition to over the gate electrode of the transfer transistor.
  • Second Embodiment a description will be given to an example in which, over the gate electrode of the transfer transistor, there is formed a film part formed of a thick hard mask film, but, over each gate electrode of transistors other than the transfer transistor in the pixel region, a film part formed of a thick hard mask film is not formed.
  • the configuration of the semiconductor device of the present Second Embodiment is the same as the configuration of the semiconductor device of First Embodiment described by reference to FIGS. 1 and 2 . A description thereon will be omitted. Further, the element structure in the peripheral circuit region is the same as the element structure in the peripheral circuit region described by reference to FIGS. 3 and 4 . A description thereon will be omitted.
  • FIGS. 27 and 28 are each a cross sectional view showing the configuration of the semiconductor device of Second Embodiment. Incidentally, in FIGS. 27 and 28 , as in FIGS. 3 and 4 , the element structure in the pixel region 1 A and the element structure in the peripheral circuit region 2 A are shown together. Further, in FIG. 28 , the portion above the interlayer insulation film IL 1 of FIG. 27 is not shown.
  • Respective portions other than the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST in the element structure in the pixel region 1 A of the semiconductor device of the present Second Embodiment are the same as respective portions in the element structure in the pixel region 1 A of the semiconductor device of First Embodiment. A description thereon will be omitted.
  • the amplification transistor AMI has the same structure as that of the amplification transistor AMI in First Embodiment, except that the film part FPa (see FIG. 3 ) is not formed over the gate electrode GEa. Then, in the present Second Embodiment, at the upper surface of the gate electrode GEa, there is formed a silicide layer SIL. This enables a coupling between the gate electrode GEa and a plug (not shown) at a low resistance.
  • the selection transistor SEL has the same structure as that of the selection transistor SEL of First Embodiment, except that the film part FPs (see FIG. 3 ) is not formed over the gate electrode GEs. Then, in the present Second Embodiment, at the upper surface of the gate electrode GEs, there is formed a silicide layer SIL. This enables a coupling between the gate electrode GEs and a plug (not shown) at a low resistance.
  • the reset transistor RST has the same structure as that of the reset transistor RST of First Embodiment, except that the film part FPr (see FIG. 3 ) is not formed over the gate electrode GEr. Then, in the present Second Embodiment, at the upper surface of the gate electrode GEr, there is formed a silicide layer SIL. This enables a coupling between the gate electrode GEr and a plug (not shown) at a low resistance.
  • the silicide layers SIL formed at respective upper surfaces of the gate electrodes GEa, GEs, and GEr are each formed of a metal silicide layer such as nickel silicide as with the silicide layers SIL formed at the upper surfaces of the source drain regions SD on respective opposite sides of the gate electrodes GEa, GEs, and GEr.
  • FIGS. 29 to 38 are each a cross sectional view showing the semiconductor device of Second Embodiment during a manufacturing step.
  • FIGS. 29 to 38 the manufacturing steps in the pixel region 1 A and the manufacturing steps in the peripheral circuit region 2 A are shown together.
  • the manufacturing steps in the peripheral circuit region 2 A are the same as the manufacturing steps in the peripheral circuit region 2 A in First Embodiment described by reference to FIGS. 7 to 22 . A description thereon will be omitted.
  • FIGS. 5 and 6 are each a manufacturing process flowchart showing some of the manufacturing steps of the semiconductor device of First Embodiment.
  • Step S 14 of FIG. 5 is performed, thereby to form the thick hard mask film HM 1 as shown in FIG. 10 .
  • the step corresponding to Step S 15 of FIG. 5 is performed, thereby to pattern the thick hard mask film HM 1 .
  • the step corresponding to the Step S 15 as shown in FIG. 29 , in the pixel region 1 A, the thick hard mask film HM 1 is patterned.
  • the film part FPt 1 formed of the thick hard mask film HM 1 is formed, the film parts FPa 1 , FPs 1 , and FPr 1 (see FIG. 11 ) are not formed.
  • the step corresponding to Step S 16 of FIG. 5 is performed, thereby to form the thin hard mask film HM 2 .
  • the film parts FPa 1 , FPs 1 , and FPr 1 are not formed.
  • the hard mask film HM 2 thinner than the hard mask film HM 1 namely, the hard mask film HM 2 having a film thickness TH 6 smaller than the thickness TH 5 of the hard mask film HM 1 .
  • the procedure can be performed in the same manner as in the step of Step S 16 of FIG. 5 .
  • the step corresponding to Step S 17 of FIG. 5 is performed, thereby to pattern the thin hard mask film HM 2 .
  • the photoresist film is left in the pixel region 1 A, in the region in which the film parts FPa 2 , FPs 2 , and FPr 2 are formed.
  • the thin hard mask film HM 2 is etched.
  • the procedure can be performed in the same manner as in the step of Step S 17 of FIG. 5 .
  • the step corresponding to Step S 18 of FIG. 5 is performed.
  • the gate electrodes GEt, GEa, GEs, GEr, GEH, and GEL are formed.
  • the film thickness TH 6 of the film parts FPa 2 , FPs 2 , and FPr 2 is smaller than the film thickness TH 5 of the film parts FPa, FPs, and FPr (see FIG. 13 ).
  • the procedure can be performed in the same manner as in the step of Step S 18 of FIG. 5 .
  • Step S 19 of FIG. 5 is performed, thereby to form the n type well NW as shown in FIG. 33 .
  • the same step as Step S 20 of FIG. 5 is performed, thereby to form the p + type semiconductor region PR as shown in FIG. 34 .
  • the same step as Step S 21 of FIG. 6 is performed, thereby to form the n type low concentration semiconductor regions NM as shown in FIG. 35 .
  • the step corresponding to Step S 22 of FIG. 6 is performed, thereby to form and pattern the cap insulation film CAP as shown in FIG. 36 .
  • the insulation film CAP 1 is etched back, so that the film parts FPa 2 , FPs 2 , and FPr 2 are exposed. Further, the exposed film parts FPa 2 , FPs 2 , and FPr 2 are removed. Then, at respective side surfaces of the gate electrodes GEa, GEs, and GEr, the insulation films CAP 1 are left. As a result, there are formed the sidewalls SW each formed of the left insulation film CAP 1 . As for other points, the procedure can be performed in the same manner as in the step of Step S 22 of FIG. 6 .
  • Step S 23 of FIG. 6 is performed, thereby to form the n type high concentration semiconductor regions NR as shown in FIG. 37 .
  • Step S 24 of FIG. 6 is performed, thereby to form the silicide layers SIL as shown in FIG. 38 .
  • the step corresponding to the Step S 24 in the active regions AcAS and AcR, at respective upper surfaces of the gate electrodes GEa, GEs, and GEr, there are formed the silicide layers SIL.
  • the procedure can be performed in the same manner as in the step of Step S 24 of FIG. 6 .
  • the silicide layer SIL need not be formed at the upper surface of the n type high concentration semiconductor region NR which is the drain region of the transfer transistor TX.
  • Step S 25 to Step S 27 of FIG. 6 the same steps as the steps of Step S 25 to Step S 27 of FIG. 6 described in connection with the manufacturing steps of the semiconductor device of First Embodiment are performed.
  • FIG. 28 there are formed the interlayer insulation film IL 1 , the contact holes CHt, CHa, CHs, CHr, CHH, and CHL, and the plugs PGt, PGa, PGs, PGr, PGH, and PGL.
  • the interlayer insulation films IL 2 to IL 4 , the wires M 1 to M 3 , and the microlens ML are formed.
  • the semiconductor device of the present Second Embodiment can be manufactured.
  • the passivation film PF and the color filter CL can be formed sequentially from the bottom between the microlens ML and the interlayer insulation film IL 4 .
  • the semiconductor device of the present Second embodiment has the same effects as the effects of the semiconductor device of First Embodiment.
  • First Embodiment it is possible to prevent or inhibit the reduction of the number of saturated electrodes in the photodiode PD. This can improve the sensitivity of the CMOS image sensor, resulting in an improvement of the performances of the semiconductor device. Further, as with First Embodiment, it is possible to reduce the frequency of the formation of white points with no light exposed thereto, namely, the formation of pixel defects. This can improve the sensitivity of the CMOS image sensor, resulting in an improvement of the performances of the semiconductor device.
  • each of the gate electrodes GEa, GEs, and GEr of transistors other than the transfer transistor TX in the pixel region 1 A there is not formed a film part including a thick hard mask film HM 1 .
  • This can establish a coupling between respective gate electrodes of transistors other than the transfer transistor TX in the pixel region 1 A, such as the amplification transistor AMI, the selection transistor SEL, and the reset transistor RST and the plugs, respectively, at a low resistance.

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