US20130064012A1 - Semiconductor device and method of manufacturing semiconductor device - Google Patents
Semiconductor device and method of manufacturing semiconductor device Download PDFInfo
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- US20130064012A1 US20130064012A1 US13/669,102 US201213669102A US2013064012A1 US 20130064012 A1 US20130064012 A1 US 20130064012A1 US 201213669102 A US201213669102 A US 201213669102A US 2013064012 A1 US2013064012 A1 US 2013064012A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims abstract description 42
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- 238000005530 etching Methods 0.000 claims description 62
- 238000000034 method Methods 0.000 claims description 30
- 238000002955 isolation Methods 0.000 claims description 28
- 239000011229 interlayer Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000002344 surface layer Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 229910004541 SiN Inorganic materials 0.000 claims description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 6
- 239000012535 impurity Substances 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
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- 229910052759 nickel Inorganic materials 0.000 description 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Definitions
- the present invention relates to a semiconductor device having a sidewall and a method of manufacturing the semiconductor device.
- DRAM Dynamic Random Access Memory
- the latest transistors have a sidewall and an extension region of a source and drain region.
- the sidewall covers a sidewall of a gate electrode.
- the extension region is located under the sidewall, that is, between the source and drain region and the channel region (for example, Japanese Unexamined patent publication NOS. 2000-269351, 2004-349372, 2008-78359, and 2006-196493).
- Japanese Unexamined patent publication NOS. 2004-349372 and 2008-78359 disclose that an N-type MOS transistor and a P-type MOS transistor are made different from each other in width of the sidewall.
- the on-state current is high.
- the transistor connected to a capacitive element such as the transistor included in the peripheral circuit of the DRAM
- the leak current is small.
- miniaturization of semiconductor devices has progressed, and the gate length has been shortened with this progress.
- the gate length is shortened, the on-state current of the transistor is increased and thus a leak current is easily generated.
- the transistor included in the logic circuit and the transistor connected to the capacitive element are generally manufactured by the same process. For this reason, in the transistor connected to the capacitive element, the leak current is caused to increase.
- a semiconductor device including: a first transistor, formed in a substrate, that includes a first gate insulating film, a source and drain region, a first gate electrode, and a first sidewall; and a second transistor, formed in the substrate, that includes a second gate insulating film, a second gate electrode, a source and drain region, and a second sidewall, wherein the first transistor is a portion of a logic circuit, the second transistor is a transistor included in a memory cell of a DRAM, or is a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM, the first gate insulating film has the same thickness as that of the second gate insulating film, the first gate electrode has the same thickness as that of the second gate electrode, and the width of the second sidewall is larger than the width of the first sidewall.
- the width of the second sidewall is larger than the width of the first sidewall. For this reason, it is possible that while the on-state current of the first transistor is raised by decreasing the substantial gate length of the first transistor, the leak current of the second transistor is lowered by increasing the substantial gate length of the second transistor.
- a method of manufacturing a semiconductor device including: forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which are a portion of a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell of a DRAM or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM; and forming an extension region of the first transistor and an extension region of the second transistor, forming a first sidewall in a sidewall of the first gate electrode, forming a second sidewall having a larger width than that of the first sidewall in a sidewall of the second gate electrode, and forming a source and drain region in each of the first transistor and the second transistor.
- the leak current of the second transistor is lowered.
- FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment
- FIGS. 2A and 2B are cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 1 ;
- FIGS. 3A and 3B are cross-sectional views illustrating the method of manufacturing the semiconductor device shown in FIG. 1 ;
- FIGS. 4A and 4B are cross-sectional views illustrating the method of manufacturing the semiconductor device shown in FIG. 1 ;
- FIGS. 5A and 5B are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a second embodiment
- FIGS. 6A and 6B are cross-sectional views illustrating the method of manufacturing the semiconductor device according to a second embodiment
- FIG. 7 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according the second embodiment
- FIGS. 8A to 8D are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a third embodiment
- FIGS. 9A to 9D are cross-sectional views illustrating the method of manufacturing the semiconductor device according to a third embodiment
- FIG. 10 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to a third embodiment
- FIG. 11 is a plan view illustrating a state before an etching stopper film and an insulating interlayer are formed in the semiconductor device shown in FIG. 9D ;
- FIG. 12 is a cross-sectional view illustrating the configuration of the semiconductor device according to a comparative example
- FIG. 13 is a plan view illustrating the configuration of the semiconductor device according to the comparative example.
- FIGS. 14A to 14C are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a fourth embodiment.
- FIGS. 15A to 15C are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the fourth embodiment.
- FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.
- This semiconductor device includes a first transistor 100 , a second transistor 200 , and a capacitive element 300 .
- the first transistor 100 is formed in a substrate 10 such as a silicon substrate, and includes a first gate insulating film 110 , a first gate electrode 120 , and a first sidewall 150 .
- the second transistor is formed the substrate 10 , and includes a second gate insulating film 210 , a second gate electrode 220 , and a second sidewall 250 .
- a capacitive element 300 is connected to the one side of source and drain regions 240 of the second transistor 200 .
- the first gate insulating film 110 has the same thickness as that of the second gate insulating film 210
- the first gate electrode 120 has the same thickness as that of the second gate electrode 220 .
- the width of the second sidewall 250 is wider than the width of the first sidewall 150 .
- the first transistor 100 has two source and drain regions 140 .
- the source and drain regions 140 are respectively provided with an extension region 130 .
- the extension region 130 is the same conductive impurity region as the source and drain regions 140 , and has a lower impurity concentration than that of the source and drain regions 140 .
- the extension region 130 is located under the first sidewall 150 .
- the second transistor 200 has two source and drain regions 240 .
- the source and drain regions 240 are respectively provided with an extension region 230 .
- the extension region 230 is the same conductive impurity region as the source and drain region 240 , and has a lower impurity concentration than that of the source and drain region 240 .
- the extension region 230 is located under the second sidewall 250 .
- the width of the second sidewall 250 is wider than the width of the first sidewall 150 .
- the width of the extension region 230 is wider than the width of the extension region 130 of the first transistor 100 .
- the width of the first sidewall 150 is equal to or greater than 1 nm and equal to or less than 70 nm
- the width of the second sidewall 250 is equal to or greater than 1.4 nm and equal to or less than 100 nm.
- the first gate insulating film 110 has the same not only thickness but also width as the second gate insulating film 210 .
- the first gate electrode 120 has the same not only thickness but also width as the second gate electrode 220 .
- the widths of the first gate electrode 120 and the second gate electrode 220 are equal to or less than, for example, 130 nm.
- the capacitive element 300 is, for example, a MIM (Metal-Insulator-Metal) type capacitive element having a cylinder shape, and is a portion of a memory cell of Dynamic Random Access Memory (DRAM).
- the first transistor 100 is a portion of a logic circuit
- the second transistor 200 is a transistor included in the memory cell of DRAM, or is a portion of a peripheral circuit that performs writing and erasing with respect to DRAM.
- One side of the source and drain regions 240 of the second transistor 200 is connected to the capacitive element 300 , and the other side of the source and drain regions 240 is connected to a bit line 310 .
- An etching stopper film 30 and an insulating interlayer 40 are in this order formed on the first transistor 100 and the second transistor 200 .
- the etching stopper film 30 is, for example, TEOS, SiO 2 , SiN, SiON, HDP, PSG, NSG, or BPSG, and functions as an etching stopper at the time of forming a contact hole in the insulating interlayer 40 .
- the insulating interlayer 40 is a multilayer film in which a plurality of insulating films is laminated.
- the first sidewall 150 is formed by a first insulating film 152 and a second insulating film 154
- the second sidewall 250 is formed by a first insulating film 252 and a second insulating film 254 .
- the first insulating film 152 is located on the substrate 10 and on the sidewall of the first gate electrode 120 , and is formed along the substrate 10 and the sidewall of the first gate electrode 120 .
- the second insulating film 154 is formed on the first insulating film 152 .
- the first insulating film 252 is formed on the substrate 10 and on the sidewall of the second gate electrode 220
- the second insulating film 254 is formed on the first insulating film 252 .
- the first insulating film 152 and the first insulating film 252 are the same film, and are formed of, for example, a silicon nitride film.
- the second insulating film 154 and the second insulating film 254 are the same film, and are formed of, for example, a silicon oxide film.
- a concave portion 156 is provided in the end surface of the first insulating film 152 located on the substrate 10
- a concave portion 256 is provided in the end surface of the first insulating film 252 located on the substrate 10 .
- the concave portion 156 is deeper than the concave portion 256 .
- the etching stopper film 30 intrudes into both of the concave portions 156 and 256 .
- contact plugs 42 , 44 , and 46 are buried in the insulating interlayer 40 .
- an insulating film among interconnects 41 is formed on the insulating interlayer 40 .
- Interconnects 50 and 52 are buried in the insulating film among interconnects 41 .
- the contact plug 42 is connected to the interconnect 50 and one side of the source and drain regions 140 of the first transistor 100 .
- the contact plug 44 is connected to the bit line 310 and one side of the source and drain regions 240 of the second transistor 200
- the contact plug 46 is connected to a lower electrode of the capacitive element 300 and the other side of the source and drain regions 240 of the second transistor 200 .
- an device isolation insulating film 20 is formed in the substrate 10 .
- the device isolation insulating film 20 is disposed to isolate each of the first transistor 100 and the second transistor 200 from others.
- FIGS. 2A and 2B to FIGS. 4A and 4B are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the embodiment.
- the first gate insulating film 110 and the first gate electrode 120 of the first transistor 100 , and the second gate insulating film 210 and the second gate electrode 220 of the second transistor 200 are formed on the substrate 10 .
- the extension region 130 of the first transistor 100 and the extension region 230 of the second transistor 200 are formed.
- an impurity implantation process for forming the extension region 130 is performed using a process separate from the impurity implantation process for forming the extension region 230 .
- the first sidewall 150 is formed in the sidewall of the first gate electrode 120 , and the second sidewall 250 having a larger width than that of the first sidewall 150 is formed in the sidewall of the second gate electrode 220 .
- the source and drain region 240 of the second transistor 200 is formed.
- the capacitive element 300 which is connected to the source and drain region 240 is formed.
- the device isolation insulating film 20 is formed in the substrate 10 by, for example, a Shallow Trench Isolation (STI) method.
- STI Shallow Trench Isolation
- the first gate insulating film 110 and the second gate insulating film 210 are formed in the substrate 10 by the same process.
- a conductive film for example, a polysilicon film is formed on the whole surface including the upper portions of the first gate insulating film 110 and the second gate insulating film 210 .
- the thickness of this conductive film is, for example, equal to or greater than 30 nm and equal to or less than 180 nm.
- the conductive film is selectively removed.
- the first gate electrode 120 and the second gate electrode 220 are formed.
- the first gate electrode 120 and the second gate electrode 220 need not be polysilicon gates, and may be formed of, for example, silicides such as a nickel silicide, or metals.
- ion implantation is performed using the device isolation insulating film 20 , the first gate electrode 120 , and the second gate electrode 220 as a mask. Thereby, the extension region 130 of the first transistor 100 and the extension region 230 of the second transistor 200 are formed in a self-aligning manner.
- a first insulating film 500 and a second insulating film 502 are in this order formed on the substrate 10 , the device isolation insulating film 20 , the first gate electrode 120 , and the second gate electrode 220 .
- the first insulating film 500 is, for example, a silicon nitride film
- the second insulating film 502 is a silicon oxide film.
- the second insulating film 502 and the first insulating film 500 are etched.
- this etching for example, dry etching is initially performed, and then wet etching is performed.
- the first sidewall 150 and the second sidewall 250 are formed.
- the concave portions 156 and 256 are respectively formed, due to wet etching, in the end surfaces of the portions located on the substrate 10 in the first insulating film 152 of the first sidewall 150 and the first insulating film 252 of the second sidewall 250 .
- cross-sectional shapes of the first sidewall 150 and the second sidewall 250 are substantially equal to each other.
- the depths of the concave portions 156 and 256 are substantially equal to each other.
- a mask film 520 is formed on the substrate 10 .
- the mask film 520 is, for example, a resist film, and covers the region in which the first transistor 100 is formed, but does not cover the region in which the second transistor 200 is formed.
- ion implantation is performed using the mask film 520 , the device isolation insulating film 20 , the second gate electrode 220 , and the second sidewall 250 as a mask. Thereby, the source and drain region 240 of the second transistor 200 is formed.
- the mask film 520 is removed.
- a mask film 530 is formed on the substrate 10 .
- the mask film 530 is, for example, a resist film, and covers the region (including the second gate electrode 220 and the second sidewall 250 ) in which the second transistor 200 is formed, but does not cover the region (including the first gate electrode 120 and the first sidewall 150 ) in which the first transistor 100 is formed.
- etching is performed using the mask film 530 as a mask. Thereby, the first sidewall 150 is etched, and decreases in width. This etching process includes a wet etching process. For this reason, the concave portion 156 is deepened.
- ion implantation is performed using the mask film 530 , the device isolation insulating film 20 , the first gate electrode 120 , and the first sidewall 150 as a mask. Thereby, the source and drain region 140 of the first transistor 100 is formed.
- the mask film 530 is removed. Thereafter, as shown in FIG. 1 , the etching stopper film 30 , the insulating interlayer 40 , the capacitive element 300 , the contact plugs 42 , 44 , and 46 , the insulating film among interconnects 41 , and the interconnects 50 and 52 are formed. In a process of forming the etching stopper film 30 among processes of forming them, a portion of the etching stopper film 30 intrudes into the concave portions 156 and 256 .
- the width of the second sidewall 250 of the second transistor 200 is larger than the width of the first sidewall 150 of the first transistor 100 .
- the width of the extension region 230 of the second transistor 200 is larger than the width of the extension region 130 of the first transistor 100 . Therefore, it is possible that while the on-state current of the first transistor 100 is raised by decreasing the substantial gate length of the first transistor 100 , the leak current of the second transistor 200 is lowered by increasing the substantial gate length of the second transistor 200 . For this reason, the holding time of information in the capacitive element 300 can be prolonged.
- the etching stopper film 30 intrudes into the concave portion 156 of the first sidewall 150 and the concave portion 256 of the second sidewall 250 , respectively.
- the concave portion 156 is deeper than the concave portion 256 . For this reason, stress generated from the etching stopper film 30 is easily applied to a channel region of the first transistor 100 . Therefore, the driving current of the first transistor 100 is increased.
- FIGS. 5A and 5B to FIG. 7 are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a second embodiment.
- the method of manufacturing the semiconductor device is the same as the method of manufacturing the semiconductor device shown in the first embodiment, with the exception of the formation timing of the first sidewall 150 and the second sidewall 250 .
- the semiconductor device manufactured by the embodiment is the same as that of the first embodiment, with the exception that there is a case where the depth of the concave portion 156 is small.
- the device isolation insulating film 20 is formed in the substrate 10 , and the first gate insulating film 110 and second gate insulating film 210 , the first gate electrode 120 and the second gate electrode 220 , the extension regions 130 and 230 , and the first insulating film 500 and the second insulating film 502 are further formed therein.
- the method of forming them is the same as that of the first embodiment.
- the mask film 530 is formed in the substrate 10 .
- the mask film 530 is, for example, a resist film, and covers the region (including the second gate electrode 220 ) in which the second transistor 200 is formed, but does not cover the region (including the first gate electrode 120 ) in which the first transistor 100 is formed.
- first insulating film 500 and second insulating film 502 are etched using the mask film 530 as a mask. Thereby, the first sidewall 150 is formed.
- ion implantation is performed using the mask film 530 , the device isolation insulating film 20 , the first gate electrode 120 , and the first sidewall 150 as a mask. Thereby, the source and drain region 140 used as a source and a drain of the first transistor 100 is formed.
- the mask film 530 is removed.
- the mask film 520 is formed on the substrate 10 .
- the mask film 520 is, for example, a resist film, and covers the region (including the first gate electrode 120 and the first sidewall 150 ) in which the first transistor 100 is formed, but does not cover the region (including the second gate electrode 220 ) in which the second transistor 200 is formed.
- the first insulating film 500 and the second insulating film 502 are etched using the mask film 520 as a mask. Thereby, the second sidewall 250 is formed. At this time, the width of the second sidewall 250 is made larger than the width of the first sidewall 150 by adjusting etching conditions.
- ion implantation is performed using the mask film 520 , the device isolation insulating film 20 , the second gate electrode 220 , and the second sidewall 250 as a mask. Thereby, the source and drain region 240 used as a source and a drain of the second transistor 200 is formed.
- the mask film 520 is removed.
- the etching stopper film 30 , the insulating interlayer 40 , the capacitive element 300 , the contact plugs 42 , 44 , and 46 , the insulating film among interconnects 41 , and the interconnects 50 and 52 are formed as shown in FIG. 1 .
- the logic circuit includes a densely-packed pattern and an isolated pattern, and the DRAM is formed only by a densely-packed pattern in many cases.
- anisotropic etching for forming the sidewall the etching rate in the isolated pattern of the logic circuit is slower than that of the densely-packed pattern. For this reason, it is often the case that the optimum time of etching in the logic circuit is longer than the optimum time of etching in the DRAM.
- the etching time is set to the optimum time of etching in the DRAM
- the insulating film used as a sidewall in the logic circuit remains in a portion other than the sidewall.
- the etching time is set to the optimum time of etching in the logic circuit
- the etching amount of the substrate becomes larger in the DRAM and thus a defect occurs in the source and drain region. This defect causes the leak current from the capacitive element and thus the data retention characteristics of the DRAM are deteriorated.
- the etching conditions for forming each of them can be set to each of the optimum conditions. For this reason, it is possible to suppress the generation of the above-mentioned problems.
- FIGS. 8A to 8D , FIGS. 9A to 9D , and FIG. 10 are cross-sectional views illustrating a method of manufacturing the semiconductor device according a third embodiment.
- the capacitive element 300 and the interconnects 50 and 52 are not shown in these drawings.
- the device isolation insulating film 20 is formed in the substrate 10 , and the first gate insulating film 110 and the second gate insulating film 210 , and the first gate electrode 120 and the second gate electrode 220 are further formed. A method of forming them is the same as that of the first embodiment.
- an offset spacer film 122 is formed in the sidewall of the first gate electrode 120
- an offset spacer film 222 is formed in the sidewall in the second gate electrode 220 .
- impurities are implanted in the substrate 10 using the first gate electrode 120 , the second gate electrode 220 , the device isolation insulating film 20 , and the offset spacer films 122 and 222 as a mask.
- the extension regions 130 and 230 are formed. Meanwhile, the impurity implantation process for forming the extension region 130 is performed using a process separate from the impurity implantation process for forming the extension region 230 .
- the first insulating film 500 is formed.
- the first insulating film 500 is, for example, a silicon nitride film.
- the second insulating film 502 is formed on the first insulating film 500 .
- the second insulating film 502 is formed of materials different from the etching stopper film 30 as described later, and it is possible to raise etching selectivity with respect to the etching stopper film 30 .
- the second insulating film 502 is, for example, a silicon oxide film, and is thicker than the first insulating film 500 .
- a mask film 540 is formed on the second insulating film 502 .
- the mask film 540 does not cover a portion located on the first gate electrode 120 in the second insulating film 502 , but covers a portion located on the second gate electrode 220 .
- the second insulating film 502 is wet-etched using the mask film 540 as a mask. Thereby, a portion located on the first gate electrode 120 and on the periphery thereof in the second insulating film 502 is removed, and the second insulating film 502 is formed on the second gate electrode 220 and on the periphery thereof.
- a third insulating film 504 used as a sidewall is formed on the second insulating film 502 , and the first gate electrode 120 and the periphery thereof.
- the third insulating film 504 is formed of the same materials as those of the second insulating film 502 .
- the third insulating film 504 located on the first gate electrode 120 and on the periphery thereof is covered with a mask film 550 .
- the mask film 550 does not cover the third insulating film 504 located on the second gate electrode 220 and on the periphery thereof.
- the mask film 550 covers a portion near the region where the second transistor 200 is formed in the device isolation insulating film 20 .
- the third insulating film 504 and the second insulating film 502 are etched using the mask film 550 as a mask, and the first insulating film 500 is further etched.
- anisotropic dry etching is used.
- the second sidewall 250 is formed.
- the surface of a portion which is not covered with the mask film 550 in the device isolation insulating film 20 is etched. Thereby, a step difference 22 is formed in the device isolation insulating film 20 .
- the mask film 550 is removed.
- the region where the extension region 230 is formed in the second gate electrode 220 , the second sidewall 250 , and the substrate 10 is covered with a mask film 560 .
- the mask film 560 does not cover the third insulating film 504 located on the first gate electrode 120 and on the periphery thereof.
- the mask film 560 covers a portion near the region where the second transistor 200 is formed in the device isolation insulating film 20 .
- the edge of the mask film 560 is kept away at a certain distance, for example, 20 nm or more from the step difference 22 . This distance is set to be larger than the sum value of maximum values of the position shift amount of the mask films 550 and 560 .
- the third insulating film 504 is etched using the mask film 560 as a mask, and the first insulating film 500 is further etched.
- anisotropic dry etching is used.
- the first sidewall 150 is formed.
- the width of the first sidewall 150 is made narrower than the width of the second sidewall 250 .
- the surface of a portion which is not covered with the mask film 560 in the device isolation insulating film 20 is etched. As described above, the edge of the mask film 560 is kept away at a certain distance from the step difference 22 . For this reason, a groove 24 is formed in the surface of the device isolation insulating film 20 .
- the mask film 560 is removed.
- the source and drain regions 140 and 240 are formed by performing ion implantation in the substrate 10 . Meanwhile, the ion implantation process for forming the source and drain region 140 is performed using a process separate from the ion implantation process for forming the source and drain regions 240 .
- a silicide forming metal film for example, Ni or Co is formed in the whole surface including the upper portions of the source and drain regions 140 and 240 , the first gate electrode 120 , and the second gate electrode 220 .
- the metal film, the source and drain regions 140 and 240 , the first gate electrode 120 , and the second gate electrode 220 are heat-treated.
- silicide films 142 and 242 are respectively formed on the source and drain regions 140 and 240
- silicide films 124 and 224 are respectively formed on the first gate electrode 120 and the second gate electrode 220 .
- the metal film which is not silicidized is removed.
- the etching stopper film 30 and the insulating interlayer 40 are formed.
- the etching stopper film 30 is the same material that of the first embodiment, for example, a silicon nitride film.
- a mask pattern (not shown) is formed on the insulating interlayer 40 , and the insulating interlayer 40 and the etching stopper film 30 are etched using this mask pattern as a mask. Thereby, a contact hole connected to the source and drain region 140 is formed.
- the contact plug 42 is formed by burying a conductor, for example, a metal such as Cu within this contact hole. Meanwhile, in this process, the contact plugs 44 and 46 shown in FIG. 1 are also formed, but are not shown in the same drawing.
- the capacitive element 300 , the insulating film among interconnects 41 , and the interconnects 50 and 52 shown in FIG. 1 are formed.
- FIG. 11 is a plan view illustrating a state before the etching stopper film 30 and the insulating interlayer 40 are formed in the semiconductor device shown in FIG. 9D .
- a gate interconnect 400 is formed on the device isolation insulating film 20 .
- the gate interconnect 400 is formed of an extraction interconnect of the second gate electrode 220 , and is connected to the second gate electrode 220 .
- a silicide film 402 is also formed in the surface layer of the gate interconnect 400 . Meanwhile, the gate interconnect 400 lies across the groove 24 .
- the second insulating film 154 in which the surface layer of the first sidewall 150 is formed is formed by materials different from those of the etching stopper film 30 , and this can raise etching selectivity with respect to the etching stopper film 30 .
- the first sidewall 150 is formed only by the first insulating film 152 , for example, as shown in FIG. 12 .
- the contact hole passes through the first sidewall 150 and thus the contact plug 42 is connected to the extension region 130 .
- the extension region 130 is shallow in depth relative to the source and drain region 140 . Therefore, in this case, the leak current of the first transistor 100 is increased.
- the second insulating film 154 in which the surface layer of the first sidewall 150 is formed has a high etching selectivity with respect to the etching stopper film 30 as described above. Therefore, even when the position of the contact hole for burying the contact plug 42 is shifted to thereby overlap with the first sidewall 150 , the contact hole does not pass through the first sidewall 150 and thus the leak current of the first transistor 100 is not increased.
- the third insulating film 504 remains in a portion which is covered by both the mask film 550 and the mask film 560 in the device isolation insulating film 20 , and thus a portion of the gate interconnect 400 is caused to be covered by the third insulating film 504 .
- the silicide film 402 is not formed in a portion which is covered by the third insulating film 504 in the gate interconnect 400 . As a result, resistance of the gate interconnect 400 is increased.
- the edge of the mask film 560 is kept away at a certain distance, for example, 20 nm or more from the step difference 22 .
- a certain distance for example, 20 nm or more from the step difference 22 .
- first sidewall 150 and the second sidewall 250 are formed by a separate process, it is possible to set etching conditions for forming each of them to each of the optimum conditions. For this reason, the insulating film for forming the sidewall is suppressed from remaining on the first gate electrode 120 , the second gate electrode 220 , or the gate interconnect 400 . Therefore, it is possible to form the silicide films 124 , 224 , and 402 on the entirety of the surfaces of the first gate electrode 120 , the second gate electrode 220 , and the gate interconnect 400 .
- FIGS. 14A to 14C and FIGS. 15A to 15C are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a fourth embodiment.
- the same reference numerals are assigned to the same components as those in the third embodiment, descriptions thereof will not be repeated.
- the device isolation insulating film 20 is formed in the substrate 10 , and further formed are the first gate insulating film 110 and the second gate insulating film 210 , the first gate electrode 120 and the second gate electrode 220 , the offset spacer films 122 and 222 , the extension regions 130 and 230 , the first insulating film 500 , and the second insulating film 502 .
- a method of forming them is the same as that of the third embodiment.
- the second insulating film 502 is etched. In etching at this time, anisotropic dry etching is used. Thereby, a sidewall 251 used as a portion of the second sidewall 250 is formed on the sidewall of the second gate electrode 220 . In addition, the second insulating film 502 remains on the sidewall of the first gate electrode 120 , and is used as a sidewall 151 .
- the sidewall 251 and the second gate electrode 220 are covered by a mask film 570 .
- the mask film 570 does not cover the first gate electrode 120 and the sidewall 151 .
- wet etching is performed using the mask film 570 as a mask, and the sidewall 151 is removed.
- the mask film 570 is removed.
- the third insulating film 504 used as a sidewall is formed on the entirety of the surfaces including the upper portions of the first gate electrode 120 and the lateral face thereof, the second gate electrode 220 , and the sidewall 251 .
- the third insulating film 504 is etched.
- anisotropic dry etching is used. Thereby, the first sidewall 150 and the second sidewall 250 are formed.
- the source and drain regions 140 and 240 formed are the source and drain regions 140 and 240 , the silicide films 142 , 242 , 124 , and 224 , the etching stopper film 30 , the insulating interlayer 40 and the contact plug 42 .
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Abstract
A semiconductor device includes a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall, and a second transistor that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall. The first transistor includes a portion of a logic circuit. The second transistor includes a transistor included in a memory cell of a DRAM, or includes a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM. The first gate insulating film has a same thickness as that of the second gate insulating film. The first gate electrode has the same thickness as that of the second gate electrode. A layer structure of the first sidewall is a same as a layer structure of the second sidewall.
Description
- The present application is a Divisional Application of U.S. patent application Ser. No. 12/805,291, filed on Jul. 22, 2010, which is based on Japanese patent application NOs. 2009-190066 and 2010-131424, the entire contents of which are incorporated hereinto by reference.
- 1. Technical Field
- The present invention relates to a semiconductor device having a sidewall and a method of manufacturing the semiconductor device.
- 2. Related Art
- In recent years, semiconductor devices have been manufactured in which a logic circuit and a memory device such as Dynamic Random Access Memory (DRAM) are integrated onto one substrate. In such semiconductor devices, a transistor included in the logic circuit and a transistor included in a peripheral circuit of the DRAM are generally manufactured by the same process. For this reason, the transistor included in the logic circuit and the transistor included in the peripheral circuit of the DRAM have, in general, mutually the same structure.
- On the other hand, it is often the case that the latest transistors have a sidewall and an extension region of a source and drain region. The sidewall covers a sidewall of a gate electrode. The extension region is located under the sidewall, that is, between the source and drain region and the channel region (for example, Japanese Unexamined patent publication NOS. 2000-269351, 2004-349372, 2008-78359, and 2006-196493).
- In particular, Japanese Unexamined patent publication NOS. 2004-349372 and 2008-78359 disclose that an N-type MOS transistor and a P-type MOS transistor are made different from each other in width of the sidewall.
- In the transistor included in the logic circuit, it is preferable that the on-state current is high. On the other hand, in the transistor connected to a capacitive element, such as the transistor included in the peripheral circuit of the DRAM, it is preferable that the leak current is small. Recently, miniaturization of semiconductor devices has progressed, and the gate length has been shortened with this progress. When the gate length is shortened, the on-state current of the transistor is increased and thus a leak current is easily generated. As mentioned above, in the semiconductor device in which the logic circuit and the transistor connected to the capacitive element are integrated onto one substrate, the transistor included in the logic circuit and the transistor connected to the capacitive element are generally manufactured by the same process. For this reason, in the transistor connected to the capacitive element, the leak current is caused to increase.
- In one embodiment, there is provided a semiconductor device including: a first transistor, formed in a substrate, that includes a first gate insulating film, a source and drain region, a first gate electrode, and a first sidewall; and a second transistor, formed in the substrate, that includes a second gate insulating film, a second gate electrode, a source and drain region, and a second sidewall, wherein the first transistor is a portion of a logic circuit, the second transistor is a transistor included in a memory cell of a DRAM, or is a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM, the first gate insulating film has the same thickness as that of the second gate insulating film, the first gate electrode has the same thickness as that of the second gate electrode, and the width of the second sidewall is larger than the width of the first sidewall.
- According to such a semiconductor device, the width of the second sidewall is larger than the width of the first sidewall. For this reason, it is possible that while the on-state current of the first transistor is raised by decreasing the substantial gate length of the first transistor, the leak current of the second transistor is lowered by increasing the substantial gate length of the second transistor.
- In another embodiment, there is provided a method of manufacturing a semiconductor device, including: forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor which are a portion of a logic circuit, and a second gate insulating film and a second gate electrode of a second transistor which is included in a memory cell of a DRAM or a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM; and forming an extension region of the first transistor and an extension region of the second transistor, forming a first sidewall in a sidewall of the first gate electrode, forming a second sidewall having a larger width than that of the first sidewall in a sidewall of the second gate electrode, and forming a source and drain region in each of the first transistor and the second transistor.
- According to the invention, it is possible that while the on-state current of the first transistor is raised, the leak current of the second transistor is lowered.
- The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment; -
FIGS. 2A and 2B are cross-sectional views illustrating a method of manufacturing the semiconductor device shown inFIG. 1 ; -
FIGS. 3A and 3B are cross-sectional views illustrating the method of manufacturing the semiconductor device shown inFIG. 1 ; -
FIGS. 4A and 4B are cross-sectional views illustrating the method of manufacturing the semiconductor device shown inFIG. 1 ; -
FIGS. 5A and 5B are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a second embodiment; -
FIGS. 6A and 6B are cross-sectional views illustrating the method of manufacturing the semiconductor device according to a second embodiment; -
FIG. 7 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according the second embodiment; -
FIGS. 8A to 8D are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a third embodiment; -
FIGS. 9A to 9D are cross-sectional views illustrating the method of manufacturing the semiconductor device according to a third embodiment; -
FIG. 10 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to a third embodiment; -
FIG. 11 is a plan view illustrating a state before an etching stopper film and an insulating interlayer are formed in the semiconductor device shown inFIG. 9D ; -
FIG. 12 is a cross-sectional view illustrating the configuration of the semiconductor device according to a comparative example; -
FIG. 13 is a plan view illustrating the configuration of the semiconductor device according to the comparative example. -
FIGS. 14A to 14C are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a fourth embodiment; and -
FIGS. 15A to 15C are cross-sectional views illustrating the method of manufacturing the semiconductor device according to the fourth embodiment. - The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
- Hereinafter, the embodiment of the invention will be described with reference to the accompanying drawings. In all the drawings, like elements are referenced by like reference numerals and descriptions thereof will not be repeated.
-
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. This semiconductor device includes afirst transistor 100, asecond transistor 200, and acapacitive element 300. Thefirst transistor 100 is formed in asubstrate 10 such as a silicon substrate, and includes a firstgate insulating film 110, afirst gate electrode 120, and afirst sidewall 150. The second transistor is formed thesubstrate 10, and includes a second gateinsulating film 210, asecond gate electrode 220, and asecond sidewall 250. Acapacitive element 300 is connected to the one side of source anddrain regions 240 of thesecond transistor 200. The firstgate insulating film 110 has the same thickness as that of the secondgate insulating film 210, and thefirst gate electrode 120 has the same thickness as that of thesecond gate electrode 220. The width of thesecond sidewall 250 is wider than the width of thefirst sidewall 150. Hereinafter, a detailed description will be given. - The
first transistor 100 has two source and drainregions 140. The source and drainregions 140 are respectively provided with anextension region 130. Theextension region 130 is the same conductive impurity region as the source and drainregions 140, and has a lower impurity concentration than that of the source and drainregions 140. Theextension region 130 is located under thefirst sidewall 150. - The
second transistor 200 has two source and drainregions 240. The source and drainregions 240 are respectively provided with anextension region 230. Theextension region 230 is the same conductive impurity region as the source and drainregion 240, and has a lower impurity concentration than that of the source and drainregion 240. Theextension region 230 is located under thesecond sidewall 250. As mentioned above, the width of thesecond sidewall 250 is wider than the width of thefirst sidewall 150. For this reason, the width of theextension region 230 is wider than the width of theextension region 130 of thefirst transistor 100. Meanwhile, the width of thefirst sidewall 150 is equal to or greater than 1 nm and equal to or less than 70 nm, and the width of thesecond sidewall 250 is equal to or greater than 1.4 nm and equal to or less than 100 nm. - In the embodiment, the first
gate insulating film 110 has the same not only thickness but also width as the secondgate insulating film 210. Thefirst gate electrode 120 has the same not only thickness but also width as thesecond gate electrode 220. The widths of thefirst gate electrode 120 and thesecond gate electrode 220 are equal to or less than, for example, 130 nm. - The
capacitive element 300 is, for example, a MIM (Metal-Insulator-Metal) type capacitive element having a cylinder shape, and is a portion of a memory cell of Dynamic Random Access Memory (DRAM). Thefirst transistor 100 is a portion of a logic circuit, and thesecond transistor 200 is a transistor included in the memory cell of DRAM, or is a portion of a peripheral circuit that performs writing and erasing with respect to DRAM. One side of the source and drainregions 240 of thesecond transistor 200 is connected to thecapacitive element 300, and the other side of the source and drainregions 240 is connected to abit line 310. - An
etching stopper film 30 and an insulatinginterlayer 40 are in this order formed on thefirst transistor 100 and thesecond transistor 200. Theetching stopper film 30 is, for example, TEOS, SiO2, SiN, SiON, HDP, PSG, NSG, or BPSG, and functions as an etching stopper at the time of forming a contact hole in the insulatinginterlayer 40. The insulatinginterlayer 40 is a multilayer film in which a plurality of insulating films is laminated. - The
first sidewall 150 is formed by a firstinsulating film 152 and a secondinsulating film 154, and thesecond sidewall 250 is formed by a firstinsulating film 252 and a secondinsulating film 254. The firstinsulating film 152 is located on thesubstrate 10 and on the sidewall of thefirst gate electrode 120, and is formed along thesubstrate 10 and the sidewall of thefirst gate electrode 120. The secondinsulating film 154 is formed on the first insulatingfilm 152. Similarly, the first insulatingfilm 252 is formed on thesubstrate 10 and on the sidewall of thesecond gate electrode 220, and the secondinsulating film 254 is formed on the first insulatingfilm 252. The firstinsulating film 152 and the first insulatingfilm 252 are the same film, and are formed of, for example, a silicon nitride film. The secondinsulating film 154 and the secondinsulating film 254 are the same film, and are formed of, for example, a silicon oxide film. - A
concave portion 156 is provided in the end surface of the first insulatingfilm 152 located on thesubstrate 10, and aconcave portion 256 is provided in the end surface of the first insulatingfilm 252 located on thesubstrate 10. Theconcave portion 156 is deeper than theconcave portion 256. Theetching stopper film 30 intrudes into both of theconcave portions - Meanwhile, contact plugs 42, 44, and 46 are buried in the insulating
interlayer 40. In addition, an insulating film amonginterconnects 41 is formed on the insulatinginterlayer 40.Interconnects contact plug 42 is connected to theinterconnect 50 and one side of the source and drainregions 140 of thefirst transistor 100. Thecontact plug 44 is connected to thebit line 310 and one side of the source and drainregions 240 of thesecond transistor 200, and thecontact plug 46 is connected to a lower electrode of thecapacitive element 300 and the other side of the source and drainregions 240 of thesecond transistor 200. - Meanwhile, an device
isolation insulating film 20 is formed in thesubstrate 10. The deviceisolation insulating film 20 is disposed to isolate each of thefirst transistor 100 and thesecond transistor 200 from others. -
FIGS. 2A and 2B toFIGS. 4A and 4B are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the embodiment. In the method of manufacturing the semiconductor device, first, the firstgate insulating film 110 and thefirst gate electrode 120 of thefirst transistor 100, and the secondgate insulating film 210 and thesecond gate electrode 220 of thesecond transistor 200 are formed on thesubstrate 10. Next, theextension region 130 of thefirst transistor 100 and theextension region 230 of thesecond transistor 200 are formed. Meanwhile, an impurity implantation process for forming theextension region 130 is performed using a process separate from the impurity implantation process for forming theextension region 230. Next, thefirst sidewall 150 is formed in the sidewall of thefirst gate electrode 120, and thesecond sidewall 250 having a larger width than that of thefirst sidewall 150 is formed in the sidewall of thesecond gate electrode 220. Next, the source and drainregion 240 of thesecond transistor 200 is formed. Next, thecapacitive element 300 which is connected to the source and drainregion 240 is formed. Hereinafter, a detailed description will be given. - First, as shown in
FIG. 2A , the deviceisolation insulating film 20 is formed in thesubstrate 10 by, for example, a Shallow Trench Isolation (STI) method. Next, the firstgate insulating film 110 and the secondgate insulating film 210 are formed in thesubstrate 10 by the same process. Subsequently, a conductive film, for example, a polysilicon film is formed on the whole surface including the upper portions of the firstgate insulating film 110 and the secondgate insulating film 210. The thickness of this conductive film is, for example, equal to or greater than 30 nm and equal to or less than 180 nm. Next, the conductive film is selectively removed. Thereby, thefirst gate electrode 120 and thesecond gate electrode 220 are formed. Meanwhile, thefirst gate electrode 120 and thesecond gate electrode 220 need not be polysilicon gates, and may be formed of, for example, silicides such as a nickel silicide, or metals. - Next, ion implantation is performed using the device
isolation insulating film 20, thefirst gate electrode 120, and thesecond gate electrode 220 as a mask. Thereby, theextension region 130 of thefirst transistor 100 and theextension region 230 of thesecond transistor 200 are formed in a self-aligning manner. - Next, as shown in
FIG. 2B , a firstinsulating film 500 and a secondinsulating film 502 are in this order formed on thesubstrate 10, the deviceisolation insulating film 20, thefirst gate electrode 120, and thesecond gate electrode 220. The firstinsulating film 500 is, for example, a silicon nitride film, and the secondinsulating film 502 is a silicon oxide film. - The thickness of the first insulating
film 500 is, for example, equal to or greater than 3 nm and equal to or less 10 nm, and the thickness of the secondinsulating film 502 is, for example, equal to or greater than 10 nm and equal to or less than 100 nm. - Next, as shown in
FIG. 3A , the secondinsulating film 502 and the first insulatingfilm 500 are etched. As this etching, for example, dry etching is initially performed, and then wet etching is performed. Thereby, thefirst sidewall 150 and thesecond sidewall 250 are formed. Theconcave portions substrate 10 in the first insulatingfilm 152 of thefirst sidewall 150 and the first insulatingfilm 252 of thesecond sidewall 250. In the state shown in the same drawing, cross-sectional shapes of thefirst sidewall 150 and thesecond sidewall 250 are substantially equal to each other. In addition, the depths of theconcave portions - After that, as shown in
FIG. 3B , amask film 520 is formed on thesubstrate 10. Themask film 520 is, for example, a resist film, and covers the region in which thefirst transistor 100 is formed, but does not cover the region in which thesecond transistor 200 is formed. Next, ion implantation is performed using themask film 520, the deviceisolation insulating film 20, thesecond gate electrode 220, and thesecond sidewall 250 as a mask. Thereby, the source and drainregion 240 of thesecond transistor 200 is formed. - After that, as shown in
FIG. 4A , themask film 520 is removed. Next, amask film 530 is formed on thesubstrate 10. Themask film 530 is, for example, a resist film, and covers the region (including thesecond gate electrode 220 and the second sidewall 250) in which thesecond transistor 200 is formed, but does not cover the region (including thefirst gate electrode 120 and the first sidewall 150) in which thefirst transistor 100 is formed. - Next, etching is performed using the
mask film 530 as a mask. Thereby, thefirst sidewall 150 is etched, and decreases in width. This etching process includes a wet etching process. For this reason, theconcave portion 156 is deepened. - Next, as shown in
FIG. 4B , ion implantation is performed using themask film 530, the deviceisolation insulating film 20, thefirst gate electrode 120, and thefirst sidewall 150 as a mask. Thereby, the source and drainregion 140 of thefirst transistor 100 is formed. - After that, the
mask film 530 is removed. Thereafter, as shown inFIG. 1 , theetching stopper film 30, the insulatinginterlayer 40, thecapacitive element 300, the contact plugs 42, 44, and 46, the insulating film amonginterconnects 41, and theinterconnects etching stopper film 30 among processes of forming them, a portion of theetching stopper film 30 intrudes into theconcave portions - Next, the action and advantages of the embodiment will be described. According to the embodiment, the width of the
second sidewall 250 of thesecond transistor 200 is larger than the width of thefirst sidewall 150 of thefirst transistor 100. For this reason, the width of theextension region 230 of thesecond transistor 200 is larger than the width of theextension region 130 of thefirst transistor 100. Therefore, it is possible that while the on-state current of thefirst transistor 100 is raised by decreasing the substantial gate length of thefirst transistor 100, the leak current of thesecond transistor 200 is lowered by increasing the substantial gate length of thesecond transistor 200. For this reason, the holding time of information in thecapacitive element 300 can be prolonged. - In addition, the
etching stopper film 30 intrudes into theconcave portion 156 of thefirst sidewall 150 and theconcave portion 256 of thesecond sidewall 250, respectively. Theconcave portion 156 is deeper than theconcave portion 256. For this reason, stress generated from theetching stopper film 30 is easily applied to a channel region of thefirst transistor 100. Therefore, the driving current of thefirst transistor 100 is increased. -
FIGS. 5A and 5B toFIG. 7 are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a second embodiment. The method of manufacturing the semiconductor device is the same as the method of manufacturing the semiconductor device shown in the first embodiment, with the exception of the formation timing of thefirst sidewall 150 and thesecond sidewall 250. In addition, the semiconductor device manufactured by the embodiment is the same as that of the first embodiment, with the exception that there is a case where the depth of theconcave portion 156 is small. - First, as shown in
FIG. 5A , the deviceisolation insulating film 20 is formed in thesubstrate 10, and the firstgate insulating film 110 and secondgate insulating film 210, thefirst gate electrode 120 and thesecond gate electrode 220, theextension regions film 500 and the secondinsulating film 502 are further formed therein. The method of forming them is the same as that of the first embodiment. - Next, as shown in
FIG. 5B , themask film 530 is formed in thesubstrate 10. Themask film 530 is, for example, a resist film, and covers the region (including the second gate electrode 220) in which thesecond transistor 200 is formed, but does not cover the region (including the first gate electrode 120) in which thefirst transistor 100 is formed. - Next, first insulating
film 500 and secondinsulating film 502 are etched using themask film 530 as a mask. Thereby, thefirst sidewall 150 is formed. - Next, as shown in
FIG. 6A , ion implantation is performed using themask film 530, the deviceisolation insulating film 20, thefirst gate electrode 120, and thefirst sidewall 150 as a mask. Thereby, the source and drainregion 140 used as a source and a drain of thefirst transistor 100 is formed. - After that, as shown in
FIG. 6B , themask film 530 is removed. Next, themask film 520 is formed on thesubstrate 10. Themask film 520 is, for example, a resist film, and covers the region (including thefirst gate electrode 120 and the first sidewall 150) in which thefirst transistor 100 is formed, but does not cover the region (including the second gate electrode 220) in which thesecond transistor 200 is formed. - Next, the first insulating
film 500 and the secondinsulating film 502 are etched using themask film 520 as a mask. Thereby, thesecond sidewall 250 is formed. At this time, the width of thesecond sidewall 250 is made larger than the width of thefirst sidewall 150 by adjusting etching conditions. - Next, as shown in
FIG. 7 , ion implantation is performed using themask film 520, the deviceisolation insulating film 20, thesecond gate electrode 220, and thesecond sidewall 250 as a mask. Thereby, the source and drainregion 240 used as a source and a drain of thesecond transistor 200 is formed. - After that, the
mask film 520 is removed. Next, theetching stopper film 30, the insulatinginterlayer 40, thecapacitive element 300, the contact plugs 42, 44, and 46, the insulating film amonginterconnects 41, and theinterconnects FIG. 1 . - It is also possible to obtain the same advantages as those of the first embodiment by the embodiment.
- In addition, the logic circuit includes a densely-packed pattern and an isolated pattern, and the DRAM is formed only by a densely-packed pattern in many cases. In anisotropic etching for forming the sidewall, the etching rate in the isolated pattern of the logic circuit is slower than that of the densely-packed pattern. For this reason, it is often the case that the optimum time of etching in the logic circuit is longer than the optimum time of etching in the DRAM.
- When the sidewall is formed by the same etching process in the logic circuit and the DRAM circuit, and the etching time is set to the optimum time of etching in the DRAM, the insulating film used as a sidewall in the logic circuit remains in a portion other than the sidewall. On the other hand, when the etching time is set to the optimum time of etching in the logic circuit, the etching amount of the substrate becomes larger in the DRAM and thus a defect occurs in the source and drain region. This defect causes the leak current from the capacitive element and thus the data retention characteristics of the DRAM are deteriorated.
- On the other hand, since the
first sidewall 150 and thesecond sidewall 250 are formed by a separate process in the embodiment, the etching conditions for forming each of them can be set to each of the optimum conditions. For this reason, it is possible to suppress the generation of the above-mentioned problems. -
FIGS. 8A to 8D ,FIGS. 9A to 9D , andFIG. 10 are cross-sectional views illustrating a method of manufacturing the semiconductor device according a third embodiment. Thecapacitive element 300 and theinterconnects - First, as shown in
FIG. 8A , the deviceisolation insulating film 20 is formed in thesubstrate 10, and the firstgate insulating film 110 and the secondgate insulating film 210, and thefirst gate electrode 120 and thesecond gate electrode 220 are further formed. A method of forming them is the same as that of the first embodiment. Next, an offsetspacer film 122 is formed in the sidewall of thefirst gate electrode 120, and an offsetspacer film 222 is formed in the sidewall in thesecond gate electrode 220. Next, impurities are implanted in thesubstrate 10 using thefirst gate electrode 120, thesecond gate electrode 220, the deviceisolation insulating film 20, and the offsetspacer films extension regions extension region 130 is performed using a process separate from the impurity implantation process for forming theextension region 230. Next, the first insulatingfilm 500 is formed. In the embodiment, the first insulatingfilm 500 is, for example, a silicon nitride film. - Next, as shown in
FIG. 8B , the secondinsulating film 502 is formed on the first insulatingfilm 500. In the embodiment, the secondinsulating film 502 is formed of materials different from theetching stopper film 30 as described later, and it is possible to raise etching selectivity with respect to theetching stopper film 30. The secondinsulating film 502 is, for example, a silicon oxide film, and is thicker than the first insulatingfilm 500. - Next, as shown in
FIG. 8C , amask film 540 is formed on the secondinsulating film 502. Themask film 540 does not cover a portion located on thefirst gate electrode 120 in the secondinsulating film 502, but covers a portion located on thesecond gate electrode 220. Next, the secondinsulating film 502 is wet-etched using themask film 540 as a mask. Thereby, a portion located on thefirst gate electrode 120 and on the periphery thereof in the secondinsulating film 502 is removed, and the secondinsulating film 502 is formed on thesecond gate electrode 220 and on the periphery thereof. - Next, as shown in
FIG. 8D , a thirdinsulating film 504 used as a sidewall is formed on the secondinsulating film 502, and thefirst gate electrode 120 and the periphery thereof. The thirdinsulating film 504 is formed of the same materials as those of the secondinsulating film 502. - Next, as shown in
FIG. 9A , the thirdinsulating film 504 located on thefirst gate electrode 120 and on the periphery thereof is covered with a mask film 550. The mask film 550 does not cover the thirdinsulating film 504 located on thesecond gate electrode 220 and on the periphery thereof. In addition, the mask film 550 covers a portion near the region where thesecond transistor 200 is formed in the deviceisolation insulating film 20. - Next, the third
insulating film 504 and the secondinsulating film 502 are etched using the mask film 550 as a mask, and the first insulatingfilm 500 is further etched. In etching at this time, anisotropic dry etching is used. Thereby, thesecond sidewall 250 is formed. In this process, the surface of a portion which is not covered with the mask film 550 in the deviceisolation insulating film 20 is etched. Thereby, astep difference 22 is formed in the deviceisolation insulating film 20. - After that, as shown in
FIG. 9B , the mask film 550 is removed. Next, the region where theextension region 230 is formed in thesecond gate electrode 220, thesecond sidewall 250, and thesubstrate 10 is covered with amask film 560. Themask film 560 does not cover the thirdinsulating film 504 located on thefirst gate electrode 120 and on the periphery thereof. In addition, themask film 560 covers a portion near the region where thesecond transistor 200 is formed in the deviceisolation insulating film 20. At this time, the edge of themask film 560 is kept away at a certain distance, for example, 20 nm or more from thestep difference 22. This distance is set to be larger than the sum value of maximum values of the position shift amount of themask films 550 and 560. - Next, the third
insulating film 504 is etched using themask film 560 as a mask, and the first insulatingfilm 500 is further etched. In etching at this time, anisotropic dry etching is used. Thereby, thefirst sidewall 150 is formed. At this time, the width of thefirst sidewall 150 is made narrower than the width of thesecond sidewall 250. - Further, in this process, the surface of a portion which is not covered with the
mask film 560 in the deviceisolation insulating film 20 is etched. As described above, the edge of themask film 560 is kept away at a certain distance from thestep difference 22. For this reason, agroove 24 is formed in the surface of the deviceisolation insulating film 20. - After that, as shown in
FIG. 9C , themask film 560 is removed. Next, the source and drainregions substrate 10. Meanwhile, the ion implantation process for forming the source and drainregion 140 is performed using a process separate from the ion implantation process for forming the source and drainregions 240. - Next, as shown in
FIG. 9D , a silicide forming metal film, for example, Ni or Co is formed in the whole surface including the upper portions of the source and drainregions first gate electrode 120, and thesecond gate electrode 220. Next, the metal film, the source and drainregions first gate electrode 120, and thesecond gate electrode 220 are heat-treated. Thereby,silicide films regions silicide films first gate electrode 120 and thesecond gate electrode 220. After that, the metal film which is not silicidized is removed. Next, theetching stopper film 30 and the insulatinginterlayer 40 are formed. Theetching stopper film 30 is the same material that of the first embodiment, for example, a silicon nitride film. - Next, as shown in
FIG. 10 , a mask pattern (not shown) is formed on the insulatinginterlayer 40, and the insulatinginterlayer 40 and theetching stopper film 30 are etched using this mask pattern as a mask. Thereby, a contact hole connected to the source and drainregion 140 is formed. Next, thecontact plug 42 is formed by burying a conductor, for example, a metal such as Cu within this contact hole. Meanwhile, in this process, the contact plugs 44 and 46 shown inFIG. 1 are also formed, but are not shown in the same drawing. Thecapacitive element 300, the insulating film amonginterconnects 41, and theinterconnects FIG. 1 are formed. -
FIG. 11 is a plan view illustrating a state before theetching stopper film 30 and the insulatinginterlayer 40 are formed in the semiconductor device shown inFIG. 9D . In the process of forming thefirst gate electrode 120 and thesecond gate electrode 220, agate interconnect 400 is formed on the deviceisolation insulating film 20. Thegate interconnect 400 is formed of an extraction interconnect of thesecond gate electrode 220, and is connected to thesecond gate electrode 220. In the process of forming thesilicide films silicide film 402 is also formed in the surface layer of thegate interconnect 400. Meanwhile, thegate interconnect 400 lies across thegroove 24. - According to the embodiment, it is also possible to obtain the same advantages as those of the first embodiment. In addition, the second
insulating film 154 in which the surface layer of thefirst sidewall 150 is formed is formed by materials different from those of theetching stopper film 30, and this can raise etching selectivity with respect to theetching stopper film 30. - When the whole
first sidewall 150 cannot raise etching selectivity with respect to theetching stopper film 30, it is considered that thefirst sidewall 150 is formed only by the first insulatingfilm 152, for example, as shown inFIG. 12 . In this case, when the position of the contact hole for burying thecontact plug 42 is shifted to thereby overlap withfirst sidewall 150, the contact hole passes through thefirst sidewall 150 and thus thecontact plug 42 is connected to theextension region 130. Theextension region 130 is shallow in depth relative to the source and drainregion 140. Therefore, in this case, the leak current of thefirst transistor 100 is increased. - On the other hand, in the embodiment, the second
insulating film 154 in which the surface layer of thefirst sidewall 150 is formed has a high etching selectivity with respect to theetching stopper film 30 as described above. Therefore, even when the position of the contact hole for burying thecontact plug 42 is shifted to thereby overlap with thefirst sidewall 150, the contact hole does not pass through thefirst sidewall 150 and thus the leak current of thefirst transistor 100 is not increased. - In addition, as shown in
FIG. 13 , it is considered that at least one of the mask film 550 and themask film 560 is shifted, and a portion of the thirdinsulating film 504 is covered by both the mask film 550 and themask film 560. In this case, the thirdinsulating film 504 remains in a portion which is covered by both the mask film 550 and themask film 560 in the deviceisolation insulating film 20, and thus a portion of thegate interconnect 400 is caused to be covered by the thirdinsulating film 504. In this case, thesilicide film 402 is not formed in a portion which is covered by the thirdinsulating film 504 in thegate interconnect 400. As a result, resistance of thegate interconnect 400 is increased. - On the other hand, in the embodiment, the edge of the
mask film 560 is kept away at a certain distance, for example, 20 nm or more from thestep difference 22. For this reason, as shown in the plan view ofFIG. 11 , even when at least one of the mask film 550 and themask film 560 is shifted, the thirdinsulating film 504 is not covered by both the mask film 550 and themask film 560 in any of the portions. Therefore, a portion in which thesilicide film 402 is not formed is suppressed from remaining in thegate interconnect 400. - In addition, since the
first sidewall 150 and thesecond sidewall 250 are formed by a separate process, it is possible to set etching conditions for forming each of them to each of the optimum conditions. For this reason, the insulating film for forming the sidewall is suppressed from remaining on thefirst gate electrode 120, thesecond gate electrode 220, or thegate interconnect 400. Therefore, it is possible to form thesilicide films first gate electrode 120, thesecond gate electrode 220, and thegate interconnect 400. -
FIGS. 14A to 14C andFIGS. 15A to 15C are cross-sectional views illustrating a method of manufacturing the semiconductor device according to a fourth embodiment. Hereinafter, the same reference numerals are assigned to the same components as those in the third embodiment, descriptions thereof will not be repeated. - First, as shown in
FIG. 14A , the deviceisolation insulating film 20 is formed in thesubstrate 10, and further formed are the firstgate insulating film 110 and the secondgate insulating film 210, thefirst gate electrode 120 and thesecond gate electrode 220, the offsetspacer films extension regions film 500, and the secondinsulating film 502. A method of forming them is the same as that of the third embodiment. - Next, as shown in
FIG. 14B , the secondinsulating film 502 is etched. In etching at this time, anisotropic dry etching is used. Thereby, asidewall 251 used as a portion of thesecond sidewall 250 is formed on the sidewall of thesecond gate electrode 220. In addition, the secondinsulating film 502 remains on the sidewall of thefirst gate electrode 120, and is used as asidewall 151. - Next, as shown in
FIG. 14C , thesidewall 251 and thesecond gate electrode 220 are covered by amask film 570. Themask film 570 does not cover thefirst gate electrode 120 and thesidewall 151. Next, wet etching is performed using themask film 570 as a mask, and thesidewall 151 is removed. - After that, as shown in
FIG. 15A , themask film 570 is removed. Next, the thirdinsulating film 504 used as a sidewall is formed on the entirety of the surfaces including the upper portions of thefirst gate electrode 120 and the lateral face thereof, thesecond gate electrode 220, and thesidewall 251. - Next, as shown in
FIG. 15B , the thirdinsulating film 504 is etched. In etching at this time, anisotropic dry etching is used. Thereby, thefirst sidewall 150 and thesecond sidewall 250 are formed. - After that, as shown in
FIG. 15C , formed are the source and drainregions silicide films etching stopper film 30, the insulatinginterlayer 40 and thecontact plug 42. And as shown inFIG. 1 , formed are thecapacitive element 300, the insulating film amonginterconnects 41, and theinterconnects - According to the embodiment, it is also possible to obtain the same advantages as those of the first embodiment.
- As described above, although the embodiments of the invention have been set forth with reference to the drawings, they are merely illustrative of the invention, and various configurations other than the foregoing can be adopted.
- It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
Claims (20)
1. A semiconductor device, comprising:
a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall; and
a second transistor, formed in the substrate, that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall,
wherein the first transistor comprises a portion of a logic circuit,
wherein the second transistor comprises a transistor included in a memory cell of a Dynamic Random Access Memory (DRAM), or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM,
wherein the first gate insulating film has a same thickness as that of the second gate insulating film,
wherein the first gate electrode has a same thickness as that of the second gate electrode, and
wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall such that a width of the second sidewall is larger than a width of the first sidewall.
2. The semiconductor device as set forth in claim 1 , wherein the first sidewall and the second sidewall include:
a first insulating film formed over the substrate and over a sidewall of the first gate electrode or the second gate electrode;
a second insulating film formed over the first insulating film; and
a concave portion provided in an end surface of the first insulating film which is located over the substrate, and
wherein a concave portion of the first sidewall is deeper than a concave portion of the second sidewall,
the semiconductor device further comprising:
an etching stopper film, formed over the first transistor and the second transistor, of which a portion intrudes into the concave portion of each of the first sidewall and the second sidewall; and
an insulating interlayer located over the etching stopper film.
3. The semiconductor device as set forth in claim 2 , wherein the etching stopper film comprises one of TEOS, SiO2, SiN, SiON, HDP, PSG, NSG, and BPSG.
4. The semiconductor device as set forth in claim 1 , further comprising:
an etching stopper film formed over the first transistor and the second transistor;
an insulating interlayer located over the etching stopper film; and
a contact which is formed in the insulating interlayer and the etching stopper film, and connected to the source and the drain region of the first transistor,
wherein at least a surface layer of the first sidewall comprises a material different from that of the etching stopper film.
5. The semiconductor device as set forth in claim 4 , wherein the etching stopper film comprises a silicon nitride film, and
wherein at least the surface layer of the first sidewall comprises a silicon oxide film.
6. The semiconductor device as set forth in claim 5 , wherein the first sidewall includes a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in that order.
7. The semiconductor device as set forth in claim 1 , further comprising:
an device isolation film which is buried in the substrate, and is located between the logic circuit and the memory cell;
a gate interconnect which is formed over the device isolation film, and is connected to the second gate electrode;
a silicide film formed over the gate interconnect; and
a groove, formed in the device isolation film, that extends in a direction intersecting the gate interconnect.
8. The semiconductor device as set forth in claim 1 , wherein the width of the first sidewall is equal to or greater than 1 nm and equal to or less than 70 nm, and the width of the second sidewall is equal to or greater than 1.4 nm and equal to or less than 100 nm.
9. A semiconductor device, comprising:
a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode and a first sidewall;
a second transistor, formed in the substrate, that includes a second gate insulating film, a source and a drain region, a second gate electrode and a second sidewall,
wherein the first gate insulating film has a same thickness as that of the second gate insulating film,
wherein the first gate electrode has a same thickness as that of the second gate electrode, and
wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall such that a width of the second sidewall is larger than a width of the first sidewall.
10. A semiconductor device according to claim 9 , wherein the first transistor comprises a portion of a logic circuit, and
wherein the second transistor comprises a transistor included in a memory cell, or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the memory cell.
11. A semiconductor device according to claim 10 , wherein the memory cell comprises a memory cell of a Dynamic Random Access Memory (DRAM).
12. A semiconductor device according to claim 9 , wherein the first sidewall and the second sidewall include:
a first insulating film formed over the substrate and over a sidewall of the first gate electrode or the second gate electrode;
a second insulating film formed over the first insulating film; and
a concave portion provided in an end surface of the first insulating film which is located over the substrate, and
wherein a concave portion of the first sidewall is deeper than a concave portion of the second sidewall,
the semiconductor device further comprising:
an etching stopper film, formed over the first transistor and the second transistor, of which a portion intrudes into the concave portion of each of the first sidewall and the second sidewall; and
an insulating interlayer located over the etching stopper film.
13. A semiconductor device according to claim 12 , wherein the etching stopper film comprises one of TEOS, SiO2, SiN, SiON, HDP, PSG, NSG, and BPSG.
14. A semiconductor device according to claim 9 , further comprising:
an etching stopper film formed over the first transistor and the second transistor;
an insulating interlayer located over the etching stopper film; and
a contact which is formed in the insulating interlayer and the etching stopper film, and connected to the source and the drain region of the first transistor,
wherein at least a surface layer of the first sidewall comprises a material different from that of the etching stopper film.
15. A semiconductor device according to claim 14 , wherein the etching stopper film comprises a silicon nitride film, and
wherein at least the surface layer of the first sidewall comprises a silicon oxide film.
16. A semiconductor device according to claim 15 , wherein the first sidewall includes a laminated structure in which a silicon nitride film and a silicon oxide film are laminated in that order.
17. A semiconductor device according to claim 9 , further comprising:
an device isolation film which is buried in the substrate, and is located between the logic circuit and the memory cell;
a gate interconnect which is formed over the device isolation film, and is connected to the second gate electrode;
a silicide film formed over the gate interconnect; and
a groove, formed in the device isolation film, that extends in a direction intersecting the gate interconnect.
18. A semiconductor device according to claim 9 , wherein the width of the first sidewall is equal to or greater than 1 nm and equal to or less than 70 nm, and the width of the second sidewall is equal to or greater than 1.4 nm and equal to or less than 100 nm.
19. A method of manufacturing a semiconductor device, the method comprising:
forming, on a substrate, a first gate insulating film and a first gate electrode of a first transistor, and a second gate insulating film and a second gate electrode of a second transistor;
forming an extension region of the first transistor and an extension region of the second transistor;
forming a first sidewall in a side wall of the first transistor;
forming a second sidewall having a larger width than that of the first sidewall in a sidewall of the second transistor; and
forming a source and a drain region in each of the first transistor and the second transistor,
wherein a layer structure of the first sidewall is a same as a layer structure of the second sidewall in the semiconductor device.
20. A method of manufacturing a semiconductor device according to claim 19 , wherein the first transistor comprises a portion of a logic circuit, and
wherein the second transistor comprises a transistor included in a memory cell of a Dynamic Random Access Memory (DRAM), or comprises a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM.
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US10505018B2 (en) * | 2013-12-05 | 2019-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacers with rectangular profile and methods of forming the same |
US10868143B2 (en) * | 2013-12-05 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spacers with rectangular profile and methods of forming the same |
US20160190318A1 (en) * | 2014-12-30 | 2016-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
CN105742282A (en) * | 2014-12-30 | 2016-07-06 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
CN111261646A (en) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | Image sensor, semiconductor device and forming method thereof |
US11736831B2 (en) | 2018-11-30 | 2023-08-22 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device and method of manufacture |
Also Published As
Publication number | Publication date |
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JP2011066391A (en) | 2011-03-31 |
US20110042749A1 (en) | 2011-02-24 |
US8309414B2 (en) | 2012-11-13 |
JP5578952B2 (en) | 2014-08-27 |
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