JPH04102368A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce an area of a memory cell and to improve step coverage of an upper layer wiring by making an insulating film on a gate electrode of a peripheral circuit part thinner than a memory cell part and by providing a sidewall to a side part of the gate electrode and the insulating film. CONSTITUTION:A sidewall 16 is formed at a side part of a gate electrode 14 of a transistor 13 and an insulating film 15 on the gate electrode 14 in a semiconductor memory. The insulating film 15 on the gate electrode 14 is thicker than a peripheral circuit part 12 in a memory cell part 11. Therefore, self-matching contact with an N<->-layer 23 is possible in the memory cell part 11 while ensuring interlaminar breakdown strength. Meanwhile, since the insulating film 15 on the gate electrode 14 is thinner than the memory cell part 11 in the peripheral circuit part 12, a step produced bar the insulating film 15 and the gate electrode 14 is small and a width L of a sidewall at a side part thereof is narrow, thereby reducing an area and improving step coverage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory having a memory cell section and a peripheral circuit section.

1 invention 4 already required.

The present invention provides that, in a semiconductor memory Q as described above, the insulating film on the gate electrode of the transistor in the peripheral circuit section is made smaller than the insulating film on the gate electrode of the transistor in the memory cell section. Although it is possible to reduce the memory cell area by forming sidewalls on the sides of the electrodes and insulating film, it is possible to reduce the memory cell area, but in the peripheral circuit area, the step coverage of the upper layer wiring is good and the characteristics of the transistor are also excellent. This is what I did.

[Prior art] In semiconductor memory, in order to reduce the memory cell area,
A self-aligned contact technique is used.

Figure 4 shows a stacked capacitor DRA using this technology.
A conventional example of M is shown, and this conventional example has a memory cell section 11 and a peripheral circuit section 12.

Polycrystalline Si 114 which is the gate electrode of transistor 13
A 5iOz film 15 is laminated thereon, and a SiO□ film 1 is deposited on these polycrystalline Si film 14 and SiO□ film 15.
A side wall six membranes wide is provided.

The capacitive element 17 of the memory cell section 11 is made up of a polycrystalline Si film 18 that is a storage node, a dielectric film 21, and a polycrystalline Si film 22 that is a plate electrode. The polycrystalline Si film 18 is connected to an N − diffusion layer 23a, which is one source/drain region of the transistor 13, via a contact hole 24.

The contact hole 24 is formed in a self-aligned manner by etching a portion of the interlayer insulating SiO□ film 25 above the N- diffusion layer 23a.

Therefore, the 5iOz film 15 is used as an offset to ensure the interlayer breakdown voltage between the polycrystalline Si films 14 and 18 even if the contact hole 24 is formed in a self-aligned manner.

[Problem to be solved by the invention]

However, although the self-aligned contact technique is not used in the peripheral circuit section 12, the SiO□ film 15 for offset is also provided in this peripheral circuit section.

Therefore, the step difference H between the polycrystalline Si film 14 and the SiO2 film 15 is large, and the step coverage of the l wiring 26 is poor.

Further, since the step H is large, the film width 6 of the SiO□ film 16 is also wider than necessary for the transistor 13 of the peripheral circuit section 12. Therefore, the characteristics of the transistor 13 in the peripheral circuit section 12 are also deteriorated.

[Means for Solving the Problems] In the semiconductor memory according to the present invention, the insulating film 15 on the gate electrode 14 of the transistor 13 in the peripheral circuit section 12 or the insulating film on the gate electrode 14 of the transistor 13 in the memory cell section 11 15, the peripheral circuit section 12
and the gate electrode 14 in the memory cell section 11
A side wall 16 is formed on the side of the insulating film 15.

[Function] Semiconductor memo according to the present invention 1. ] (Yo, transistor 1
The gate electrode 14 of No. 3 and the insulating film 1 on this gate electrode 14
5 and the side wall 16 is formed, but the insulation II on the gate electrode 14! ii! l5 is the peripheral circuit section 12
It is thicker in the memory cell portion 11 than in the memory cell portion 11. Therefore, in the memory cell portion 11, self-aligned contact is possible while ensuring interlayer breakdown voltage.

On the other hand, in the peripheral circuit section 12, the insulating film 1 on the gate electrode 14
5 is thinner than the memory cell portion 11, this insulating film 15
The difference in level caused by the gate electrode 14 is small, and the width of the side wall of these side parts is also narrow.

〔Example〕

Hereinafter, first to third embodiments of the present invention applied to a stacked capacitance type DRAM will be described with reference to FIGS. 1 to 3.

FIG. 1 shows the steps for manufacturing the first embodiment. In this manufacturing process, as shown in FIG. 1A, a SiO□ film 28 for element isolation is formed on the surface of the Si substrate 27, and the area covered with this SiO□ film 28 is used as an element formation region 31. .

Next, S10. which becomes the gate insulating film. A film 32 is formed on the surface of the element forming region 31, and is further laminated on the polycrystalline Si film 14 for gate electrode, the SiO□ film 33, the SIN film 34, and the SiO□ film 15 for offset.

Then, the 5i02 film 15 in the peripheral circuit section 12 is removed.

Next, as shown in FIG. 1B, the resist 35 is patterned to form the gate insulating film.
The 5iOz film 15, the SiN film 34, the SiO□ film 33, and the polycrystalline Si film 14 are patterned using the same method.

Note that when the four-layer film is patterned using the resist 35 in this way, the first
As shown in Figure B, the resist 35 has receded.

However, in this manufacturing process, the 5iO7 film 33 and SiN
If the film 34 is provided, the polycrystalline S1 film 14 can be patterned after the resist 35 is removed by using the films 33 and 34 patterned before the resist 35 retreats as a mask. Therefore, the 5iOz film 33 and S
The iN film 34 is not necessarily required.

Thereafter, impurities are introduced into the element formation region 31 using the polycrystalline Si film 14 etc. as a mask, thereby forming N- diffusion layers 23a to 23d.

Next, as shown in FIG. 1C, side walls with a width of 6 and a width of 6 of the SiO□ film 16 are formed on the sides of the polycrystalline Si film 14 and the like by etching the entire surface of the SiO□ film 16 with a width of 6.

Then, only in the peripheral circuit section 12, by introducing impurities into the element formation region 31 using the polycrystalline Si film 14, the 5iOz film 16, etc. as masks, the N diffusion layers 36c, 3
Form 6d. In the process up to this point, the memory cell section 11
A transistor 13 was formed in both the peripheral circuit section 12 and the peripheral circuit section 12 .

Next, as shown in FIG. 1D, a SiO□ film 25 is deposited over the entire surface, and the resist 37 is further patterned to have an opening 37a only on the N- diffusion layer 23a of the memory cell portion 11.

Next, by etching the SiO□ film 25 using the resist 37 as a mask, an N-
A contact hole 24 for a storage node of a capacitive element is formed in a self-aligned manner with respect to the diffusion layer 23a.

Thereafter, capacitive elements, focus lines, etc. are formed by the same steps as in the conventional example shown in FIG.

In the first embodiment manufactured as described above, the peripheral circuit section 1
In the transistor 13 of No. 2, an SiO□ film 15 for offset is provided on the polycrystalline Si film 14 serving as the gate electrode.
It has not been done. Therefore, as is clear from FIG. 1E, the step caused by the polycrystalline S1 film 14, etc.
The width 6 of the SiO□ film 16 is also narrower than the width in the memory cell portion 11.

In this way, in this first embodiment, the 5iOz film 15 was completely removed in the peripheral circuit section 12, but the SiO□ film 1
It is effective to simply make the 5-film structure 5 thinner in the peripheral circuit portion 12 than in the memory cell portion 11.

FIG. 2 shows the final steps for manufacturing the second embodiment. Even in this manufacturing process, as shown in FIGS. 2A and 2B, up to the formation of the N- diffusion layers 23a to 23d, 540 □
The manufacturing process is substantially the same as that of the first embodiment described above, except that the film 33 and the SiN film 34 are not formed.

Next, after depositing 16 SiO□ films on the entire surface with a width of 6D,
By etching and hacking only this SiO□ film 16 and circuit portion 12, a side wall having a width of 6 and a width of SiO□ film 16 is formed only on the polycrystalline S1 film 14 of the peripheral circuit portion 12.

Then, by introducing impurities only into the element formation region 31 of the peripheral circuit section 12 with a film width of 6 squares for the polycrystalline Si film 14 and SiO□ film 16, the N diffusion layers 36c, 36d
form.

Thereafter, the S+Oz film 38, the SiN film 39, and the SiO□ film 41 are sequentially deposited by CVD, and the SiO□ film 41 is removed only in the peripheral circuit section 12. Incidentally, when the SiO□ film 41 is removed, the SiN film 39 serves as an etching stopper.

Next, as shown in FIG. 2C, Si is used only in the peripheral circuit section 12.
The N film 39 is removed. However, since this is to relieve the stress caused by the S+N film 39, removal is not necessarily necessary.

Second, only in the memory cell portion 11 is the SiO□ film 41, Si
By sequentially etching and hacking the N' film 39 and the S+Oz film 38.16, the sidewalls made of these films are removed from the polycrystalline Si film 14 and the SO□ film 154 of the memory cell section 11.
Form only this.

Next, as shown in FIG. 2D, a SiO□ film 25 and a SiN film 42 are sequentially deposited over the entire surface, and a resist with a pattern similar to the resist 37 shown in FIG. By etching the SiN film 42 and the SiO□ film 25, a contact hole 24 for the N- diffusion layer 23a is formed in a self-aligned manner.

Then, the capacitive element 17 is formed by patterning the polycrystalline Si film 18 into a memory note pattern, covering the polycrystalline Si film 18 with a dielectric film 21, and patterning the polycrystalline Si film 22 into a plate electrode pattern. do.

Note that the impurity contained in the polycrystalline 5jui18 is Si
Solid-phase diffusion is performed into the substrate 27 to form an N'' diffusion layer 36a within the N- diffusion layer 23a.

Thereafter, a BPSG film 43 is deposited over the entire surface by CVD, a portion of the BPSG film 43 corresponding to the peripheral circuit section 12 is removed, and the BPSG film 43 is reflowed in this state.

Next, as shown in FIG. 2E, a contact hole 44 for the N- diffusion layer 23b is opened in the BPSG film 43, etc., and the polycrystalline Si film 45 is patterned into a hit line pattern.

At this time as well, the impurity contained in the polycrystalline Si film 45 is solid-phase diffused into the Si substrate 27, and an N'' diffusion layer 36b is formed in the N- diffusion layer 23b.

Thereafter, a BPSG film 46 is deposited over the entire surface, and a contact hole 47 for the N° diffusion layer 36c is opened in the BPSG film 46 and the like. Then, in this state, the BPSG film 46 is reflowed, and the 〇 wiring 26 is formed by sputtering and patterning.

In the second embodiment manufactured as described above, the peripheral circuit section 1
Since the 5iOz film 15 is not provided on the polycrystalline Si film 14 of No. 2 and is removed from the 1-circuit portion 12 for the SiO It is smaller than the step H. Moreover, the BPSG film 43 is also removed from the peripheral circuit section 12.

Therefore, as is clear from the comparison between FIG. 2E and FIG. 4, the step coverage of the A42 wiring 26 is good in this second embodiment.

Even if the 5iO7 film 41 is removed from the peripheral circuit section 12 in this second embodiment, it is used only for forming the sidewalls of the polycrystalline Si film 14, etc. in the 1 recell section 11 for this SiO□ film 41 film. Therefore, there is no particular inconvenience.

Further, even if the BPSG film 43 is removed in the peripheral circuit section 12, the capacitor element 17 and the bit line are not present in the peripheral circuit section 12, and the polycrystalline Si film 22 serving as the plate electrode and the polycrystalline Si film serving as the bit line 45 is also insulated using polycrystalline S1 film 45.
There is no particular problem because flattening is not necessary.

Note that in this second embodiment as well, 5 in the peripheral circuit section 12
The width p of the in2 film 16 is the width p of the SiO
□Membrane 16 Narrower than membrane width 6.

By the way, in the above-mentioned first and second embodiments, the sidewalls made of the polycrystalline Si film 14, etc., which are the gate electrodes, and the 5iOz film 16, etc., were formed, or the sidewalls were formed by RIE when forming the sidewalls. As a result, crystal defects may occur in the S1 substrate 27, or a dislocation network may spread from the end of the side wall.

As a result, a leakage current is generated in the transistor 13, which may deteriorate the data retention characteristics of the memory cell.

For this reason, as shown in FIG.
A structure without side walls is being considered.

However, in this structure, in the memory cell section ]1,
Between the polycrystalline Si film 14 that is the gate electrode and the polycrystalline Si film 18 that is the memory note, two layers of S are provided as an insulating film between the eyebrows.
There are 16 iO□ films and 6 film widths.

For this reason, there are problems such as the interlayer insulating film is thick, stress becomes large, and conversely induces crystal defects in the Si substrate 27, and the large step difference makes it difficult to process the upper layer wiring.

FIG. 3 shows the process of manufacturing a third embodiment that solves these problems. In this manufacturing process, after patterning the polycrystalline S1 film 14 into the pattern of the gate electrode of the transistor 13, the diffusion layers 23a to 23d are formed.

Then, the SiO□ film 16 is deposited on the entire surface with a width of 6D, and then the SiN film 48 is deposited on the entire surface under reduced pressure C to 'D.

Next, the SiN film 48 and the SiO□ film 16 film width 6 sides circuit portion 1
2, the polycrystalline Si film 14 of the peripheral circuit section 12 is coated with 5iOz as shown in FIG. 3B.
A side wall of membrane 16 is formed.

Then, using the 5in2 film 16 as a mask, the N diffusion layer 36 is
After forming the 5102 film 25 on the entire surface, only the SiO□ film 25 in the memory cell portion 11 is removed by etching with phosphoric acid. At this time, 1g of SiN
448 becomes an etching stopper.

Next, as shown in FIG. 3C, the contact hole 24 for the N- diffusion layer 23a is made six holes wide by the SiO□ film 16, and the polycrystalline Si film 18 is patterned in the pattern of the storage node of the capacitive element.

Thereafter, plate electrodes of capacitive elements, bit lines, etc. are formed by the same steps as in the conventional example shown in FIG. 4.

In the third embodiment manufactured as described above, the SiO□ film 25 is removed from the memory cell portion 11, so even though the sidewalls on the SiO□ film 16 are not formed in the memory cell portion 11, Regardless, the interlayer insulating film between the polycrystalline Si films 14 and 18 is thin.

In addition, when manufacturing this third embodiment, the SiO□ film 16
Although the SiN film 48 was formed on the film 6, this SiN film 48
By forming 6 on the SiO□ film 16, the thickness of the interlayer insulating film in the memory cell portion 11 can be further reduced.

[Effects of the Invention] In the semiconductor memory according to the present invention, since self-aligned contact is possible in the memory cell portion while ensuring interlayer breakdown voltage, the memory cell area can be reduced.
In the peripheral circuit area, the level difference between the gate electrode and the insulating film on it is small, so the level difference coverage of the upper layer wiring is good.Furthermore, in the peripheral circuit area, the width of the sidewall of the side part of the gate electrode, etc. is narrow, so the characteristics of the transistor are also excellent. There is.

[Brief explanation of drawings]

1 to 3 are side sectional views sequentially showing manufacturing steps of first to third embodiments of the present invention, respectively. 4 and 5 are side sectional views of a conventional example and another conventional example of the present invention, respectively. In addition, in the reference numerals used in the drawings, 1 t-----Memory cell section 12-
−−−−−−−−−−−Peripheral circuit section 13−−−−−11−
---=) Rangemetal 14 --- Polycrystalline Si films 15 and 16 ----=-5iO□ film.

Claims (1)

[Claims] A semiconductor memory having a memory cell section and a peripheral circuit section, wherein an insulating film on a gate electrode of a transistor in the peripheral circuit section is thinner than an insulating film on a gate electrode of a transistor in the memory cell section. . A semiconductor memory, wherein side walls are formed on sides of the gate electrode and the insulating film in the peripheral circuit section and the memory cell section.