TWI672797B - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure and a method of fabricating the same. The semiconductor structure includes a substrate, a first gate, a second gate, a first spacer, and a second spacer. The first gate and the second gate are on the substrate. The first spacer is formed on the plurality of sidewalls of the first gate and includes a first gap inner layer, a first etch barrier layer and a first gap outer layer, the first etch barrier layer has an L-shaped cross section, and An etch barrier layer is formed between the first gap inner layer and the first gap outer layer. The second spacer is formed on the plurality of sidewalls of the second gate and includes a second gap inner layer, a second etch barrier layer and a second gap outer layer, the second etch barrier layer has an L-shaped cross section, and A second etch barrier layer is formed between the second gap inner layer and the second gap outer layer. A thickness of the second spacer is greater than a thickness of the first spacer.

Description

Semiconductor structure and method of manufacturing same

The present disclosure relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having a low voltage component and a high voltage component and a method of fabricating the same.

With the miniaturization and complication of semiconductor devices, high-voltage components and low-voltage logic components are usually disposed in a single device at the same time. However, based on the operating principle of the two components, the structure and manufacturing process are also quite different. In order to achieve the best performance of these two components in a single device, the industry is committed to developing process methods and performance to improve such devices.

The disclosure relates to a semiconductor structure and a method of fabricating the same. In an embodiment, the thickness of the second spacer in the high voltage region of the semiconductor structure is greater than the thickness of the first spacer in the low voltage region, so that the electric field in the region between the gate and the drain region in the high voltage region can be reduced, and the improvement is improved. The gate-induced drain leakage current occurs in the region where the gate and the drain overlap in the negative gate bias. The effect of (GIDL)), in turn, can achieve the effect of maintaining the processing speed of the low pressure region and the breakdown voltage of the high voltage region.

In accordance with an embodiment of the present disclosure, a semiconductor structure is proposed. The semiconductor structure includes a substrate, a first gate, a second gate, a first spacer, and a second spacer. The first gate and the second gate are on the substrate. The first spacer is formed on the plurality of sidewalls of the first gate and includes a first gap inner layer, a first etch barrier layer and a first gap outer layer, the first etch barrier layer has an L-shaped cross section, and An etch barrier layer is formed between the first gap inner layer and the first gap outer layer. The second spacer is formed on the plurality of sidewalls of the second gate and includes a second gap inner layer, a second etch barrier layer and a second gap outer layer, the second etch barrier layer has an L-shaped cross section, and A second etch barrier layer is formed between the second gap inner layer and the second gap outer layer. A thickness of the second spacer is greater than a thickness of the first spacer.

In accordance with another embodiment of the present disclosure, a method of fabricating a semiconductor structure is presented. The manufacturing method of the semiconductor structure includes the steps of: providing a substrate; forming a first gate and a second gate on the substrate; and forming a first spacer and a second spacer respectively at the first gate On the sidewalls and on the plurality of sidewalls of the second gate. The first spacer includes a first gap inner layer, a first etch barrier layer and a first gap outer layer, wherein the first etch barrier layer has an L-shaped cross section, and the first etch barrier layer is formed in the first gap inner layer Between the outer layer of the first gap. The second spacer includes a second gap inner layer, a second etch barrier layer and a second gap outer layer, wherein the second etch barrier layer has an L-shaped cross section, and the second etch barrier layer is formed in the second gap inner layer Between the outer layer of the second gap. A thickness of the second spacer is greater than a thickness of the first spacer.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10, 20‧‧‧ semiconductor structure

100‧‧‧Substrate

200‧‧‧first gate

210, 310‧‧‧ side walls

300‧‧‧second gate

400‧‧‧First spacer

400t, 410t, 420t, 430t, 500t, 510t, 520t, 530t, 600t, 700t, 830t, 840t‧ ‧ thickness

410‧‧‧The first gap inner layer

420‧‧‧First etch barrier

430‧‧‧ first gap outer layer

440, 540‧‧‧ nitride layer

500‧‧‧Second spacer

510‧‧‧Second gap inner layer

520‧‧‧second etch barrier

530‧‧‧ second gap outer layer

600‧‧‧First gate dielectric layer

700‧‧‧Second gate dielectric layer

810‧‧‧Internal spacer material

820‧‧‧etching barrier material

830‧‧‧First outer spacer material

840‧‧‧Second outer spacer material

I, II, III, IV‧‧‧ curves

M‧‧‧Photo Mask

FIG. 1 is a schematic diagram of a semiconductor structure of an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a semiconductor structure of an embodiment of the present disclosure.

3A-3E are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

FIG. 4 is a graph showing a base current-gate voltage (Ib-Vg) of a semiconductor structure according to an embodiment of the present disclosure and a comparative example.

FIG. 5 is a graph showing a drain current-drain voltage (Id-Vd) of a semiconductor structure according to an embodiment of the present disclosure and a comparative example.

In the embodiments disclosed herein, a semiconductor structure and a method of fabricating the same are presented. In an embodiment, the thickness of the second spacer in the high voltage region of the semiconductor structure is greater than the thickness of the first spacer in the low voltage region, so that the electric field in the region between the gate and the drain region in the high voltage region can be reduced, and the improvement is improved. The GIDL effect can further achieve the effect of maintaining the processing speed of the low voltage region and the breakdown voltage of the high voltage region. However, the embodiments and the corresponding drawings are only intended to be illustrative, and are not intended to limit the scope of the invention. Further, elements having the same reference numerals in the drawings and the description of the invention are the same. In addition, it should be noted that the dimensional ratios on the drawings are not necessarily drawn to the scale of the actual products, and therefore are not intended to limit the scope of the present invention. use. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. In addition, the drawings in the embodiments are omitted in order to clearly show the technical features of the present invention.

FIG. 1 is a schematic diagram of a semiconductor structure 10 in accordance with an embodiment of the present disclosure. As shown in FIG. 1 , the semiconductor structure 10 includes a substrate 100 , a first gate 200 , a second gate 300 , a first spacer 400 , and a second spacer 500 . The first gate 200 and the second gate 300 are located on the substrate 100. The first spacer 400 is formed on the plurality of sidewalls 210 of the first gate 200, and the first spacer 400 includes a first interlayer inner layer 410, a first etch barrier layer 420, and a first gap outer layer 430. The first etch stop layer 420 has an L-shaped cross section, and the first etch stop layer 420 is formed between the first gap inner layer 410 and the first gap outer layer 430. The second spacer 500 is formed on the plurality of sidewalls 310 of the second gate 300, and the second spacer 500 includes a second gap inner layer 510, a second etch barrier layer 520, and a second gap outer layer 530. The second etch stop layer 520 has an L-shaped cross section, and the second etch stop layer 520 is formed between the second gap inner layer 510 and the second gap outer layer 530. The thickness 500t of the second spacer 500 is greater than the thickness 400t of the first spacer 400.

In an embodiment, the thickness 500t of the second spacer 500 is, for example, greater than about 80% of the thickness 400t of the first spacer 400. For example, the thickness 500t of the second spacer 500 is, for example, about 1400 angstroms (Å), and the thickness 400t of the first spacer 400 is, for example, about 860 angstroms.

In an embodiment, the semiconductor structure 10 is, for example, a semiconductor device having a low voltage component and a high voltage component, and the low voltage component region can be configured, for example, as a logic component. For example, the semiconductor structure 10 may be a driver integrated circuit of a display panel (driver) IC). In the semiconductor structure 10 of the embodiment, the first gate 200 is located in the low voltage region and the second gate 300 is located in the high voltage region.

According to an embodiment of the present disclosure, the thickness 500t of the second spacer 500 in the high voltage region is greater than the thickness 400t of the first spacer 400 in the low voltage region, so that the high voltage region can be lowered between the gate and the drain region. The electric field in the region reduces the occurrence of leakage current and improves the effect of gate-induced drain leakage current (GIDL) occurring in the region where the gate and the drain overlap when the negative gate bias is applied, thereby further improving the high voltage region. The breakdown voltage.

Still further, in the semiconductor structure 10 of the embodiment, the second spacer 500 of the high voltage region has a relatively large thickness of 500t, and the first spacer 400 of the low voltage region remains at a predetermined thinner thickness 400t. Since the low voltage region mainly processes the logic signal, if the first spacer 400 in the low voltage region has a too large thickness, the resistance of the region is too high, especially when the signal amount is large, the processing of the components in the low voltage region is seriously affected. speed. Therefore, according to an embodiment of the present disclosure, the effect of retaining the speed of the low pressure region and the breakdown voltage of the high voltage region can be achieved by designing the spacers of different regions through different thicknesses.

As shown in FIG. 1, the thickness 530t of the second gap outer layer 530 is greater than the thickness 430t of the first gap outer layer 430. In one embodiment, the difference between the thickness 530t of the second gap outer layer 530 and the thickness 430t of the first gap outer layer 430 is, for example, greater than 0 angstroms to about 1800 angstroms. In one embodiment, the ratio of the thickness 530t of the second gap outer layer 530 to the thickness 430t of the first gap outer layer 430 is, for example, greater than 0 to about 3.5. For example, in one embodiment, the thickness 530t of the second gap outer layer 530 is, for example, about 1150 angstroms, and the thickness 430t of the first gap outer layer 430 is, for example, about 650 angstroms.

In the embodiment, as shown in FIG. 1, the thickness 510t of the second interstitial inner layer 510 is the same as the thickness 410t of the first interstitial inner layer 410, for example. For example, in one embodiment, the thickness 510t of the second interstitial layer 510 and the thickness 410t of the first interstitial inner layer 410 are, for example, about 100 angstroms.

In the embodiment, as shown in FIG. 1, the thickness 520t of the second etch barrier layer 520 is the same as the thickness 420t of the first etch barrier layer 420, for example. For example, in one embodiment, the thickness 520t of the second etch stop layer 520 and the thickness 420t of the first etch stop layer 420 are, for example, about 200 angstroms.

As shown in FIG. 1, the first gap inner layer 410 and the second gap inner layer 420 have, for example, an L-shaped cross section.

In one embodiment, the first gap outer layer 430 and the second gap outer layer 530 comprise an oxide layer, and the first etch stop layer 420 and the second etch stop layer 520 comprise a nitride layer. For example, the first gap outer layer 430 and the second gap outer layer 530 are both ruthenium oxide layers, and the first etch barrier layer 420 and the second etch barrier layer 520 are both tantalum nitride layers. In the embodiment, the first interstitial inner layer 410 and the second interstitial inner layer 420 are both, for example, a ruthenium oxide layer.

As shown in FIG. 1 , the semiconductor structure 10 further includes a first gate dielectric layer 600 and a second gate dielectric layer 700 . The first gate dielectric layer 600 is formed between the first gate 200 and the substrate 100, and the second gate dielectric layer 700 is formed between the second gate 300 and the substrate 100. In the semiconductor structure 10 of the embodiment, the first gate 200 is located in the low voltage region, and the second gate 300 is located in the high voltage region, and the thickness 700t of the second gate dielectric layer 700 is greater than the thickness of the first gate dielectric layer 600 by 600t. .

FIG. 2 is a schematic diagram of a semiconductor structure 20 in accordance with an embodiment of the present disclosure. In the embodiment, the same or similar components as the foregoing embodiments are used together. For similar or similar components, please refer to the foregoing for related descriptions of the same or similar components, and details are not described herein again.

As shown in FIG. 2, in one embodiment, the first gap outer layer 430 and the second gap outer layer 530 comprise a nitride layer, and the first etch stop layer 420 and the second etch stop layer 520 comprise an oxide layer. In one embodiment, the first interstitial inner layer 410 and the second interstitial inner layer 510 are each, for example, a ruthenium oxide layer.

For example, in an embodiment, the first gap outer layer 430 and the second gap outer layer 530 are both tantalum nitride layers, and the first etch stop layer 420 and the second etch stop layer 520 are both tantalum nitride layers.

As shown in FIG. 2, in an embodiment, the first spacer 400 further includes a nitride layer 440, and the nitride layer 440 is located between the first gap inner layer 410 and the first etch barrier layer 420, and the nitride layer 440 is, for example, a tantalum nitride layer; the second spacer 500 further includes a nitride layer 540, the nitride layer 540 is between the second interstitial layer 510 and the second etch stop layer 520, and the nitride layer 540 is, for example, nitrogen.矽 layer.

3A-3E are schematic views showing a method of fabricating a semiconductor structure 10 in accordance with an embodiment of the present invention. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 3A, a substrate 100 is provided to form a first gate 200 and a second gate 300 on the substrate 100.

Moreover, as shown in FIG. 3A, a first gate dielectric layer 600 is formed between the first gate 200 and the substrate 100, and a second gate dielectric layer 700 is formed on the second gate 300 and the substrate 100. Between the thickness of the second gate dielectric layer 700 The degree 700t is greater than the thickness 600t of the first gate dielectric layer 600. In the embodiment, the first gate dielectric layer 600 and the second gate dielectric layer 700 are formed on the substrate 100, and then the first gate electrode 200 and the second gate electrode 300 are formed on the first gate dielectric layer 600. And on the second gate dielectric layer 700.

Next, as shown in FIG. 3A, an inner spacer material 810, an etch stop material 820, and a first outer spacer material 830 are formed. In an embodiment, the inner spacer material 810 covers the first gate 200 and the second gate 300, the etch stop material 820 is formed on the inner spacer material 810, and the first outer spacer material 830 is formed on the etch barrier material 820. on. As shown in FIG. 3A, the inner spacer material 810 also covers the first gate dielectric layer 600 and the second gate dielectric layer 700 and the surface of the substrate 100, and the etch barrier material 820 covers the inner spacer material 810. And the first outer spacer material 830 covers the etch stop material 820.

In an embodiment, the inner spacer material 810 and the first outer spacer material 830 are, for example, a cerium oxide (SiO ₂ ) film, and tetraethoxy decane (TEOS) can be used as a raw material to form an inner layer gap by a deposition process. Material 810 and first outer spacer material 830.

Next, as shown in FIGS. 3B-3C, a portion of the first outer spacer material 830 located above the first gate 200 is removed by a wet etching process. This wet process has high selectivity for the first outer spacer material 830 and the etch stop material 820, thus etching only the first outer spacer material 830 and stopping the surface of the etch barrier material 820.

In detail, as shown in FIG. 3B, a mask M is disposed above the second gate 300, and then removed as shown in FIG. 3C by the wet etching process and exposed to the mask M. Part of the first outer gap material above the gate 200 Material 830, leaving a portion of the first outer spacer material 830 above the second gate 300.

Next, as shown in FIG. 3D, a second outer spacer material 840 is formed to cover the first gate 200 and the second gate 300. In detail, a second outer spacer material 840 is formed on the etch stop material 820 over the first gate 200 and on a portion of the first outer spacer material 830 above the second gate 300.

In an embodiment, the second outer spacer material 840 is, for example, a ruthenium dioxide film, and the second outer spacer material 840 can be formed by a deposition process using tetraethoxy decane as a raw material.

In an embodiment, the ratio of the thickness 840t of the second outer spacer material 840 to the thickness 830t of the first outer spacer material 830 is, for example, 0.5 to 2. For example, in one embodiment, the thickness 830t of the first outer spacer material 830 is, for example, about 500 angstroms, and the thickness 840t of the second outer spacer material 840 is, for example, about 650 angstroms.

Next, as shown in FIG. 3E, a portion of the inner spacer material 810, the etch barrier material 820, and the first outer spacer material between the first gate 200 and the second gate 300 are removed by a dry etching process. 830 and a second outer spacer material 840 are formed to form a first spacer 400 and a second spacer 500 on the sidewall 210 of the first gate 200 and the sidewall 310 of the second gate 300, respectively. Thus far, the semiconductor structure 10 as shown in Fig. 3E (Fig. 1) is formed.

According to the manufacturing method of the embodiment of the present disclosure, only one dry etching process is required, and spacers of different thicknesses of the high pressure region and the low pressure region can be defined. Furthermore, by adjusting the thickness 830t of the first outer spacer material 830 and the thickness 840t of the second outer spacer material 840, according to the actual semiconductor structure The thickness of the gap between the high pressure zone and the low pressure zone is easily adjusted to meet the requirements of the device to optimize the performance.

A method of fabricating a semiconductor structure 20 in accordance with another embodiment of the present invention is described below. Please refer to Fig. 2 and Fig. 3A to Fig. 3E at the same time.

First, referring to FIG. 2 and FIG. 3A, after forming the inner spacer material 810 and before forming the etching stopper material 820, a nitride material layer may be formed on the inner spacer material 810, and then formed. The barrier material 820 is etched onto the layer of nitride material. In other words, this layer of nitride material is between the inner spacer material 810 and the etch stop material 820.

Next, referring to FIGS. 3B-3D, a portion of the first outer spacer material 830 located above the first gate 200 is removed by a wet etching process, and a second outer spacer material 840 is formed to cover the first gate. The pole 200 and the second gate 300.

Next, referring to FIGS. 2 and 3E, a portion of the inner spacer material 810, the etch barrier material 820, and the first outer gap between the first gate 200 and the second gate 300 are removed by a dry etching process. The material 830 and the second outer spacer material 840 also remove a portion of the nitride material layer between the first gate 200 and the second gate 300 to form a nitride layer of the first spacer 400, respectively. 440 and a nitride layer 540 of the second spacer 500. Thus far, the semiconductor structure 20 as shown in FIG. 2 can be formed.

4 is a graph showing a base current-gate voltage (Ib-Vg) of a semiconductor structure according to an embodiment of the present disclosure and a comparative example, and FIG. 5 is a diagram showing an embodiment of the present disclosure and a A graph of the gate current-drain voltage (Id-Vd) of the semiconductor structure of the comparative example. In Figures 4 through 5, curves I and III represent the results measured from the semiconductor structure 10 of the embodiment, and curves II and IV represent self-comparisons. The results of the semiconductor structure measurements. The semiconductor structure 10 of the embodiment and the semiconductor structure of the comparative example are both semiconductor devices having high voltage elements. In the semiconductor structure of the comparative example, the spacers on the sidewalls of the two gates respectively located in the high voltage region and the low voltage region have the same thickness. In the semiconductor structure 10 of the embodiment, the first gate 200 is located in the low voltage region and the second gate 300 is located in the high voltage region. The doping conditions of the drain/source regions of both the semiconductor structure 10 of the embodiment and the semiconductor structure of the comparative example are the same. Figures 4 through 5 show the measured results in the high pressure zone.

As shown in Fig. 4, as can be seen from curves I and II, the base current of the semiconductor structure 10 of the embodiment is significantly lower than the base current of the semiconductor structure of the comparative example by about 30%. Since the doping conditions of the semiconductor structure 10 of the embodiment and the drain/source regions of the semiconductor structure of the comparative example are the same, the effect of the junction should be close. In other words, the base current of the semiconductor structure 10 of the embodiment can be greatly reduced compared to the semiconductor structure of the comparative example, apparently because the spacer of the high voltage region has a large thickness, and the spacer of a larger thickness reduces the high voltage. The electric field effect of the drain/source region of the region.

As shown in Fig. 5, the GIDL effect can be greatly reduced by lowering the electric field in the high voltage region. In Fig. 5, for example, when the drain current is 10 pA, the drain voltage of the semiconductor structure 10 of the embodiment can be greatly increased compared to the semiconductor structure of the comparative example which can withstand a drain voltage of -13V. To -15.5V. As a result, the reduction of the GIDL effect and the electric field drop in the vicinity of the drain electrode can further increase the breakdown voltage of the components in the high voltage region.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. Those skilled in the art to which the invention pertains can make various changes and changes without departing from the spirit and scope of the invention. Decoration. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (18)

A semiconductor structure includes: a substrate; a first gate and a second gate on the substrate; a first gate dielectric layer formed between the first gate and the substrate; and a a second gate dielectric layer is formed between the second gate and the substrate, wherein a thickness of the second gate dielectric layer is greater than a thickness of the first gate dielectric layer; a first gap a spacer formed on the plurality of sidewalls of the first gate, the first spacer comprising: a first gap inner layer; a first etch barrier layer; and a first gap outer layer, wherein the first spacer The etch stop layer has an L-shaped cross section, and the first etch stop layer is formed between the first gap inner layer and the first gap outer layer; and a second spacer is formed on the plurality of the second gate The second spacer includes: a second gap inner layer; a second etch barrier layer; and a second gap outer layer, wherein the second etch barrier layer has an L-shaped cross section, and the second etch barrier a layer formed between the second gap inner layer and the second gap outer layer; wherein the second A thickness of the spacer is greater than a thickness of the first spacer. The semiconductor structure of claim 1, wherein the second A thickness of the outer layer of the gap is greater than a thickness of the outer layer of the first gap. The semiconductor structure of claim 2, wherein the difference between the thickness of the second gap outer layer and the thickness of the first gap outer layer is greater than 0 Å to 1800 Å. The semiconductor structure of claim 2, wherein the ratio of the thickness of the second gap outer layer to the thickness of the first gap outer layer is greater than 0 to 3.5. The semiconductor structure of claim 1, wherein a thickness of the second gap inner layer is the same as a thickness of the first gap inner layer. The semiconductor structure of claim 1, wherein a thickness of the second etch barrier layer is the same as a thickness of the first etch barrier layer. The semiconductor structure of claim 1, wherein the first gap inner layer and the second gap inner layer each have an L-shaped cross section. The semiconductor structure of claim 1, wherein the first gap outer layer and the second gap outer layer comprise an oxide layer, and the first etch barrier layer and the second etch barrier layer comprise a nitride layer. The semiconductor structure of claim 1, wherein the first The outer layer of the gap and the outer layer of the second gap comprise a nitride layer, and the first etch stop layer and the second etch stop layer comprise an oxide layer. A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a first gate and a second gate on the substrate; forming a first gate dielectric layer between the first gate and the substrate Forming a second gate dielectric layer between the second gate and the substrate, wherein a thickness of the second gate dielectric layer is greater than a thickness of the first gate dielectric layer; and forming a The first spacer and the second spacer are respectively on the plurality of sidewalls of the first gate and the plurality of sidewalls of the second gate; wherein the first spacer comprises a first gap inner layer, a first spacer An etch barrier layer and a first gap outer layer, wherein the first etch barrier layer has an L-shaped cross section, and the first etch barrier layer is formed between the first gap inner layer and the first gap outer layer; The second spacer includes a second gap inner layer, a second etch stop layer and a second gap outer layer, wherein the second etch stop layer has an L-shaped cross section, and the second etch stop layer is formed on the second Between the inner layer of the gap and the outer layer of the second gap; and wherein the A spacer thickness greater than a thickness of the first spacer. The method of fabricating a semiconductor structure according to claim 10, wherein the forming the first spacer and the second spacer comprises: forming an inner spacer material covering the first gate and the second gate ; Forming an etch stop material on the inner spacer material; and forming a first outer spacer material on the etch stop material. The method of manufacturing the semiconductor structure of claim 11, wherein the forming the first spacer and the second spacer further comprises: removing the first portion above the first gate by a wet etching process A portion of an outer spacer material. The method of fabricating a semiconductor structure according to claim 12, wherein the forming the first spacer and the second spacer further comprises: forming a second outer spacer material covering the first gate and the second Gate. The method of fabricating a semiconductor structure according to claim 13, wherein a ratio of a thickness of the second outer spacer material to a thickness of the first outer spacer material is 0.5 to 2. The method of manufacturing the semiconductor structure of claim 13, wherein the forming the first spacer and the second spacer further comprises: removing the first gate and the second gate by a dry etching process a portion of the inner spacer material, the etch stop material, the first outer spacer material, and the second outer spacer material between the poles to form the sidewalls of the first gate and the first The first spacer and the second spacer on the sidewalls of the two gates. The method of fabricating a semiconductor structure according to claim 10, wherein a thickness of the second gap outer layer is greater than a thickness of the first gap outer layer. The method of fabricating a semiconductor structure according to claim 10, wherein the first interstitial inner layer and the second interstitial inner layer each have an L-shaped cross section. The method of fabricating a semiconductor structure according to claim 10, wherein the first gap outer layer and the second gap outer layer comprise an oxide layer, and the first etch barrier layer and the second etch barrier layer comprise a nitrogen Chemical layer.