TW201442120A - Semiconductor device and method for forming the same - Google Patents

Abstract

A semiconductor device is disclosed. The semiconductor device includes an isolation structure is formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate corresponding to the field plate region. The step gate dielectric structure includes a first layer of a first dielectric material and a second layer of the dielectric material vertically laminating each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material. A method for forming a semiconductor device is also disclosed.

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a high voltage semiconductor device having a shallow trench isolation (STI) and a method of fabricating the same.

At present, the power management integrated circuit (PMIC) is most commonly used in a bipolar-CMOS (complementary metal oxide semiconductor transistor)-bipolar-CMOS (complementary metal oxide semiconductor transistor)- Structure of LDMOS (lateral diffused metal oxide semiconductor transistor, BCD). Complementary metal oxide semiconductor transistors (CMOS) are used in digital circuits, bipolar transistors can drive high currents, and laterally diffused metal oxide semiconductor transistors (LDMOS) have high voltages (HV). Processing power. The trend of power saving and high-speed performance affects the structure of laterally diffused metal oxide semiconductor transistors. The semiconductor industry continues to develop low leakage current and low-on-resistance (RDSon) laterally diffused metal oxide semiconductors. Transistor.

LDMOS devices have now developed various structures that can be widely used in everyday applications and can withstand high off-state breakdown. However, the on resistance of the conventional LDMOS device (on resistance, Ron) can't be lowered. On-resistance is an important factor affecting the power loss of conventional MOS field effect transistor (MOSFET) devices. The above results increase the ratio of the on-resistance to the drain-source breakdown voltage (Ron/BVdss ratio), which in turn affects the reliability of the BCD process.

Accordingly, there is a need in the art for a novel semiconductor device and method of fabricating the same to improve the above disadvantages.

One embodiment of the present invention provides a semiconductor device. The semiconductor device includes an isolation structure disposed in the substrate to define an active region of the substrate, wherein the active region has a field region; a differential gate dielectric structure, the substrate located in the field plate region The above-mentioned stepped gate dielectric structure comprises a first layer of a first dielectric material and a second layer of a first dielectric material stacked vertically to each other; a second layer of dielectric material, wherein the first dielectric material The first layer and the second layer of the first dielectric material are separated from each other by the second dielectric material layer, and the etching rate of the second dielectric material layer to an etchant is different from the first dielectric material The etching rate of the second layer to the above etchant.

Another embodiment of the present invention provides a method of fabricating a semiconductor device. The method for manufacturing a semiconductor device includes: providing a substrate; sequentially forming a first dielectric material first layer and a second dielectric material layer on a surface of the substrate; and patterning the first dielectric material first layer And the second dielectric material layer; the first layer of the first dielectric material and the second dielectric material layer are patterned as a hard mask layer, and a part of the substrate is removed to form in the substrate An insulating trench; forming an insulating structure in the isolated trench to define An active region of the substrate; a second layer of a first dielectric material is formed in a comprehensive manner; and a mask pattern is formed on the second layer of the first dielectric material in the active region to define in the active region a plate region; performing an etching process to remove the second layer of the first dielectric material not covered by the mask pattern to form a second layer pattern of the first dielectric material, wherein the second dielectric material layer As an etch stop layer of the etching process; removing the patterned first dielectric material first layer and the second dielectric material layer not covered by the second dielectric material second layer pattern A differential gate dielectric structure is formed on the substrate in the field plate region.

200‧‧‧Substrate

201‧‧‧ surface

202‧‧‧First layer of first dielectric material

204‧‧‧Second dielectric material layer

206‧‧‧hard cover layer

208‧‧‧Isolated trench

209‧‧‧ side wall

210‧‧‧Isolated structure

212, 214, 216‧‧‧ doped areas

218‧‧‧First wiring doping area

220‧‧‧Second wiring doping area

221‧‧‧Second layer of first dielectric material

222‧‧‧Second layer pattern of first dielectric material

223‧‧‧ mask pattern

224‧‧ ‧ differential gate dielectric structure

226‧‧‧ gate dielectric layer

228‧‧ ‧ gate layer

230‧‧‧ gate structure

232‧‧‧ lining

234‧‧‧ dielectric materials

300‧‧‧active area

302‧‧‧Field area

500‧‧‧Semiconductor device

T1, T2‧‧‧ height

W1, W2‧‧‧ width

Fig. 1 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1 showing a cross-sectional view of the semiconductor device according to an embodiment of the present invention along the longitudinal direction of the channel.

Fig. 3 is a cross-sectional view taken along line B-B' of Fig. 1 showing a cross-sectional view of the semiconductor device according to an embodiment of the present invention in the width direction of the channel.

4-5, 6a, and 7a are cross-sectional views taken along line A-A' of Fig. 1, which show a process sectional view of a semiconductor device according to an embodiment of the present invention.

6b and 7b are cross-sectional views taken along line B-B' of Fig. 1, showing a process sectional view of a semiconductor device according to an embodiment of the present invention.

In order to make the objects, features, and advantages of the present invention more comprehensible, the detailed description of the embodiments and the accompanying drawings. The present specification provides various embodiments to illustrate the techniques of various embodiments of the present invention. Characteristics. The arrangement of the various elements in the embodiments is for illustrative purposes and is not intended to limit the invention. The overlapping portions of the drawings in the embodiments are for the purpose of simplifying the description and are not intended to be related to the different embodiments.

Embodiments of the present invention provide a semiconductor device. In this embodiment, the semiconductor device can be a P-type bipolar-complementary metal oxide semiconductor transistor-bipolar-CMOS (complementary metal oxide semiconductor transistor)-LDMOS (lateral diffused Metal oxide semiconductor transistor), BCD). Embodiments of the present invention utilize a hard mask layer that is formed to form an isolation structure (eg, STI), an additional deposition process, and an additional lithography/etch process to form a substrate in the field plate region of the substrate. A differential gate dielectric structure on the surface replaces the shallow trench isolation field plate structure in the conventional HV device. Therefore, compared with the conventional high voltage device, the current path from the drain to the source can be further shortened to further reduce the on-resistance and maintain a high breakdown voltage, thereby reducing the lateral MOS transistor device. Power loss.

1 is a top plan view showing a semiconductor device 500 according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1 showing a cross-sectional view of the semiconductor device 500 according to an embodiment of the present invention along the longitudinal direction of the channel. Fig. 3 is a cross-sectional view taken along line B-B' of Fig. 1 showing a cross-sectional view of the semiconductor device 500 according to an embodiment of the present invention in the width direction of the channel. In this embodiment, the semiconductor device 500 can be a P-type bipolar-complementary metal oxide semiconductor transistor-bipolar-CMOS (complementary metal oxide semiconductor). Transistor) - LDMOS (lateral diffused metal oxide semiconductor transistor), BCD). As shown in FIGS. 1-3, in an embodiment of the invention, the semiconductor device 500 includes a substrate 200, an isolation structure 210, and a differential gate dielectric structure 224. The isolation structure 210 is located within the substrate 200 to define an active region 300 of the substrate 200, and the active region 300 has a field plate region 302 therein. Additionally, the stepped gate dielectric structure 224 is located on the substrate 200 within the field plate region 302. In an embodiment of the invention, the stepped gate dielectric structure 224 includes a first dielectric material first layer 202 and a first dielectric material second layer 222 stacked perpendicularly to each other, and the stepped gate dielectric structure 224 is further A second dielectric material layer 204 is included. In an embodiment of the invention, the first dielectric material first layer 202 and the first dielectric material second layer 222 are separated from each other by the second dielectric material layer 204.

As shown in FIG. 1-3, in an embodiment of the invention, the semiconductor device 500 further includes a first doped region 216 located in the active region 300 between the field plate region 302 and the isolation structure 210, wherein the first The conductivity type of the doped region 216 is opposite to the conductivity type of the substrate 200 within the active region 300. A second doped region 212 is disposed in the substrate 200 within the active region 300, wherein the second doped region 212 surrounds the first doped region 216, and wherein the first doped region 216 and the second doped region 212 have opposite The type of conductivity. A third doped region 214 is disposed within the substrate 200 outside the active region 300 and surrounds the isolation structure 210, wherein the first doped region 216 and the third doped region 214 have the same conductivity type. A gate structure 230 is disposed on the substrate 200 within the active region 300 and extends from the first doped region 216 to the stepped gate dielectric structure 224.

In an embodiment of the invention, the first dielectric material first layer 202 and the second dielectric material layer 204 formed of different materials may be etched to form an isolation structure 210 such as a shallow trench isolation (STI). Hard cover. In addition, in this issue In the first embodiment, the second layer 222 of the first dielectric material and the first layer 202 of the dielectric material are formed of the same material. Therefore, the second dielectric material layer 204 of the stepped gate dielectric structure 224 can be formed as described above. An etch stop layer of the etching process of the step gate dielectric structure 224.

4-5, 6a, and 7a are cross-sectional views taken along line A-A' of Fig. 1, showing a process sectional view of a semiconductor device 500 according to an embodiment of the present invention. 6b and 7b are cross-sectional views taken along line B-B' of Fig. 1, showing a process sectional view of a semiconductor device 500 according to an embodiment of the present invention. Please refer to FIGS. 1 and 4 at the same time. First, a substrate 200 is provided. In an embodiment of the invention, the substrate 200 can be a germanium substrate. In other embodiments, silicon germanium (SiGe), bulk semiconductor, strained semiconductor, compound semiconductor, silicon on insulator (SOI), Or other commonly used semiconductor substrates. The substrate 200 can be implanted with P-type or N-type impurities to change its conductivity type for design needs. In an embodiment of the invention, the conductivity type of the substrate 200 is P-type.

Then, referring to FIGS. 1 and 4 at the same time, a first dielectric material layer 202 and a second dielectric material layer 204 are sequentially formed on the surface 201 of the substrate 200 by using a deposition process. In an embodiment of the invention, the first layer 202 of the first dielectric material can be viewed as a pad oxide 202 and the second layer of dielectric material 204 can be viewed as a tantalum nitride layer 204. In an embodiment of the invention, the first dielectric material first layer 202 and the second dielectric material layer 204 are collectively considered as a hard mask layer 206 that subsequently forms an etch process of the isolation structure 210.

Next, please refer to the first and fourth figures at the same time, and the lithography and etching process can be used to pattern the hard mask layer 206 to define the formation of the subsequent isolation structure. The surface 201 of the substrate 200 is exposed and exposed. Then, an etching process is performed, and the exposed mask 200 is etched by using the hard mask layer 206 as an etch hard mask of the above etching process to form the isolation trench 208 in the substrate 200. Next, a liner 232 can be formed on the sidewall 209 of the isolation trench. Thereafter, a high density plasma chemical vapor deposition (HDPCVD) process is performed to form, for example, a high-density plasma (HDP) oxide on the hard mask layer 206. Electrical material 234 is filled into isolation trench 208.

Next, please refer to FIGS. 1 and 5 at the same time, and the excess dielectric material 234 on the second dielectric material layer 204 can be removed and planarized by a planarization process such as chemical mechanical polish (CMP). The surfaces of the dielectric material 234 and the second dielectric material layer 204 are such as to form an isolation structure 210 such as a shallow trench isolation (STI) in the isolation trench 208. The isolation structure 210 extends from the surface 201 of the substrate 200 into the substrate 200, and the top surface of the isolation structure 210 is aligned with the top surface of the second dielectric material layer 204. In the present embodiment, the isolation structure 210 defines the position of an active region 300 of the substrate 200.

Then, referring to the first, sixth, and sixth embodiments, a doping region 212 can be formed in the substrate 200 in the active region 300 by using an ion implantation method, wherein the conductivity type of the doping region 212 can be electrically conductive with the substrate 200. The type is reversed and the dopant concentration of the doped region 214 can be, for example, greater than the dopant concentration within the substrate 200. In this embodiment, the doping region 212 can be regarded as an n-type drift doped region 212 as a channel region and a source region of the final semiconductor device. ).

Then, referring to the first, sixth, and sixth embodiments, a doping region 214 is formed in the substrate 220 outside the active region 300 by using an ion implantation method, wherein the doping region 214 surrounds the isolation structure 210 and the doping region. The side boundary of 212, but the bottom boundary of doped region 212 is not surrounded by doped region 214. In the present embodiment, the doping region 214 may have the same conductivity type as the substrate 200, and the doping concentration of the doping region 214 may be greater than, for example, the dopant concentration in the substrate 200. In this embodiment, the doped region 214 can be regarded as a PW doped region. In an embodiment of the invention, the process sequence of the doping regions 212 and 214 is not limited, and the process sequence may be interchanged arbitrarily.

Then, referring to the first, sixth, and sixth embodiments, a doped region 216 is formed in the substrate 220 in the active region 300 by ion implantation. In this embodiment, the doped region 216 will be located within the active region 300 between the isolation structure 210 and the field plate region 302 defined by subsequent processes. In the present embodiment, the boundary of the doping region 216 is surrounded by the doping region 212, and the conductivity type of the doping region 216 is opposite to that of the substrate 200 (ie, the doping region 216 and the doping region 212 have opposite conductivity). Type, and doped region 216 has the same conductivity type as doped region 214). In an embodiment of the invention, the doped region 216 can be considered as a p-type drift region 216, which serves as a drain region of the semiconductor device. In an embodiment of the present invention, an annealing process is preferably performed after the doping region 216 is formed to make the dopant of the doping region 216 laterally diffused and have a concentration gradient.

Next, please refer to the figures 1, 6a, and 6b at the same time, and form a comprehensive method by chemical vapor deposition (CVD) or atomic layer CVD (ALD). the first A second layer 221 of dielectric material. In this embodiment, the second layer 221 of the first dielectric material may be a high temperature oxide (HTO). In an embodiment of the invention, the thickness of the second layer 221 of the first dielectric material formed by the above-described CVD or ALD) method can be well controlled according to design requirements. In an embodiment of the invention, the thickness of the second layer 221 of the first dielectric material may be much greater than the total thickness of the hard mask layer 206, and the thickness of the first layer 202 of the first dielectric material is less than the thickness of the first dielectric material. The thickness of the second layer 221 . In this embodiment, the first layer 202 of the first dielectric material and the second layer 221 of the first dielectric material may be designed to be the same material, and the second layer 221 of the first dielectric material and the second dielectric material may be designed. Layer 204 is a different material.

Then, referring to the first, sixth, and sixth embodiments, a lithography process is performed to form a mask pattern 223 on the second layer 221 of the first dielectric material in the active region 300. The mask pattern 223 is The formation position of the exit plate area 302 is defined.

Then, referring to the first, seventh, and seventh embodiments, the mask pattern 223 is used as an etching mask, and an etching process such as an anisotropic etching process is performed to remove the first dielectric not covered by the mask pattern 223. The second layer 221 of material (as shown in Figures 6a, 6b). In an embodiment of the present invention, since the first dielectric material second layer 221 and the second dielectric material layer 204 are made of different materials, the second dielectric material layer 204 etches an etchant used in the etching process. The rate may be different from the etch rate of the second layer 221 of the first dielectric material to the etchant, so that the etching process proceeds until the surface of the second dielectric material layer 204 is exposed. After the etching process, a first dielectric material second layer pattern 222 is formed, wherein the second dielectric material layer 204 serves as an etch stop layer of the etching process.

Next, please refer to the first, second, and third figures at the same time, for example, a wet One etching process of the etching process to remove the patterned first dielectric material first layer 202 and second dielectric material layer 204 (hard mask layer 206) that are not covered by the first dielectric material second layer pattern 222 Until the surface 201 of the substrate 200 is exposed, a differential gate dielectric structure 224 is formed on the substrate 200 within the field plate region 302. In an embodiment of the invention, the stepped gate dielectric structure 224 includes a patterned first dielectric material first layer 202 and a second dielectric material layer 204 (patterned hard mask layer 206) and is patterned. A second layer pattern 222 of a first dielectric material on the second dielectric material layer 204. In this embodiment, the stepped gate dielectric structure 224 is an oxide-nitride-oxide (ONO) composite structure, wherein the first layer 202 of the patterned first dielectric material is a pad oxide layer. A dielectric material second layer pattern 222 is a high temperature oxide layer, and the patterned second dielectric material layer 204 is a tantalum nitride layer.

Next, please refer to FIGS. 1, 2, and 3 at the same time to illustrate the manner in which the gate structure 230, the first wiring doping region 218, and the second wiring doping region 220 are formed. The substrate 200 in the active region 300 may be formed by, for example, thermal oxidation, chemical vapor deposition (CVD) or atomic layer CVD (ALD). A gate dielectric layer 226 is deposited thereon. Gate dielectric layer 226 can include conventional dielectric materials such as oxides, nitrides, oxynitrides, oxycarbides, or combinations thereof. The gate dielectric layer 224 may also include aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), hafnium oxynitride (HfON), hafnium silicate (HfSiO _{4 ).} Zirconium oxide (ZrO ₂ ), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO ₄ ), yttrium oxide (Y ₂ O ₃ ), lanthanum oxide High dielectric constant (L ₂ O ₃ ), cerium oxide (CeO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ) or a combination thereof A dielectric material having a dielectric constant greater than 8). Next, a gate layer 228 can be formed on the gate dielectric layer 226 by a thin film deposition method such as chemical vapor deposition (CVD). The gate layer 228 includes germanium or polysilicon. Gate layer 228 is preferably doped with dopants to reduce its sheet resistance. In other embodiments, the gate layer 228 comprises amorphous silicon.

Next, please refer to the first, second, and third figures at the same time, and comprehensively cover a patterned photoresist layer (not shown) to define the formation position of the gate structure 230, and then use an anisotropic etching method. A portion of the gate dielectric layer 226 and the gate layer 228 are removed to form a gate structure 230 on the substrate 200 in the active region 300. Thereafter, the patterned photoresist layer is removed. As shown in FIGS. 1, 2, and 3, in an embodiment of the invention, the gate structure 230 extends from the doped region 216 to the stepped gate dielectric structure 224. In the present embodiment, the gate structure 230 covers a portion of the doped region 216 and a portion of the stepped gate dielectric structure 224, and the top doped region 216 and the portion of the stepped gate dielectric structure 224 are gated from the gate structure. 230 exposed.

Then, referring to the first, second, and third figures, an ion implantation step may be performed to form the first wiring doping region 218 in the partially doped region 212, respectively. A further ion implantation step is performed to form a second wiring doping region 220 in the partially doped region 216. In an embodiment of the invention, the conductivity type of the first wiring doping region 218 is the same as the conductivity type of the doping region 212, and the conductivity type of the second wiring doping region 220 is the same as that of the doping region 216. In the present embodiment, the first wiring doping region 218 can be regarded as an n-type drift doping region (N-type body of the semiconductor device). The wiring-up region of the region 212 has a conductivity type such as an n-type. In addition, the second wiring doping region 220 can be regarded as a source of a semiconductor device and a pick-up region of a p-type drift region 216, and the conductivity type is preferably p. type. After the above process, the semiconductor device 500 of one embodiment of the present invention is formed.

As shown in the first, second, and third figures, the semiconductor device 500 replaces the conventional high voltage device as a field plate structure by using a stepped gate dielectric structure 224 formed on the substrate 100 in the field plate region 302. a localized oxidation structure (LOCOS) or a shallow trench isolation structure (STI). In an embodiment of the invention, the stepped gate dielectric structure is an oxide-nitride-oxide (ONO) composite structure, wherein the underlying oxide (the first dielectric material first layer) and the intermediate layer of nitrogen The material (the second dielectric material layer) is a hard mask layer that forms an isolation structure (eg, STI), and the nitride of the intermediate layer can serve as an etch stop layer for the etching process used to form the step-lag gate dielectric structure. Therefore, the gate structure 230 of the semiconductor device 500 can extend over the stepped gate dielectric structure 224 on the substrate 100 to reduce the reduced surface field (RESURF) of the device, thereby enabling the semiconductor device 500 to maintain a high bungee - Drain-Source breakdown voltage (BVdss). In the present embodiment, the thickness T2 of the step-lag gate dielectric structure 224 can be designed (which can be achieved by the process) not equal to the thickness T1 of the isolation structure 210. In this embodiment, the width W2 of the stepped gate dielectric structure 224 can be designed (which can be achieved by the process) to be less than or equal to the width W1 of the isolation structure 210. Moreover, the stepped gate dielectric structure 224 is formed over the substrate 200 without extending into the substrate 200. Therefore, the drain-source breakdown voltage of the semiconductor device 500 can be maintained compared to the conventional high voltage device (Drain- Source breakdown voltage, BVdss), can be entered into one Step shortening the current path from the drain to the source to further reduce the on resistance (Ron) and maintain the high drain-source breakdown voltage, thereby reducing the power loss of the lateral metal oxide semiconductor field effect transistor device . Moreover, the reduction of the on-resistance and the maintenance of the high drain-source breakdown voltage can effectively reduce the ratio of the on-resistance to the drain-source breakdown voltage of the semiconductor device 500 (Ron/BVdss ratio), and can cause the semiconductor device 500 It can withstand higher operation voltages and can reduce the pitch size and cell size of the semiconductor device 500.

While the present invention has been described by way of example only, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

200‧‧‧Substrate

201‧‧‧ surface

202‧‧‧First layer of first dielectric material

204‧‧‧Second dielectric material layer

210‧‧‧Isolated structure

212, 214, 216‧‧‧ doped areas

218‧‧‧First wiring doping area

220‧‧‧Second wiring doping area

222‧‧‧Second layer pattern of first dielectric material

224‧‧ ‧ differential gate dielectric structure

226‧‧‧ gate dielectric layer

228‧‧ ‧ gate layer

230‧‧‧ gate structure

232‧‧‧ lining

300‧‧‧active area

302‧‧‧Field area

500‧‧‧Semiconductor device

T1, T2‧‧‧ height

W1, W2‧‧‧ width

Claims (20)

A semiconductor device comprising: a substrate; an isolation structure located in the substrate to define an active region of the substrate, wherein the active region has a field region; and a differential gate dielectric structure is located in the field On the substrate in the board region, wherein the stepped gate dielectric structure comprises: a first layer of a first dielectric material and a second layer of a first dielectric material stacked vertically with each other; and a second layer of dielectric material The first layer of the first dielectric material and the second layer of the first dielectric material are separated from each other by the second layer of dielectric material, and the etching rate of the second dielectric material layer to an etchant is different An etch rate of the etchant in the second layer of the first dielectric material. The semiconductor device of claim 1, further comprising: a first doped region located in the active region between the field plate region and the isolation structure, wherein a conductivity type of the first doped region Resisting the conductivity type of the substrate in the active region; and a gate structure on the substrate in the active region and extending from the first doped region to the differential gate dielectric structure. The semiconductor device of claim 1, wherein the stepped gate dielectric structure is an oxide-nitride-oxide composite structure. The semiconductor device of claim 3, wherein the first layer of the first dielectric material is a pad oxide layer, the second layer of the first dielectric material is a high temperature oxide layer, and the second dielectric layer The material layer is a tantalum nitride layer. The semiconductor device of claim 1, wherein the thickness of the differential gate dielectric structure is not equal to the thickness of the isolation structure. The semiconductor device of claim 1, wherein the width of the differential gate dielectric structure is less than or equal to the width of the isolation structure. The semiconductor device of claim 1, wherein the first layer of the first dielectric material has a thickness less than a thickness of the second layer of the first dielectric material. The semiconductor device of claim 1, wherein a top surface of the isolation structure is aligned with a top surface of the second dielectric material layer. The semiconductor device of claim 2, wherein the gate structure comprises a gate dielectric layer and a gate layer on the gate dielectric layer, wherein the gate dielectric layer and the gate A doped region is in contact with the differential gate dielectric structure. The semiconductor device of claim 1, further comprising: a second doped region located in the substrate in the active region, wherein the second doped region surrounds the first doped region, and wherein The first doped region and the second doped region have opposite conductivity types; and a third doped region located in the substrate outside the active region and surrounding the isolation structure, wherein the first doped region It has the same conductivity type as the third doped region. A method of fabricating a semiconductor device, comprising the steps of: providing a substrate; sequentially forming a first dielectric material layer and a second dielectric material layer on a surface of the substrate; patterning the first dielectric material a first layer and the second layer of dielectric material; The first layer of the first dielectric material and the second layer of dielectric material are patterned as a hard mask layer, and a portion of the substrate is removed to form an isolation trench in the substrate; Forming an isolation structure in the trench to define an active region of the substrate; forming a second layer of the first dielectric material in a comprehensive manner; forming a mask on the second layer of the first dielectric material in the active region a pattern to define a plate region in the active region; performing an etching process to remove the second layer of the first dielectric material not covered by the mask pattern to form a second layer pattern of the first dielectric material Wherein the second layer of dielectric material acts as an etch stop layer of the etch process; and removing the patterned first layer of the first dielectric material that is not covered by the second layer of the first dielectric material and The second layer of dielectric material forms a differential gate dielectric structure on the substrate in the field plate region. The method of manufacturing the semiconductor device of claim 11, further comprising: forming a first region in the active region between the field plate region and the isolation structure before forming the second layer of the first dielectric material a doped region, wherein a conductivity type of the first doped region is opposite to a conductivity type of the substrate in the active region. The manufacturing method of the semiconductor device of claim 11, after forming the stepped gate dielectric structure, further comprising: forming a gate structure on the substrate in the active region, wherein the gate structure is from the gate structure The first doped region extends to cover the segmented gate dielectric structure. A method of manufacturing a semiconductor device according to claim 11, wherein Forming the insulating structure includes: forming a liner on a sidewall of the insulating trench; performing a high-density plasma chemical vapor deposition process, forming a dielectric material on the hard mask layer, and filling the insulating trench And performing a chemical mechanical polishing process to remove excess dielectric material on the second dielectric material layer of the hard mask layer to form the isolation structure in the isolation trench, wherein the isolation structure is The top surface is aligned with a top surface of the second layer of dielectric material. The method of fabricating a semiconductor device according to claim 11, wherein the stepped gate dielectric structure is an oxide-nitride-oxide composite structure. The method of manufacturing the semiconductor device of claim 15, wherein the first layer of the first dielectric material is a pad oxide layer, the second layer of the first dielectric material is a high temperature oxide layer, and the The second dielectric material layer is a tantalum nitride layer. The method of fabricating a semiconductor device according to claim 11, wherein the thickness of the stepped gate dielectric structure is not equal to the thickness of the insulating structure. The method of fabricating a semiconductor device according to claim 11, wherein a width of the stepped gate dielectric structure is less than or equal to a width of the insulating structure. The method of fabricating a semiconductor device according to claim 11, wherein a thickness of the first layer of the first dielectric material is less than a thickness of the second layer of the first dielectric material. A method of manufacturing a semiconductor device according to claim 12, wherein Before forming the second layer of the first dielectric material, further comprising: forming a second doping region in the substrate in the active region, wherein the second doping region surrounds the first doping region, and wherein the a doped region and the second doped region have opposite conductivity types; and a third doped region is formed in the substrate outside the active region, wherein the third doped region surrounds the isolation structure, and wherein the doped region The first doped region and the third doped region have the same conductivity type.