CN118076095A

CN118076095A - Semiconductor structure and preparation method thereof

Info

Publication number: CN118076095A
Application number: CN202211426000.9A
Authority: CN
Inventors: 唐怡
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-11-14
Filing date: 2022-11-14
Publication date: 2024-05-24
Also published as: WO2024103655A1

Abstract

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and is used for solving the problem of low integration level of semiconductor devices, and the semiconductor structure comprises: a plurality of semiconductor units arrayed in a horizontal direction and a vertical direction; the semiconductor unit comprises a first transistor structure and a second transistor structure, wherein the first transistor structure comprises a first semiconductor layer, and the second transistor structure comprises a gate structure and a second semiconductor layer; wherein the gate structure is located between the first semiconductor layer and the second semiconductor layer, the gate structure being in contact with sidewalls of the first semiconductor layer and the second semiconductor layer. Thus, the memory element is thinned, so that more transistor units are accommodated in a unit volume, and the integration density of the semiconductor structure is improved.

Description

Semiconductor structure and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

A dynamic random access memory (dynamic random access memory, abbreviated as DRAM) is a semiconductor memory that randomly writes and reads data at high speed, and is widely used in data storage devices or apparatuses. DRAM is composed of a plurality of repeated memory cells, each memory cell typically including 1 capacitor and 1 transistor. With the rapid development of semiconductor memory technology, higher demands are also being placed on DRAM cells, such as higher integration, faster read and write speeds, lower power consumption, and the like. Therefore, how to improve the storage performance and realize higher integration under the large premise of shrinking the device size is still a problem to be solved.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, comprising:

A plurality of semiconductor units arrayed in a horizontal direction and a vertical direction;

The semiconductor unit comprises a first transistor structure and a second transistor structure, wherein the first transistor structure comprises a first semiconductor layer, and the second transistor structure comprises a gate structure and a second semiconductor layer;

Wherein the gate structure is located between the first semiconductor layer and the second semiconductor layer, the gate structure being in contact with sidewalls of the first semiconductor layer and the second semiconductor layer.

In some embodiments, in the semiconductor units arranged in a horizontal direction, the gate structure is located at the same layer as the second semiconductor layer and the first semiconductor layer.

In some embodiments, the semiconductor structure further comprises:

and a write word line structure penetrating the first semiconductor layer among the plurality of semiconductor cells arranged in the vertical direction.

In some embodiments, the write word line structure includes one or more sub-write word line structures including a sub-write word line and a word line dielectric layer surrounding the sub-write word line, and the word line dielectric layer is located between the sub-write word line and the first semiconductor layer.

In some embodiments, further comprising:

isolation posts penetrating through the plurality of first semiconductor layers arranged in the vertical direction;

the isolation column is located between the write word line structure and the gate structure.

In some embodiments, the second semiconductor layer includes a first active portion and a second active portion, and the first active portion and the second active portion are arranged along the horizontal direction.

In some embodiments, the semiconductor structure further comprises:

and the plurality of leads are arranged in an array along the horizontal direction and the vertical direction, and the plurality of leads comprise a read word line electrically connected with the first active part and a read bit line electrically connected with the second active part.

In some embodiments, the plurality of leads are arranged in a plurality of rows and a plurality of columns, wherein a row includes the plurality of leads arranged in a horizontal direction and a column includes the plurality of leads arranged in a vertical direction, the semiconductor structure further comprising:

A connecting piece;

The connection piece is electrically connected with at least two read word lines.

In some embodiments, the first semiconductor layer includes a third active portion and a fourth active portion, the third active portion of the first semiconductor layer being in contact with the gate structure, the semiconductor structure further comprising:

a plurality of write bit lines stacked in a vertical direction, the write bit lines being electrically connected to fourth active portions in the semiconductor cells arranged in the horizontal direction;

and a plurality of conductive pillars arranged in the horizontal direction and extending in the vertical direction, the plurality of conductive pillars being electrically connected to different write bit lines, respectively.

In some embodiments, further comprising:

The first isolation structure is positioned between two adjacent columns of semiconductor units and is used for electrically isolating the two adjacent columns of semiconductor units, wherein one column of semiconductor units comprises a plurality of semiconductor units which are arranged along the vertical direction.

In some embodiments, further comprising:

And a second isolation structure between a read word line and a read bit line connected to the same second semiconductor layer.

The embodiment of the disclosure also provides a method for preparing the semiconductor structure, which comprises the following steps:

Providing a laminated structure, wherein the laminated structure comprises a plurality of dielectric layers and sacrificial layers which are alternately stacked along a vertical direction, the laminated structure comprises a first area, a first transistor area, a second transistor area and a second area which are sequentially divided along a first direction, and the second transistor area comprises a first subarea close to the first transistor area and a second subarea close to the second area;

Removing the sacrificial layer in the first region and the first transistor region to form a first void;

Filling a portion of the first void located in the first transistor region to form a first semiconductor layer;

Retaining the sacrificial layer within the first sub-region, removing the sacrificial layer within the second sub-region and the second region to form a second void;

Filling a gate dielectric layer and a second semiconductor layer in a portion of the second void located in the second sub-region;

The rest of the sacrificial layer and the gate dielectric layer form a gate structure.

In some embodiments, after forming the first semiconductor layer, the method further comprises:

Forming an initial via hole penetrating through the first semiconductor layer in the first transistor region;

Forming a sacrificial post within the initial via;

removing part of the sacrificial post to form a write word line through hole, and taking the reserved part of the sacrificial post as an isolation post;

And forming a writing line structure in the writing line through hole, wherein the isolation column is positioned between the writing line structure and the grid structure.

In some embodiments, forming a write word line structure within the write word line via includes:

forming a word line dielectric layer in the write word line through hole, wherein the word line dielectric layer covers the inner wall of the word line through hole;

And filling a writing line in the writing line through hole, wherein the word line medium layer is positioned between the writing line and the first semiconductor layer.

forming a plurality of first isolation structures arranged in a horizontal direction on the first transistor region, the second transistor region and the second region, the first isolation structures extending in the first direction and the vertical direction;

A plurality of second isolation structures are formed on the second region, and the second isolation structures extend along the first direction and the vertical direction and are positioned between two adjacent first isolation structures.

In some embodiments, the first isolation structure and the second isolation structure are formed in the same process.

In some embodiments, the second semiconductor layer includes a first active portion and a second active portion, and the first active portion and the second active portion are arranged along the horizontal direction;

the method further comprises the steps of:

filling a first conductive material in portions of the first voids within the first region to form a plurality of write bit lines;

filling a second conductive material in portions of the plurality of second voids in the second region; the second conductive material is separated by the second isolation structure to form a plurality of leads arranged in an array along a horizontal direction and a vertical direction, and the plurality of leads comprise a read word line electrically connected with the first active part and a read bit line electrically connected with the second active part.

In some embodiments, the filling of the first void with a first conductive material and the filling of the second void with a second conductive material are performed in a same step filling process.

In some embodiments, after forming the leads, the method further comprises:

etching part of the first isolation structure to form a first through hole, wherein the first through hole exposes a plurality of read word lines;

forming a connection member in the first via hole, the connection member electrically connecting a plurality of the read word lines exposed from the first via hole;

Etching the rest first isolation structure to form a second through hole, wherein the second through hole exposes a plurality of read word lines;

and forming a connecting piece in the second through hole, wherein the connecting piece is electrically connected with a plurality of read word lines exposed from the second through hole.

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: a plurality of semiconductor units arrayed in a horizontal direction and a vertical direction; the semiconductor unit comprises a first transistor structure and a second transistor structure, wherein the first transistor structure comprises a first semiconductor layer, and the second transistor structure comprises a gate structure and a second semiconductor layer; wherein the gate structure is located between the first semiconductor layer and the second semiconductor layer, the gate structure being in contact with sidewalls of the first semiconductor layer and the second semiconductor layer. In the embodiment of the disclosure, a transistor is used to replace a capacitor to form a 2T0C semiconductor unit structure, and the vertical height of the whole semiconductor unit is compressed by adopting a side wall connection mode, so that the thinning of the storage element is realized, more layers of semiconductor units can be integrated in a certain space, and the integration density of the semiconductor structure is improved.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

FIG. 1 is a three-dimensional schematic diagram of a semiconductor structure according to an embodiment of the disclosure;

FIG. 2 is a top view of a semiconductor structure according to one embodiment of the present disclosure;

FIG. 3 is a three-dimensional perspective and detailed schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

FIG. 4 is a three-dimensional schematic diagram of a conductive pillar connected to a write bit line according to an embodiment of the disclosure;

FIG. 5 is a three-dimensional perspective and detail view of a connector according to an embodiment of the present disclosure;

FIG. 6 is a detailed schematic view of a connector according to another embodiment of the present disclosure;

Fig. 7 is a flow chart of a semiconductor structure in a manufacturing process according to an embodiment of the present disclosure;

fig. 8 to 28 are schematic views of a semiconductor structure according to an embodiment of the present disclosure during a manufacturing process, wherein fig. 8, 13 to 16, 19 to 20 are schematic vertical cross-sectional views along a line a-a 'in fig. 2, fig. 9 to 12, 17 to 18, 21, 28 are schematic top views of the semiconductor structure during the manufacturing process, and fig. 22 to 27 are schematic vertical cross-sectional views along a line b-b' in fig. 21.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

A conventional Dynamic Random Access Memory (DRAM) is a 1T1C structure including a Transistor (Transistor) and a Capacitor (Capacitor), and the Capacitor is responsible for storing data information, but at the same time, the Capacitor also limits the development of the memory to the integration direction. It has been found that the gate in the transistor can accommodate a small amount of charge, so a 2T0C structure appears, which greatly alleviates the problem of space utilization. However, as the critical dimensions of DRAM continue to shrink, the problems of large memory cell size and low space utilization are also more pronounced.

Based on this, the embodiment of the disclosure provides a semiconductor structure, as shown in fig. 1 to 3, including:

a plurality of semiconductor units 13 arrayed in the horizontal direction and the vertical direction;

The semiconductor unit 13 comprises a first transistor structure 14 and a second transistor structure 15, the first transistor structure 14 comprising a first semiconductor layer 10, the second transistor structure 15 comprising a gate structure 11 and a second semiconductor layer 12;

Wherein the gate structure 11 is located between the first semiconductor layer 10 and the second semiconductor layer 12, the gate structure 11 is in contact with sidewalls of the first semiconductor layer 10 and the second semiconductor layer 12.

The semiconductor units 13 in the above semiconductor structure are horizontally arranged to form a typical 2T0C semiconductor unit structure, and the first semiconductor layer 10 and the second semiconductor layer 12 are respectively arranged at two sides of the gate structure 11 along the first direction in which the semiconductor units 13 extend in a manner of contacting with the side walls, so that the height of each row of semiconductor units 13 can be reduced, and thus more layers of semiconductor units 13 can be integrated in a certain space. Thus, the memory element can be thinned, so that more transistor structures can be accommodated in a unit volume, thereby improving the integration density of the semiconductor structure.

It will be appreciated that the gate structure 11 includes a gate layer 110 and a gate dielectric layer 111 (see fig. 1), one side of the gate layer 110 is connected to the first semiconductor layer 10, the other side is connected to the gate dielectric layer 111, and the connection between the second semiconductor layer 12 and the gate structure 11 is achieved through the gate dielectric layer 111. The material of the gate layer 110 includes a conductive material, such as one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, and in a specific embodiment, the material of the gate layer 110 is polysilicon or doped polysilicon. The material of the gate dielectric layer 111 may include silicon oxide, a high-K dielectric material, or a combination thereof, and in a specific embodiment, the material of the gate dielectric layer 111 is silicon oxide.

In practice, the gate layer 110 may include one or more layers of gate conductive material, which may be the same or different. It can be appreciated that the gate layer 110 serves as a memory element of the novel 2T0C structure, and the multi-layer conductive material can further enhance the performance of the memory.

In some embodiments, as shown in fig. 3, in the semiconductor units 13 arranged in the horizontal direction, the gate structure 11 is located at the same layer as the second semiconductor layer 12 and the first semiconductor layer 10.

The gate structure 11, the first semiconductor layer 10, and the second semiconductor layer 12 are positioned on the same layer, and the projections of the gate structure 11, the second semiconductor layer 12, and the first semiconductor layer 10 in the horizontal direction overlap, so that the height of the semiconductor unit 13 can be reduced to the maximum extent, and the space utilization rate can be improved.

Of course, in some other embodiments, the gate structure 11 is in contact with the sidewalls of the first semiconductor layer 10 and the second semiconductor layer 12, but there may be a certain height difference (not illustrated) in the vertical direction. In some embodiments, as shown in fig. 2, the first semiconductor layer 10 includes a third active portion 100 and a fourth active portion 101, where the third active portion 100 of the first semiconductor layer 10 is in contact with the gate structure 11, and the fourth active portion 101 is located at an end of the first semiconductor layer 10 away from the third active portion 100; the semiconductor structure further includes, referring to fig. 1: a plurality of write bit lines 32 stacked in the vertical direction, the write bit lines 32 being electrically connected to the fourth active portions 101 in the semiconductor cells 13 arranged in the horizontal direction;

a plurality of conductive pillars 33 (see fig. 4) arranged in the horizontal direction and extending in the vertical direction, the plurality of conductive pillars 33 being electrically connected to different write bit lines 32, respectively.

Here, a window 35 is reserved on the write bit line 32 located at the upper layer, and the window 35 can allow the conductive pillar 33 connected to the write bit line 32 at the lower layer to pass through. It should be understood that the plurality of write bit lines 32 may be arranged in a stepped structure (not shown) from bottom to top in the vertical direction, and a portion of each step protruding from the step of the upper layer is used to provide the conductive pillars 33. Compared with the embodiment provided as the step structure, the mode of reserving the window 35 can save the occupied area for providing the protruding step, thereby further improving the integration level of the semiconductor structure. Here, the position of the conductive pillar 33 on the write bit line 32 is not limited, and it is sufficient that one conductive pillar 33 is connected to one write bit line 32.

The material of the write bit line 32 may include a conductive material, such as a metal, a carbon-containing material, or a metal nitride, and the like, specifically, including, but not limited to, tungsten, copper, graphene, or titanium nitride, and the like, for example. The material of the conductive pillars 33 may comprise a conductive material, such as a metallic material, and the material of the conductive pillars 33 may be the same as or different from the material of the write bit lines 32. In some embodiments, the Young's modulus of the conductive pillars 33 is greater than the Young's modulus of the write bit lines 32, so that the problems of poor device stability caused by oblique deformation of the conductive pillars 33 can be alleviated.

In some embodiments, referring to fig. 1-2, the semiconductor structure further includes a write word line structure 31, the write word line structure 31 extending through the first semiconductor layer 10 of the plurality of semiconductor units 13 arranged in a vertical direction. Here, the number of the write word line structures 31 may be one or more. (in order to clearly embody the details of the semiconductor structures in this disclosure, only the complete structure of one write word line structure 31 is illustrated in fig. 1, with the portions of the other write word line structure 31 located between two first transistor structures 14 that are adjacent one above the other being omitted.)

The grid electrode of the writing transistor is formed in a vertical writing word line mode, compared with the traditional mode that the grid electrode of the writing transistor is independently formed above the semiconductor layer, the structure is simplified, and the integration level is improved.

In some embodiments, as shown in fig. 1-2, the semiconductor structure further includes isolation pillars 21, and the isolation pillars 21 penetrate the plurality of first semiconductor layers 10 arranged in the vertical direction; the isolation pillar 21 is located between the write word line structure 31 and the gate structure 11. The isolation column 21 can isolate the write word line structure 31 from the gate structure 11, preventing the write word line structure 31 from shorting with the gate structure 11, signal crosstalk, and the like. The material of the isolation column 21 may comprise an insulating material, such as one or more of an oxide, nitride, or oxynitride, including but not limited to silicon nitride in a particular embodiment.

In some embodiments, as shown in fig. 2, the write word line structure 31 includes one or more sub-write word line structures 20, the sub-write word line structures 20 include sub-write word lines 200 and word line dielectric layers 201 surrounding the sub-write word lines, and the word line dielectric layers 201 are located between the sub-write word lines 200 and the first semiconductor layer 10. The arrangement of the plurality of sub-write word line structures 20 can further increase the gate control capability and improve the electrical performance of the memory.

In the drawings of the present embodiment, only 2 sub-write word line structures 20 are schematically shown, but the actual number of sub-write word line structures 20 is not limited to 2, and specifically, the number of sub-write word line structures 20 may be 1,3, 4, 5, 6, or the like. It will be appreciated that the isolation pillars 21 are located between the write word line structure 31 and the gate structure 11 for isolating the write word line signal from the gate structure 11, and when the write word line structure 31 includes a plurality of sub-write word line structures 20, the isolation pillars 21 may be located between the sub-write word line structures 20 and the gate structure 11, and the number of the isolation pillars 21 should correspond to the number of the sub-write word line structures 20, as shown in fig. 2.

The material of the sub-write word line 200 may include one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. In the present embodiment, the material of the sub-write word line 200 is a metal material. The material of the word line dielectric layer 201 may include silicon oxide, a high-K dielectric material, or a combination thereof. In this embodiment, the word line dielectric material is a high-K dielectric material. In some embodiments, a barrier layer may be further formed between the word line dielectric layer 201 and the material layer of the sub-write word line 200 to prevent diffusion of the material of the sub-write word line 200, and the material of the barrier layer may be titanium nitride, for example.

In some embodiments, referring to fig. 3, the second semiconductor layer 12 includes a first active portion 121 and a second active portion 120, and the first active portion 121 and the second active portion 120 are arranged in a horizontal direction.

The first active portion 121 and the second active portion 120 of the second semiconductor layer 12 are connected to the gate dielectric layer 111 and are arranged in a horizontal direction. In actual operation, the distribution of the first active portions 121 and the second active portions 120 in the second semiconductor layer 12 is related to the connection of the subsequent wires 30, and is not uniformly distributed according to the positions shown in fig. 3, as shown in fig. 2 and 5, the wires 30 connected to the connection elements 34 are the read word lines 301, and the wires connected to the read word lines 301 are the first active portions 121.

In some embodiments, as shown in fig. 2 and fig. 5, the semiconductor structure further includes: the plurality of leads 30 are arranged in an array in the horizontal and vertical directions, and the plurality of leads 30 include a read word line 301 electrically connected to the first active portion 121 and a read bit line 300 electrically connected to the second active portion 120.

The material of the lead 30 may include a conductive material such as a metal, a carbonaceous material, or a metal nitride, etc., specifically including, but not limited to, tungsten, copper, graphene, or titanium nitride, etc.

In some embodiments, the leads 30 contact the sidewalls of the second semiconductor layer 12, which can further improve space utilization.

In order to clearly illustrate the detailed features of the semiconductor structure of the present disclosure, not all the components of the semiconductor structure are illustrated in fig. 1 to 5, but in fact, the semiconductor structure further includes some other components, as illustrated in fig. 21, the semiconductor structure further includes a second isolation structure 18, and the second isolation structure 18 is located between a read word line 301 and a read bit line 300 connected to the same second semiconductor layer 12. The second isolation structure 18 is provided to prevent the read word line 301 and the read bit line 300 from being shorted or signal crosstalk. The material of the second isolation structure 18 may include an insulating material, such as one or more of an oxide, nitride, or oxynitride.

In some embodiments, referring to fig. 5, the plurality of leads 30 are arranged in a plurality of rows and a plurality of columns, wherein a row includes the plurality of leads 30 arranged in a horizontal direction and a column includes the plurality of leads 30 arranged in a vertical direction, the semiconductor structure further includes:

A connector 34;

the connection 34 electrically connects at least two read word lines 301.

In the operation of the device, the read word lines need to be externally connected with a low level, for example, 0V, compared with the case that each read word line 301 is independently led out, at least two read word lines 301 are electrically connected and led out together through the connecting piece 34, so that the structure of the device can be simplified, and the reliability of the device can be improved.

Here, the specific position and connection manner of the connection member 34 are not particularly limited as long as it is possible to realize that at least two read word lines 301 can be electrically connected together and led out.

For example, in some embodiments, referring to fig. 6, a connector 34 may be located between two adjacent columns of leads 30, electrically connecting the read word lines 301 in two adjacent columns, and commonly leading the read word lines 301 in two adjacent columns of leads 30.

In some other embodiments, as shown in fig. 27, the read word lines 301 in four adjacent second transistor structures 15 are electrically connected together by the connection elements 34, and the connection elements 34 located at the upper layer are alternately arranged with the connection elements 34 located at the lower layer in front projection on the horizontal plane. The connection member 34 of fig. 27 does not need to connect the read word lines 301 of the entire column compared to the scheme as illustrated in fig. 6, and thus can shorten the line length, and compared to the scheme of fig. 6, the RC of the bottom read word line 301 can be reduced to thereby increase the data transmission speed.

It will be appreciated that the 4 row 8 column lead 30 array configuration illustrated in fig. 6 is merely illustrative of one possible embodiment, and that the number of rows and columns of the lead 30 array may be other numbers.

In some embodiments, referring to fig. 21, the semiconductor structure further includes a first isolation structure 17, where the first isolation structure 17 is located between two adjacent columns of semiconductor units 13 and is used to electrically isolate the two adjacent columns of semiconductor units 13, where one column of semiconductor units includes a plurality of semiconductor units 13 arranged along a vertical direction.

The material of the first isolation structure 17 may include an insulating material, such as one or more of oxide, nitride, or oxynitride.

Referring to fig. 7, a method for manufacturing a semiconductor structure provided in the present disclosure is described in further detail below with reference to specific embodiments.

First, step S101 is performed, referring to fig. 8, providing a stacked structure 36, the stacked structure 36 including a plurality of dielectric layers 42 and sacrificial layers 41 alternately stacked in a vertical direction, the stacked structure 36 including a first region A1, a first transistor region A2, a second transistor region A3, and a second region A4 sequentially divided in a first direction, the second transistor region A3 including a first sub-region P1 adjacent to the first transistor region A2 and a second sub-region P2 adjacent to the second region A4.

In practice, the stack structure 36 is formed on the substrate 40, and the stack structure 36 may be formed by an epitaxial growth process, wherein the material of the sacrificial layer 41 includes, but is not limited to, polysilicon, and the material of the dielectric layer 42 includes, but is not limited to, silicon oxide. Substrate 40 may be made of a semiconductor material, which may be one or more of silicon, germanium, silicon germanium compounds, and silicon carbon compounds.

Here, the first direction is a direction parallel to the plane in which the substrate 40 lies.

Note that in fig. 8 of the embodiment of the present disclosure, a stack of a certain number of dielectric layers 42 and sacrificial layers 41 is schematically shown to form the stacked structure 36. In practice, the actual number of layers of the laminated structure 36 is not limited to the number shown in the drawings in the embodiments of the present disclosure, and specifically, the number of layers of the laminated structure 36 may be 12, 24, 48, 64, 128, 256, or the like. However, the number of layers of the laminated structure 36 may be more or less, and is not particularly limited herein, and may be flexibly determined according to the requirements in actual operation.

In some embodiments, after forming the laminate structure 36, referring to fig. 9-10, further comprising: a plurality of first isolation structures 17 arranged in the horizontal direction are formed on the first transistor region A2, the second transistor region A3, and the second region A4, the first isolation structures 17 extending in the first direction and the vertical direction.

Specifically, the method of forming the first isolation structure 17 includes: first, referring to fig. 9, a first mask layer (not shown) is formed on the stacked structure 36, where the first mask layer has a plurality of first mask openings distributed in parallel; etching the laminated structure 36 along the first mask opening by taking the first mask layer as a mask, and etching the parts of the laminated structure 36 in the first transistor area A2, the second transistor area A3 and the second area A4 until the substrate 40 is exposed to form a first groove 170; then, referring to fig. 10, the first trench 170 is filled with an isolation material to form a first isolation structure 17, and the material of the first isolation structure 17 may be silicon oxide or other suitable isolation material. If necessary, a surface planarization process (CMP) may be further performed after filling the isolation material in the first trench 170 so that the upper surface of the first isolation structure 17 is flush with the upper surface of the stacked structure 36.

Here, the first trench 170 may be formed using an anisotropic etching process, for example, a plasma etching process; the filled isolation material may employ one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) processes.

Next, step S102 is performed, referring to fig. 13, removing the sacrificial layer 41 located in the first region A1 and the first transistor region A2 to form a first void 410.

The sacrificial layer 41 may be removed by a wet etching process or a dry etching process, for example, by etching in a lateral direction using an acidic solution.

Next, referring to fig. 14 to 15, step S103 is performed to fill the portion of the first void 410 located within the first transistor region A2 to form the first semiconductor layer 10.

In actual operation, referring to fig. 14, the first void 410 may be first filled to form the initial first semiconductor layer 105, and then, referring to fig. 15, the initial first semiconductor layer 105 is etched to remove a portion of the initial first semiconductor layer 105 located in the first region A1, and the remaining initial first semiconductor layer 105 is defined as the first semiconductor layer 10.

Here, filling the first voids 410 may employ one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) processes. The material forming the first semiconductor layer 10 may include a metal oxide semiconductor material, such as zinc tin oxide (ZnxSnyO, commonly referred to as "ZTO"), indium zinc oxide (InxZnyO, commonly referred to as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly referred to as "IGZO"), indium gallium silicon oxide (InxGaySizO, commonly referred to as "IGSO"), indium tungsten oxide (InxWyO, commonly referred to as "IWO"), and the like. Forming the first semiconductor layer 10 may further include a step of forming the third active portion 100 and the fourth active portion 101 (see fig. 3 for specific positions) in the first semiconductor layer 10 through a doping process.

Next, referring to fig. 16, the first conductive material is filled in portions of the plurality of first voids 410 located in the first region A1 to form the plurality of write bit lines 32.

It should be appreciated that filling the first conductive material may employ one or more of a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), or an Atomic Layer Deposition (ALD) process, and that the first conductive material may include a metal, a carbon-containing material, or a metal nitride, etc., specifically including, but not limited to, tungsten, copper, graphene, titanium nitride, etc., for example.

In some embodiments, the method of fabricating a semiconductor structure provided by the present disclosure further includes the step of forming the write word line structure 31.

Specifically, after the first isolation structure 17 is formed, an initial via 50 (see fig. 11) penetrating the first semiconductor layer 10 is formed in the first transistor region A2;

Then, a sacrificial post 51 is formed in the initial via 50 (see fig. 12);

After forming the write bit line 32, part of the sacrificial post 51 is removed, a write word line via 52 is formed, and a remaining part of the sacrificial post serves as the isolation post 21 (see fig. 17);

Next, the write word line structure 31 is formed within the write word line via 52, with the isolation pillar 21 located between the write word line structure 31 and the gate structure 11 (see fig. 18).

In practice, the method of forming the write word line structure 31 within the write word line via 52 includes:

Forming a word line dielectric layer 201 in the write word line via 52, the word line dielectric layer 201 covering the inner wall of the word line via 52; the write word line via 52 is filled with a write word line, and the word line dielectric layer 201 is located between the write word line and the first semiconductor layer 10.

The grid electrode of the writing transistor is formed in a vertical writing word line mode, compared with the traditional mode that the grid electrode of the writing transistor is independently formed above the semiconductor layer, the structure is simplified, and the integration level is improved. In addition, the isolation pillars 21 are provided to isolate the write word line structure 31 from the gate structure 11, preventing shorting or cross-talk.

Here, the process of forming the initial via 52 and removing a portion of the sacrificial post 51 may employ an anisotropic etching process, such as a plasma etching process. The process of forming the sacrificial post 51 may employ one or more of a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), or an Atomic Layer Deposition (ALD) process, wherein the material of the sacrificial post 51 may include one or more of an insulating material, such as an oxide, nitride, or oxynitride, etc. The material of the word line dielectric layer 201 is a high K dielectric material, and the process of forming the word line dielectric layer 201 may use an atomic layer deposition process. Filling the write word line can adopt an atomic layer deposition or a radio frequency sputtering physical vapor deposition method.

Next, step 104 is performed, referring to fig. 19, to remove the sacrificial layer 41 located in the second sub-region P2 and the second region A4 to form the second void 411 while leaving the sacrificial layer 41 located in the first sub-region P1.

Then, step 105 is performed, referring to fig. 20, to fill the gate dielectric layer 111 and the second semiconductor layer 12 in the portion of the second void 411 located in the second sub-region P2;

the remaining sacrificial layer 41 and the gate dielectric layer 111 form the gate structure 11.

In actual operation, after the gate electrode 110 is formed by the remaining sacrificial layer 41 located in the first sub-region P1 and the gate dielectric layer 111 is filled, there may be a case where the filled gate dielectric layer 111 exceeds the second sub-region P2, in which case, a portion of the gate dielectric layer 111 may be etched back first, a space is reserved for filling the second semiconductor layer 12 subsequently, and then the second semiconductor layer 12 is formed by refilling. The filling material of the second semiconductor layer 12 may include a metal oxide semiconductor material, such as Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), or the like.

The sacrificial layer 41 and the gate dielectric layer 111 may be removed by a wet etching process, for example, etching with an acidic solution. The filling gate dielectric layer 111 and the second semiconductor layer 12 may employ one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) processes.

With continued reference to fig. 20, the second conductive material 125 is filled in portions of the plurality of second voids 411 that are located in the second region A4. Etching the portion of the second semiconductor layer 12 beyond the second sub-region P2 is also included before filling the second conductive material, so that the second conductive material is filled. The filling of the second conductive material may employ one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) processes.

In some embodiments, after forming the first semiconductor layer 10, referring to fig. 21-22, the method further comprises:

a plurality of second isolation structures 18 are formed on the second region A4, the second isolation structures 18 extending in the first direction and the vertical direction and being located between two adjacent first isolation structures 17.

The second conductive material is separated by the second isolation structures 18 to form a plurality of leads 30 arranged in an array in the horizontal and vertical directions, the plurality of leads 30 including a read word line 301 electrically connected to the first active portion 121 and a read bit line 300 electrically connected to the second active portion 120.

In practice, the method of forming the second isolation structure 18 may include: first, a second mask layer (not shown) is formed on the laminated structure 36, and a plurality of second mask openings are formed in the second mask layer, wherein the second mask openings are distributed in parallel; etching the laminated structure 36 along the second mask opening by taking the second mask layer as a mask, and etching the part of the laminated structure 36 located in the second area A4 until the substrate 40 is exposed to form a second groove; the second trench is filled with an isolation material to form a second isolation structure 18, and the material of the second isolation structure 18 may be silicon oxide or other suitable isolation material.

The second trench may be formed using an anisotropic etching process, such as a plasma etching process; the filled isolation material may employ one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) processes.

Next, referring to fig. 23 to 27, further including:

etching part of the first isolation structure 17 to form a first through hole S1, wherein the first through hole S1 exposes the plurality of read word lines 301;

Forming a connection member 34 in the first via hole S1, the connection member 34 electrically connecting the plurality of read word lines 301 exposed from the first via hole S1;

Etching the remaining first isolation structures 17 to form second through holes S2, wherein the bottom surfaces of the second through holes S2 are higher than the upper surfaces of the connecting pieces 34 in the first through holes, and the second through holes S2 expose the plurality of read word lines 301;

A connection member 34 is formed in the second via hole S2, and the connection member 34 electrically connects the plurality of read word lines 301 exposed from the second via hole S2.

Specifically, taking an array of 4 rows and 8 columns of the leads 30 as an example, referring to fig. 23, first, a portion of the first isolation structures 17 is etched, for example, an odd number (1 st and 3 rd as illustrated in the figure) of the first isolation structures 17 is etched to form first through holes S1, and the first through holes S1 expose the substrate 40; then, referring to fig. 24, the first through hole S1 is filled with a conductive material, and the conductive material is etched back, so that a connection member 34 located at the lower layer is formed, and the connection member 34 electrically connects 4 read word lines 301 in the adjacent 4 second transistor structures 15; then, referring to fig. 25, the first through hole S1 is filled with a dielectric material; next, referring to fig. 26, the remaining first isolation structures 17, for example, the even number of first isolation structures 17 (as illustrated by the 2 nd) are etched, and the etching depth is controlled so that the bottom surface of the second through hole S2 is higher than the upper surface of the connection member 34 in the first through hole S1; next, referring to fig. 27, the second via S2 is filled with a conductive material, and a connection member 34 is formed at an upper layer to connect 4 read word lines 301 in adjacent 4 second transistor structures 15.

It should be noted that, referring to fig. 28 (the top views of the first through hole S1 and the second through hole S2 are shown in fig. 28), only the portion of the first isolation structure 17 located in the second region A4 is etched when the first through hole S1 and the second through hole S2 are formed, so that etching of the first isolation structure 17 located on the first transistor region A2 and the second transistor region A3 is avoided, and the connection member 34 is prevented from electrically connecting with the first transistor structure 14 and the second transistor structure 15 to cause a short circuit.

In actual operation, the first and second through holes S1 and S2 may be formed using an anisotropic etching process, such as a plasma etching process. Filling the first and second vias S1 and S2 to form the connection 34 may employ one or more of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD) processes. The upper portion of the first via S1 may be filled with Physical Vapor Deposition (PVD), and a dielectric material, such as oxide, nitride, or oxynitride, may be the same as or different from the material of the first isolation layer.

The first isolation structure 17 illustrated in fig. 9-10 is formed after the formation of the laminate structure 36 and prior to the formation of the first void 410, and the second isolation structure 18 illustrated in fig. 21 is formed after the formation of the second conductive material 125, it being understood that the sequence of steps described above is not the only limitation of the embodiments of the present disclosure, and in fact, the steps of preparing the first isolation structure 17 and the second isolation structure 18 may be completed after the formation of the laminate structure 36 and prior to the preparation of the connector 34. The first isolation structure 17 and the second isolation structure 18 may be formed in two process steps, and the sequence of preparation of the two may not be limited, and in some embodiments, the first isolation structure 17 and the second isolation structure 18 may be formed in the same process, so that the processes of mask, etching, filling, and the like may be saved, the process flow may be simplified, and the manufacturing cost may be reduced.

The steps illustrated in fig. 15-16 for filling the first conductive material to form the write bit line 32 are located before the steps illustrated in fig. 19-20 for filling the second conductive material 125, and the sequence of steps is not the only limitation of the embodiments of the present disclosure, and it should be understood that the first void 410 may be filled with the first conductive material and the second void 411 may be filled with the second conductive material in the same filling process, so as to reduce the one-time filling process, simplify the flow, and reduce the cost.

It should be noted that the method for manufacturing a semiconductor structure and the semiconductor structure provided in the embodiments of the present disclosure may be applied to any integrated circuit including the structure, such as a Dynamic Random Access Memory (DRAM). The features of the embodiments described in the present invention may be combined arbitrarily without any conflict.

The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the scope of the present disclosure, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the present disclosure.

Claims

1. A semiconductor structure, comprising:

2. The semiconductor structure of claim 1, wherein,

In the semiconductor units arranged in the horizontal direction, the gate structure is located at the same layer as the second semiconductor layer and the first semiconductor layer.

3. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:

4. The semiconductor structure of claim 3, wherein,

The word line structure comprises one or more sub-write word line structures, the sub-write word line structures comprise sub-write word lines and word line dielectric layers surrounding the sub-write word lines, and the word line dielectric layers are located between the sub-write word lines and the first semiconductor layers.

5. The semiconductor structure of claim 3, further comprising:

6. The semiconductor structure of claim 1, wherein the second semiconductor layer includes a first active portion and a second active portion, and wherein the first active portion and the second active portion are arranged along the horizontal direction.

7. The semiconductor structure of claim 6, wherein the semiconductor structure further comprises:

8. The semiconductor structure of claim 7, wherein a plurality of the leads are arranged in a plurality of rows and a plurality of columns, wherein a row includes a plurality of the leads arranged in a horizontal direction and a column includes a plurality of the leads arranged in a vertical direction, the semiconductor structure further comprising:

A connecting piece;

9. The semiconductor structure of claim 1, wherein the first semiconductor layer includes a third active portion and a fourth active portion, the third active portion of the first semiconductor layer being in contact with the gate structure, the semiconductor structure further comprising:

10. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:

11. The semiconductor structure of claim 7, wherein the semiconductor structure further comprises:

12. A method of fabricating a semiconductor structure, comprising:

13. The method of claim 12, wherein after forming the first semiconductor layer, the method further comprises:

Forming a sacrificial post within the initial via;

14. The method of claim 13, wherein forming a write word line structure within the write word line via comprises:

15. The method of claim 12, wherein after forming the first semiconductor layer, the method further comprises:

16. The method of claim 15, wherein the first isolation structure and the second isolation structure are formed in a same process.

17. The method according to claim 15, wherein the second semiconductor layer includes a first active portion and a second active portion, and wherein the first active portion and the second active portion are arranged in the horizontal direction;

the method further comprises the steps of:

18. The method of claim 17, wherein the filling of the first void with a first conductive material and the filling of the second void with a second conductive material are performed in a single fill process.

19. The method of claim 17, wherein after forming the leads, the method further comprises: