JP2013254860A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving excellent yield by preventing device characteristics of the semiconductor device from deteriorating due to occurrence of an eaves part on an element isolation region of a peripheral circuit region.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: forming a first high-dielectric constant insulating film on a peripheral circuit region including a memory cell region and an element isolation region of a semiconductor substrate; removing the first high-dielectric constant insulating film on the memory cell region by wet etching after performing damage etching treatment for at least a part of the first high-dielectric constant insulating film; and forming a first conductive film on the memory cell region and the peripheral circuit region.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

Conventionally, for the purpose of improving device characteristics, a MISFET (Metal Insulator Semiconductor Field) in which a gate insulating film of a high dielectric constant insulating film having a dielectric constant higher than that of SiO ₂ and a metal gate made of a metal material is combined. (Effect Transistor) has been proposed.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 2007-329237) discloses an n-channel type and a p-channel type each having a high dielectric constant insulating film containing at least hafnium, silicon, oxygen, and nitrogen and a gate electrode containing nickel silicide. MISFETs are disclosed.

  Patent Document 2 (Japanese Patent Laid-Open No. 2006-24594) discloses a high dielectric constant insulating film such as a gate insulating film containing zirconium oxide, hafnium oxide, zirconium silicate, hafnium silicate, and the like, and a gate electrode containing a group IV transition metal. Provided are n-channel and p-channel MISFETs.

JP 2007-329237 A JP 2006-24594 A

  1 to 3 are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device including a high dielectric constant insulating film and a metal gate. In the conventional manufacturing method, first, as shown in FIG. 1, after forming a transistor Tr including a buried word line 3 in the memory cell region M of the semiconductor substrate 1, the entire surface on the memory cell region M and the peripheral circuit region C is formed. Then, the first high dielectric constant insulating film 6a is formed. Next, a metal gate 6c and a conductive film 6d made of a metal film are formed on the P well 1e in the peripheral circuit region C, and a second high dielectric constant insulating film 6b, a metal gate 6c made of a metal film and a conductive film are formed on the N well 1d. 6d is formed. Thereafter, a damage / dry etching process is performed on the exposed first high dielectric constant insulating film 6a other than on the P well 1e and the N well 1d. As a result, the exposed first high dielectric constant insulating film 6a is converted into a damaged film 6a 'and is easily removed in a later wet etching process.

  As shown in FIG. 2, the first high dielectric constant insulating film 6a 'is removed by wet etching. At this time, the element isolation region 2 is also etched to form the eaves portion 15a.

  As shown in FIG. 3, conductive films 5b and 6f and a cap insulating film 6g are formed on the entire surface of the memory cell region M and the peripheral circuit region C, and then patterned. As a result, the bit line 20 is formed on the memory cell region M and the gate electrode 21 is formed on the peripheral circuit region C. At this time, the conductive film 5b or the like remains in the eaves portion 15a formed in the process of FIG. 2 to generate a remaining portion 15b such as a conductive film, and a short circuit of the gate electrode 21 occurs.

One embodiment is:
A first step of forming a first high dielectric constant insulating film on a peripheral circuit region having a memory cell region and an element isolation region of a semiconductor substrate;
A second step of removing the first high dielectric constant insulating film by wet etching after performing a damage etching process on at least a part of the first high dielectric constant insulating film on the memory cell region;
A third step of forming a first conductive film on the memory cell region and the peripheral circuit region;
The present invention relates to a method for manufacturing a semiconductor device.

  It is possible to prevent the device characteristics of the semiconductor device from deteriorating due to the occurrence of the eaves on the element isolation region in the peripheral circuit region. As a result, a semiconductor device with excellent yield can be provided.

It is sectional drawing explaining the problem of the conventional semiconductor device. It is sectional drawing explaining the problem of the conventional semiconductor device. It is sectional drawing explaining the problem of the conventional semiconductor device. It is a top view showing the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 1st Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 2nd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example. It is sectional drawing showing 1 process of the manufacturing method of the semiconductor device of 3rd Example.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, these Examples are specific examples shown for a deeper understanding of the present invention, and the present invention is not limited to these specific examples.

(First embodiment)
Hereinafter, a semiconductor device according to a first embodiment to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, a case where the present invention is applied to a DRAM (Dynamic Random Access Memory) as a semiconductor device will be described as an example. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for convenience, and the dimensional ratios of the respective components are the same as the actual ones. Not exclusively. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. . The same applies to the second and third embodiments.

First, the configuration of a DRAM (semiconductor device) as an embodiment to which the present invention is applied will be described. The DRAM of this embodiment is composed of a memory cell region M and a peripheral circuit region C shown in FIG. 4, and has a 6F2 cell arrangement (F is the minimum processing dimension). As shown in FIG. 4A, a plurality of element isolation regions 2 and active regions 1a are alternately formed at predetermined intervals in the Y direction in the memory cell region M of the DRAM (semiconductor device) of this embodiment. Further, a buried gate electrode 3 serving as a word line and a buried wiring 3 ′ for element isolation are buried in the semiconductor substrate at predetermined intervals in the Y direction shown in FIG. 4A so as to cut the active region 1a vertically. Has been. Further, the direction (X ₁ direction shown in FIG. 4A) perpendicular to the buried gate electrode 3 and the buried wire 3 ', a plurality of bit lines 20 are arranged at predetermined intervals. Memory cells are respectively formed in regions where the buried gate electrode 3 and the active region 1a intersect.

  The buried gate electrode (word line) 3 and the buried wiring 3 ′ have the same structure but have different functions. The buried gate electrode 3 is used as the gate electrode of the memory cell, whereas the buried wiring 3 'for element isolation is provided to isolate adjacent transistors by applying a predetermined potential. In other words, adjacent transistors on the same active region 1a are separated by maintaining the embedded wiring 3 'for element isolation at a predetermined potential so that the parasitic transistor is turned off. A plurality of memory cells are formed in the entire memory cell region M, and a capacitor 10 is provided for each memory cell. As shown in FIG. 4A, the capacitor contacts 8 connected to each capacitor 10 are arranged in the memory cell region M at a predetermined interval so as not to overlap each other. Each memory cell is connected to the bit line 20 via the bit contact 5.

  As shown in FIG. 4B, the peripheral circuit region C includes a region Cn where an N-channel MOS transistor (hereinafter may be referred to as NMOS) is formed, and a P-channel MOS transistor (hereinafter referred to as PMOS). A region Cp is formed in which a region may be formed. The regions Cn and Cp are arranged so as to sandwich the element isolation region (STI) 2 therebetween. In each of the regions Cn and Cp, an active region 1a where the surface of the semiconductor substrate is exposed is disposed, and a gate electrode 21 formed simultaneously with the bit line 20 of the memory cell region M is formed so as to divide the active area 1a into two. Has been. In each region Cn and Cp, the active region 1a on both sides of the gate electrode 21 becomes the source and drain 1c. The gate electrode 21, the source and drain 1c, and the gate insulating film (not shown) formed on the regions Cn and Cp respectively constitute a transistor Tr in the peripheral circuit region. The gate electrode 21 is connected in a region (not shown) on the right side of FIG. 4B. The source and drain 1c of the PMOS and NMOS are connected to the wiring 13 via the peripheral transistor contact 8 'and the wiring contact 12, respectively.

Subsequently, with reference to FIGS. 4 to 21, a method for manufacturing the semiconductor device of the first embodiment will be described. 5 to 21 illustrate a cross section corresponding to the cross section in the AA ′ direction in FIG. 4. The same applies to FIGS. 22 to 33 and 34A. 34B and 35 show cross sections corresponding to the cross section in the BB ′ direction of FIG. 4. The manufacturing method of the semiconductor device of the first embodiment is as follows:
(1) Step of forming the element isolation region 2,
(2) a step of forming the buried gate electrodes 3, 3 ′ in the memory cell region M;
(3) formation process of the bit line 20 and the gate electrode 21;
(4) a step of forming the capacitor contact plug 8 and the peripheral transistor contact 8 ′;
(5) Capacitor 10 formation process,
(6) wiring layer forming step,
It is roughly composed of Below, each said process is demonstrated in detail.

(1) Process of Forming Element Isolation Region 2 As shown in FIG. 5, for example, a silicon oxide film (SiO ₂ ) and a mask silicon nitride film (Si ₃ N ₄ ) (both on a P-type semiconductor substrate 1) (Not shown) are sequentially deposited. Next, a silicon nitride film, a silicon oxide film, and a silicon substrate 1 are sequentially patterned using photolithography and dry etching techniques, and an element isolation trench (trench) for partitioning the active region 1a on the silicon substrate 1 is formed. Form. At this time, the silicon surface to be the active region 1a of the silicon substrate 1 is covered with the mask silicon nitride film. Next, a silicon oxide film is formed on the surface of the silicon substrate 1 exposed in the element isolation trench. Specifically, a silicon oxide film is formed by thermal oxidation on the surface of the silicon oxide film and the silicon nitride film covering the active region 1a of the silicon substrate 1 together with the surface of the silicon substrate 1 in the element isolation trench. Next, after depositing a silicon nitride film so as to fill the inside of the element isolation trench, etch back is performed to leave the silicon nitride film at the bottom inside the element isolation trench.

  Next, a silicon oxide film is deposited so as to fill the inside of the element isolation trench by, eg, CVD. Thereafter, the surface of the substrate is flattened by CMP until the silicon nitride film for mask is exposed. Thus, even if the width of the element isolation groove is very narrow by embedding the inside of the element isolation groove mainly with a layer structure of a lower silicon nitride film and an upper silicon oxide film, The insulating film can be reliably filled in the separation groove. Next, the silicon nitride film and the silicon oxide film for the mask are removed by wet etching, for example. As a result, the surface of the element isolation trench (that is, the surface of the silicon oxide film) and the surface of the silicon substrate 1 have substantially the same height. In this manner, an element isolation region (STI (Shallow Trench Isolation)) 2 is formed. 5 and the subsequent drawings do not show the detailed structure of the element isolation region 2. In addition, the active region 1 a is partitioned and formed on the silicon substrate 1 by the element isolation region 2.

  Next, a silicon oxide film 3a is formed on the exposed surface of the silicon substrate 1 by thermal oxidation. Using a photolithography technique, a resist mask R is formed so as to cover the peripheral circuit region. Using this resist mask R as a mask, low concentration N-type impurities (phosphorus or the like) are ion-implanted into the active region 1a of the silicon substrate 1. Thereby, the diffusion layer 1b is formed in the vicinity of the surface of the silicon substrate 1 in the memory cell region M. This diffusion layer 1b functions as part of the source and drain of a transistor to be formed later.

(2) Step of Forming Embedded Gate Electrodes 3 and 3 ′ in Memory Cell Region M As shown in FIG. 6, a mask silicon nitride film 3b and a carbon film (amorphous carbon film) 3c are formed on the silicon oxide film 3a. Sequentially deposited. Thereafter, the carbon film 3c, the silicon nitride film 3b, and the silicon oxide film 3a are sequentially patterned using a resist mask R formed by a photolithography technique to form a hard mask. Next, the gate electrode groove (trench) 3d is formed by etching the semiconductor substrate 1 exposed at the bottom of the opening of the hard mask by dry etching using a hard mask. The gate electrode trench 3d is formed as a line pattern extending in a predetermined direction (Y direction in FIG. 4A) intersecting the active region 1a. When forming the gate electrode groove 3d, the semiconductor substrate 1 is etched so that the gate electrode groove 3d is shallower than the element isolation region 2.

  As shown in FIG. 7, a gate insulating film 3e is formed so as to cover the inner wall surface of the gate electrode trench 3d. As the gate insulating film 3e, for example, a silicon oxide film formed by thermally oxidizing the surface of the semiconductor substrate 1 can be used. Next, gate electrode materials are sequentially deposited on the gate insulating film 3e to fill the gate electrode trench 3d. Specifically, for example, titanium nitride (TiN) and tungsten (W) are used as the gate electrode material, and the laminated film 3g of the titanium nitride film and the tungsten film is embedded in the gate electrode groove 3d. Next, the laminated film 3g of the titanium nitride film and the tungsten film embedded in the gate electrode groove 3d is etched back to leave the titanium nitride film and the tungsten film 3g only at the bottom of the gate electrode groove 3d. In this manner, the buried gate electrode (word line) 3 and the buried wiring 3 ′ are formed in the gate electrode groove 3 d provided in the semiconductor substrate 1. The etch back amount during the etch back is such that the upper surface of the tungsten film 3g constituting the buried gate electrode 3 and the buried wiring 3 ′ in the gate electrode trench 3d is lower (deeper) than the silicon layer of the semiconductor substrate 1. Adjust so that Next, in order to fill the inside of the gate electrode trench 3d, the cap insulating film 3i is formed of, for example, a silicon nitride film or the like. Next, after performing a CMP process and planarizing until the mask silicon nitride film 3b is exposed, the mask for the peripheral circuit region C is exposed so that the silicon surface of the semiconductor substrate 1 in the peripheral circuit region C is exposed. The silicon nitride film 3b and the silicon oxide film 3a are removed by etching.

(3) Step of Forming Bit Line 20 and Gate Electrode 21 As shown in FIG. 8, a first high dielectric constant insulating film (High-K film) 6a is formed on the entire surface of the semiconductor substrate 1 (first Process).

  As shown in FIG. 9, a metal gate 6c made of a metal film, a conductive film 6d, and a mask oxide film 6e are stacked in this order on the first high dielectric constant insulating film 6a. Next, after applying a resist mask R to the entire surface, only the resist mask R on the P well 1e is left by photolithography.

  As shown in FIG. 10, only the metal gate 6c, the conductive film 6d, and the mask oxide film 6e on the P well 1e are left by etching using the resist mask R (not shown), and the other part of the film 6c. , 6d, 6e are removed. In this etching, the first high dielectric constant insulating film 6a is not etched but left on the entire surface of the semiconductor substrate 1. Thereafter, the resist mask R is removed. A second high dielectric constant insulating film (High-K film) 6 b is formed on the entire surface of the semiconductor substrate 1. Next, a metal gate 6c made of a metal film and a conductive film 6d are sequentially laminated on the entire surface of the semiconductor substrate 1. Thereafter, after a resist mask R is applied to the entire surface, only the resist mask R on the N well 1d is left by photolithography.

  As shown in FIG. 11, only the second high dielectric constant insulating film 6b, the metal gate 6c, and the conductive film 6d on the N well 1d are left by etching using a resist mask R (not shown). The other portions of the films 6b, 6c and 6d are removed. Also in this etching, the first high dielectric constant insulating film 6a is not etched but left on the entire surface of the semiconductor substrate 1. At this time, the conductive film 6d and the metal gate 6c located under the mask oxide film 6e on the P well 1e remain without being removed. Thereafter, the resist mask R is removed. A laminated film of the metal gate 6c and the conductive film 6d provided independently on the P well 1e and the N well 1d is an element isolation region 2 located between the P well 1e and the N well 1d in the X direction of FIG. It extends to the top.

  As shown in FIG. 12, after applying a resist on the entire surface of the semiconductor substrate 1, a resist mask R is formed so that the bit contact portion is opened by a photolithography technique. Next, damage / etching is performed on the portion of the first high dielectric constant insulating film 6a exposed at the bottom of the opening of the resist mask R to convert it into a damaged layer 6a '(second step). The damaged layer 6a 'is damaged by this damage and etching, and is removed by wet etching shown in FIG. At the time of this damage / etching, in this embodiment, since the first high dielectric constant insulating film 6a on the peripheral circuit region C is all protected by the resist mask R, it is not converted into the damaged layer 6a '.

  As shown in FIG. 13, after removing the resist mask R, the damaged layer 6a 'and the mask oxide film 6e are removed by wet etching. Thereby, in the memory cell region M, the surface of the silicon nitride film 3b appears in the bit contact portion. At this time, the first high dielectric constant insulating film 6a other than the bit contact portion that has not been damaged / etched is not damaged and remains without being removed by wet etching.

  As shown in FIG. 14, the silicon nitride film 3b and silicon oxide film 3a in the bit contact portion and the surface of the semiconductor substrate 1 are etched by dry etching using the first high dielectric constant insulating film 6a as a mask, and the bit contact is formed. Hole 5a is formed. As a result, the surface of the semiconductor substrate 1 is exposed at the bottom of the bit contact hole 5a.

  As shown in FIG. 15, a conductive film 5b (for example, a polysilicon film containing impurities) is formed on the entire surface of the semiconductor substrate 1 so as to fill the bit contact holes 5a, and a conductive film 6f ( For example, WN / W) from the substrate side, and a cap insulating film 6g (for example, a silicon nitride film) are sequentially formed (third step). At this time, as described above, according to the conventional manufacturing method, the first high dielectric constant insulating film 6a on the peripheral circuit region C is subjected to the damage etching process. Therefore, in the subsequent wet etching process, the first high dielectric constant insulating film 6a on the peripheral circuit region C is removed, and an eaves portion is generated in the element isolation region 2 located therebelow by wet etching. For this reason, after the film formation of the conductive film 5b, the material of the conductive film 5b remains under the eaves portion, causing a short circuit or the like, resulting in deterioration of device characteristics. On the other hand, in this embodiment, the first high dielectric constant insulating film 6a on the peripheral circuit region C is not damaged or etched, so that it remains on the element isolation region 2 even after wet etching in FIG. The element isolation region 2 is prevented from being exposed to wet etching. As a result, even when the conductive film 5b is formed, it is possible to prevent an eaves portion from occurring in the element isolation region 2 and deterioration of device characteristics such as a short circuit due to the conductive film 5b remaining under the eaves part.

  As shown in FIG. 16, a resist is applied to the entire surface of the semiconductor substrate 1. Thereafter, using a photolithography technique, a resist mask R that covers a region for forming the bit line in the memory cell region M and a region for forming the gate electrode in the peripheral circuit region C is formed.

As shown in FIG. 17, patterning is performed by etching using the resist mask R so that the stacked film remains on the bit contact portion in the memory cell region M and on the P well 1e and the N well 1d in the peripheral circuit region C. (4th process). Specifically, the conductive films 5b and 6f and the cap insulating film 6g are patterned on the bit contact portion. As a result, the bit contact 5 made of the conductive film 5b and the bit line 20 made of the conductive films 5b and 6f are formed. A cap insulating film 6g is formed on the bit line 20. The bit line 20 is formed as a pattern extending in a direction (X ₁ direction shown in FIG. 4) intersecting the buried word line 3 and the buried wiring 3 '. In FIG. 4, as an example, the bit line 20 has a linear shape orthogonal to the embedded word line 3, but the shape of the bit line 20 is not limited to this. For example, the bit line 20 may be arranged in a partially curved shape.

  On the P well 1e in the peripheral circuit region C, the first high dielectric constant insulating film 6a, the metal gate 6c, the conductive films 6d, 5b, and 6f, and the cap insulating film 6g are patterned. As a result, the gate electrode 21 for the N-channel type MOS transistor, which includes the metal gate 6c and the conductive films 6d, 5b, and 6f, is formed. On the N well 1d in the peripheral circuit region C, the first high dielectric constant insulating film 6a, the second high dielectric constant insulating film 6b, the metal gate 6c, the conductive films 6d, 5b, 6f, and the cap insulating film 6g are patterned. To do. As a result, the gate electrode 21 for the P-channel type MOS transistor, which includes the metal gate 6c and the conductive films 6d, 5b, and 6f, is formed. A cap insulating film 6g is formed on each gate electrode 21. Next, N-type impurities are implanted into the P well 1e in the peripheral circuit region C to form the source and drain 1c. Thereafter, a P-type impurity is implanted into N well 1d to form source and drain 1c. Thereafter, the resist mask R is removed.

(4) Capacitor Contact Plug Formation Step As shown in FIG. 18, a sidewall insulating film 6 h is formed on the entire surface of the semiconductor substrate 1. As the sidewall insulating film 6h, a silicon nitride film (Si ₃ N ₄ ), a silicon oxynitride film (SiON), or the like can be used. Next, SOD (Spin On Dielectric) is applied to the entire surface of the semiconductor substrate 1 so as to cover the bit line 20 and the gate electrode 21. Thereafter, an SOD annealing process is performed in a water vapor (H ₂ O) atmosphere to modify the film into a solid film, thereby forming the SOD film 7a. Next, until the upper surface of the sidewall insulating film 6h is exposed, CMP processing is performed on the SOD film 7a to flatten the surface. Thereafter, a second interlayer insulating film 7b made of a silicon oxide film is formed so as to cover the upper surfaces of the SOD film 7a and the sidewall insulating film 6h. Next, a resist mask R is formed on the second interlayer insulating film 7b by using a photolithography technique. Next, contact holes 8a are formed by dry etching using the resist mask R so that one of the source and drain 1b of the memory cell region M and the source and drain 1c of the peripheral circuit region C are exposed. In the peripheral circuit region C, the contact hole 8a is formed by a SAC (Self Alignment Contact) method using a sidewall insulating film 6h formed so as to cover the gate electrode 21 as a sidewall. At this time, when the opening is formed in the second interlayer insulating film 7b and the SOD film 7a, the sidewall insulating film 6h exposed at the bottom is removed to form the contact hole 8a.

  As shown in FIG. 19, a sidewall 8b made of, for example, a silicon nitride film is formed on the inner wall of the contact hole 8a. Next, using the second interlayer insulating film 7 as a mask, the surface of the semiconductor substrate 1 exposed at the bottom of the contact hole 8a in the P well 1e in the memory cell region M and the peripheral circuit region C is formed on the surface of the semiconductor substrate 1 with N such as phosphorus. Ions of type impurities are implanted. Thereby, an N-type impurity diffusion layer 1 b ′ is formed in the vicinity of the silicon surface of the silicon substrate 1. Similarly, a P-type impurity diffusion layer 1b 'is formed by ion-implanting P-type impurities into the surface of the semiconductor substrate 1 in the N well 1d in the peripheral circuit region C. These impurity diffusion layers 1b 'constitute part of the source and drain.

  Next, a polysilicon film containing phosphorus is deposited on the second interlayer insulating film 7 so as to be embedded in the contact hole 8a. Thereafter, the polysilicon film is etched back to form a polysilicon film 8c at the bottom of the contact hole 8a. Next, after forming a cobalt silicide (CoSi) film 8d on the surface of the polysilicon film 8c, a tungsten film is formed so as to fill the inside of the contact hole 8a. Next, the tungsten film is planarized by CMP until the surface of the second interlayer insulating film 7 is exposed, and a tungsten plug 8f is formed. In this way, in the memory cell region M, the capacitor contact plug 8 including the polysilicon layer 8c, the cobalt silicide layer 8d, and the tungsten plug 8f is formed. In the peripheral circuit region C, a peripheral transistor contact 8 'including a polysilicon layer 8c, a cobalt silicide layer 8d, and a tungsten plug 8f is formed.

  Next, tungsten nitride (MN) and tungsten (W) are sequentially deposited on the second interlayer insulating film 7 after the formation of the capacitor contact plug 8 and the peripheral transistor contact 8 'to form a laminated film. Next, this laminated film is patterned by a photolithography technique and a dry etching technique. Thereby, the capacitor contact pad 10a is formed on the capacitor contact plug 8 in the memory cell region M, and the peripheral wiring 10a 'is formed on the peripheral transistor contact 8' in the peripheral circuit region C. Here, since it is necessary to form the capacitor contact pads 10a at equal intervals in the memory cell region M, the capacitor contact pads 10a are formed at positions shifted from the capacitor contact plug 8 in plan view. However, since at least a part of the capacitor contact pad 10 a is disposed so as to overlap the capacitor contact plug 8 in plan view, the capacitor contact pad 10 a is connected via a portion in contact with the capacitor contact plug 8.

  Next, a stopper film 10b is formed on the second interlayer insulating film 7 using, for example, a silicon nitride film so as to cover the capacitor contact pad 10a and the peripheral wiring 10a '. Next, a third interlayer insulating film 9 is formed on the stopper film 10b using, for example, a silicon oxide film. Next, a resist mask R having an opening at a position corresponding to the capacitor contact pad 10 a is formed on the third interlayer insulating film 9. By dry etching using the resist mask R as a mask, the capacitor cylinder opening 10c is formed so as to penetrate the third interlayer insulating film 9 and the stopper film 10b on the capacitor contact pad 8. Thereby, a part of the upper surface of the capacitor contact pad 10a is exposed.

(5) Step of Forming Capacitor 10 As shown in FIG. 20, the lower electrode 10d of the capacitor element is formed using, for example, titanium nitride so as to cover the inner wall surface of the capacitor cylinder opening 10c and the upper surface of the exposed capacitor contact pad 10a. Form. As a result, the bottom of the lower electrode 10d is connected to the upper surface of the capacitive contact pad 10a. Next, a capacitive insulating film 10e is formed on the third interlayer insulating film 9 so as to cover the surface of the lower electrode 10d. As the capacitive insulating film 10e, for example, zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), and a stacked film thereof can be used. Next, the upper electrode 10f of the capacitor is formed using, for example, titanium nitride so as to cover the surface of the capacitive insulating film 10e. In this manner, the capacitor 10 including the lower electrode 10d, the capacitive insulating film 10e, and the upper electrode 10f is formed. Next, a fourth interlayer insulating film 11 made of, for example, a silicon oxide film is formed so as to cover the upper electrode 10f.

(6) Wiring Layer Formation Step As shown in FIG. 21, using the photolithography technique and the etching technique, the memory cell region M passes through the fourth interlayer insulating film 11 and reaches the upper electrode 10f, and the peripheral circuit region C Then, a contact hole 12a that penetrates the fourth interlayer insulating film 11, the third interlayer insulating film 9, and the stopper film 10b and reaches the peripheral wiring 10a ′ is formed. Next, after forming a barrier film (not shown) on the inner wall of the contact hole 12a, a tungsten film is formed so as to fill the inside of the contact hole 12a. Next, the tungsten film is planarized by CMP until the surface of the fourth interlayer insulating film 11 is exposed, and the tungsten film is left inside the contact hole 12a to form the wiring contact 12. Next, a conductive film 13 a such as aluminum (Al) or copper (Cu) and a mask insulating film 13 b are stacked so as to cover the upper surface of the wiring contact 12 and the surface of the fourth interlayer insulating film 11. Thereafter, the wiring 13 is formed by patterning the conductive film 13a and the mask insulating film 13b using a photolithography technique and an etching technique. Thereafter, a protective insulating film 14 is formed so as to cover the wiring 13, thereby completing the memory cell of the DRAM of this embodiment.

  As described above, in this embodiment, the first high dielectric constant insulating film 6a on the peripheral circuit region C is not subjected to the damage / etching process of FIG. For this reason, the first high dielectric constant insulating film 6a on the peripheral circuit region C remains on the element isolation region 2 during the wet etching process of FIG. 13 and prevents the element isolation region 2 from being exposed to the wet etching. To do. As a result, it is possible to prevent an eaves portion from occurring in the element isolation region 2 and a deterioration in device characteristics such as a short circuit due to the conductive film 5b remaining under the eaves portion. As a result, a semiconductor device with excellent yield can be provided. In the step of FIG. 14, the bit contact hole 5a can be formed by etching using the first high dielectric constant insulating film 6a as a mask.

(Second embodiment)
22 to 27 are views showing a method of manufacturing the semiconductor device of this example. In the first embodiment, in the step shown in FIG. 12, only the first high dielectric constant insulating film 6a corresponding to the bit contact portion is damaged and etched, and in this step shown in FIG. Only the dielectric insulating film 6a was removed. In contrast, in this embodiment, the first high dielectric constant insulating film 6a in the entire memory cell region M is damaged and etched, and then the first high dielectric constant insulating film 6a in this portion is removed. The point of removal is different. Below, the manufacturing method of a present Example is demonstrated centering on a process different from 1st Example.

  First, the steps of FIGS. 5 to 11 of the first embodiment are performed. Next, as shown in FIG. 22, after a resist is applied to the entire surface of the semiconductor substrate 1, a resist mask R in which the resist remains only on the peripheral circuit region C is formed by a photolithography technique. Next, using the resist mask R as a mask, the first high dielectric constant insulating film 6a located on the entire surface of the memory cell region M is damaged / etched to be converted into a damaged layer 6a ′ (see FIG. Second step). The damaged layer 6a 'is damaged by damage / etching and is removed by wet etching in the step of FIG. Further, during this damage / etching, all of the first high dielectric constant insulating film 6a on the semiconductor substrate 1 in the peripheral circuit region C is protected by the resist mask R. For this reason, the first high dielectric constant insulating film 6a on the peripheral circuit region C is not converted into the damaged layer 6a '.

  As shown in FIG. 23, after removing the resist mask R, the damaged layer 6a 'and the mask oxide film 6e on the P well 1e are removed by wet etching. Thereby, in the memory cell region M, the surface of the silicon nitride film 3b appears in the bit contact portion. At this time, the first high-dielectric-constant insulating film 6a in the peripheral circuit region C that has not been damaged / etched is not damaged and remains without being removed by wet etching.

  As shown in FIG. 24, the bit contact hole 5a is removed by using the photolithography technique and the dry etching technique to remove the silicon nitride film 3b, the silicon oxide film 3a, and a part of the surface of the semiconductor substrate 1 in the bit contact portion. Form. As a result, the surface of the semiconductor substrate 1 appears at the bottom of the bit contact hole 5a.

  As shown in FIG. 25, a conductive film 5b (for example, a polysilicon film) is formed on the entire surface of the semiconductor substrate 1 so as to fill the bit contact hole 5a, and a conductive film 6f (for example, a polysilicon film) is formed thereon. , WN / W) and a cap insulating film 6g (for example, a silicon nitride film) are sequentially formed (third process). At this time, as described above, according to the conventional manufacturing method, the first high dielectric constant insulating film 6a on the peripheral circuit region C is subjected to the damage etching process. Therefore, in the subsequent wet etching process, the first high dielectric constant insulating film 6a on the peripheral circuit region C is removed, and an eaves portion is generated in the element isolation region 2 located therebelow by wet etching. For this reason, after the film formation of the conductive film 5b, the material of the conductive film 5b remains under the eaves portion, causing a short circuit or the like, resulting in deterioration of device characteristics. On the other hand, in this embodiment, the first high dielectric constant insulating film 6a on the peripheral circuit region C has not been damaged or etched, so that it remains on the element isolation region 2 even in the wet etching process of FIG. Thus, the element isolation region 2 is prevented from being exposed to wet etching. As a result, it is possible to prevent the eaves portion from occurring in the element isolation region 2 and the conductive film 5b remains below the eaves portion after the formation of the conductive film 5b and the like, thereby deteriorating device characteristics such as a short circuit.

  As shown in FIG. 26, a resist is applied to the entire surface of the semiconductor substrate 1. Thereafter, using a photolithography technique, a resist mask R is formed so that a resist in a region for forming a bit line in the memory cell region M and a region for forming a gate electrode in the peripheral circuit region C remains.

  Thereafter, the semiconductor device of this embodiment is completed by performing the steps of FIGS. 17 to 21 of the first embodiment.

  As described above, in the present embodiment, the first high dielectric constant insulating film 6a on the peripheral circuit region C is not damaged or etched in the process of FIG. For this reason, the first high dielectric constant insulating film 6a on the peripheral circuit region C remains on the element isolation region 2 even in the wet etching process of FIG. 23 and prevents the element isolation region 2 from being exposed to the wet etching. To do. As a result, it is possible to prevent an eaves portion from occurring in the element isolation region 2 and a deterioration in device characteristics such as a short circuit due to the conductive film 5b remaining under the eaves portion. As a result, a semiconductor device excellent in yield can be provided.

(Third embodiment)
27 to 35 are views showing a method for manufacturing the semiconductor device of this example. In the first embodiment, the resist mask R is formed so as to cover the entire surface on the P well 1e and the N well 1d in the X direction in the steps of FIGS. On the other hand, the present embodiment is different in that the resist mask R is formed so as to cover a part on the P well 1e and the N well 1d in the X direction. Below, the manufacturing method of a present Example is demonstrated centering on a process different from 1st Example.

  First, the process of FIGS. 5-8 of 1st Example is implemented. As shown in FIG. 27, a metal gate 6c made of a metal film, a conductive film 6d, and a mask oxide film 6e are stacked in this order on the first high dielectric constant insulating film 6a. Next, after applying a resist to the entire surface, a resist mask R is formed by leaving only the resist located on a part of the P well 1e by photolithography.

  As shown in FIG. 28, only the metal gate 6c, the conductive film 6d, and the mask oxide film 6e located under the resist mask R are left by etching using the resist mask R (not shown), and other portions. The films 6c, 6d, and 6e are removed. In this etching, the first high dielectric constant insulating film 6a is not etched but left on the entire surface of the semiconductor substrate 1. Thereafter, the resist mask R is removed. A second high dielectric constant insulating film (High-K film) 6 b is formed on the entire surface of the semiconductor substrate 1. Next, a metal gate 6c made of a metal film and a conductive film 6d are sequentially laminated on the entire surface of the semiconductor substrate 1. Thereafter, after a resist is applied to the entire surface, only a resist located on a part of the N well 1d is left by a photolithography technique to form a resist mask R.

  As shown in FIG. 29, only the second high dielectric constant insulating film 6b, the metal gate 6c, and the conductive film 6d on the N well 1d are left by etching using the resist mask R (not shown). The other portions of the films 6b, 6c and 6d are removed. Also in this etching, the first high dielectric constant insulating film 6a is not etched but left on the entire surface of the semiconductor substrate 1. At this time, the conductive film 6d and the metal gate 6c located under the mask oxide film 6e on the P well 1e remain without being removed. Thereafter, the resist mask R is removed. A laminated film of a metal gate 6c and a conductive film 6d is provided independently on the P well 1e and the N well 1d. In FIG. 29, these laminated films are provided only on the P well 1e and the N well 1d, respectively, and do not extend to the element isolation region 2 located between the P well 1e and the N well 1d.

  As shown in FIG. 30, after applying a resist on the entire surface of the semiconductor substrate 1, a resist mask R having an opening in the bit contact portion is formed by a photolithography technique. Next, using the resist mask R as a mask, the portion of the first high dielectric constant insulating film 6a exposed at the bottom of the opening is damaged and etched to be converted into a damaged layer 6a ′ (second step). . The damaged layer 6a 'is damaged by this damage and etching, and is removed by wet etching shown in FIG. At the time of this damage / etching, in this embodiment, since the first high dielectric constant insulating film 6a on the peripheral circuit region C is all protected by the resist mask R, it is not converted into the damaged layer 6a '.

  As shown in FIG. 31, after removing the resist mask R, the damaged layer 6a 'and the mask oxide film 6e are removed by wet etching. Thereby, in the memory cell region M, the surface of the silicon nitride film 3b appears in the bit contact portion. At this time, the first high dielectric constant insulating film 6a other than the bit contact portion that has not been damaged / etched is not damaged and remains without being removed by wet etching.

  As shown in FIG. 32, the silicon nitride film 3b, the silicon oxide film 3a in the bit contact portion, and part of the surface of the semiconductor substrate 1 are etched by dry etching using the first high dielectric constant insulating film 6a as a mask. Then, the bit contact hole 5a is formed. As a result, the surface of the semiconductor substrate 1 is exposed at the bottom of the bit contact hole 5a.

  As shown in FIG. 33, a conductive film 5b (for example, polysilicon film) is formed on the entire surface of the semiconductor substrate 1 so as to fill the bit contact hole 5a, and a conductive film 6f (for example, WN / W) is formed thereon. W), and a cap insulating film 6g (for example, a silicon nitride film) are sequentially formed (third step). At this time, as in the first and second embodiments, in this embodiment, the first high dielectric constant insulating film 6a on the peripheral circuit region C that has not been subjected to the damage etching process is formed in the wet etching process of FIG. However, it remains on the element isolation region 2 to prevent the element isolation region 2 from being exposed to wet etching. As a result, it is possible to prevent an eaves portion from occurring in the element isolation region 2 and deterioration of device characteristics such as a short circuit due to the conductive film 5b remaining under the eaves portion after the conductive film 5b is formed.

  As shown in FIG. 34, a resist is applied to the entire surface of the semiconductor substrate 1. Thereafter, patterning is performed using a photolithography technique so that a resist R is left in a region where the bit line of the memory cell region M is formed and a region where the gate electrode of the peripheral circuit region C is formed.

  As shown in FIG. 35, by etching using a resist mask R (not shown), the P-well 1e and N-well 1d (not shown) on the bit contact portion of the memory cell region M and the peripheral circuit region C are shown. Then, patterning is performed so that the laminated film remains (fourth step). At this time, in this embodiment, the width of the metal gate 6c formed in the steps of FIGS. 27 to 29 and the conductive film 6d in the BB ′ direction (see FIG. 4B) is compared with that of the first and second embodiments. It is narrow. For this reason, the distance L between the metal gates 6c and the conductive films 6d constituting the NMOS and PMOS gate electrodes 21 is widened, and the aspect of the hollow portion formed by these metal gates 6c and conductive films 6d and the semiconductor substrate 1 is increased. The ratio becomes smaller. Therefore, when the conductive films 5b and 6f are formed in the step of FIG. 33, these conductive films are formed in a region having a wide interval L and a small aspect ratio, and the conductive films 5b and 6f are disconnected or have high resistance. Can be prevented.

  Thereafter, the semiconductor device of this embodiment is completed by carrying out the steps of FIGS. 18 to 21 of the first embodiment.

  As described above, in this embodiment, the first high dielectric constant insulating film 6a on the peripheral circuit region C not subjected to the damage / etching process of FIG. 30 is formed in the element isolation region 2 during the wet etching process of FIG. This prevents the element isolation region 2 from being exposed to wet etching. As a result, it is possible to prevent an eaves portion from occurring in the element isolation region 2 and deterioration of device characteristics such as a short circuit due to the conductive film 5b remaining under the eaves portion after the conductive film 5b is formed. As a result, a semiconductor device excellent in yield can be provided. Further, since the peripheral circuit region C is entirely covered with the first high dielectric constant insulating film 6a, the boundary between the region Cn where the NMOS is formed and the region Cp where the PMOS is formed is disposed on the element isolation region 2. There is no need to do. As a result, the PN boundary margin is increased, alignment can be facilitated, and a semiconductor device capable of miniaturization can be obtained. In the step of FIG. 32, the bit contact hole 5a can be formed by etching using the first high dielectric constant insulating film 6a as a mask.

  In the first to third embodiments, the conductive films 5b and 6f correspond to the “first conductive film” recited in the claims. The metal gate 6c and the conductive film 6d correspond to the “second conductive film” recited in the claims.

In the first to third embodiments, the first and second high-k insulating film 6a, and 6b, the relative dielectric constant than SiO ₂ (in the case of SiO ₂ about 3.6) is greater insulating film Represents that. Typically, the dielectric constant of the high dielectric constant insulating film can be several tens to thousands. As the first and second high dielectric constant insulating films, for example, HfSiO, HfSiON, HfZrSiO, HfZrSiON, ZrSiO, ZrSiON, HfAlO, HfAlON, HfZrAlO, HfZrAlON, ZrAlO, or ZrAlON can be used.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Active region 1b, 1c Source and drain 1b 'Contact diffusion region 1d N well 1e P well 2 Element isolation region (STI: Shallow trench insulator)
3 buried word line 3 'buried wiring 3a silicon oxide film 3b silicon nitride film 3c amorphous carbon film 3d gate electrode trench (trench)
3e Gate oxide film 3g Laminated film 3i of titanium nitride film and tungsten film 3i Cap insulating film (silicon oxide film)
5 bit contact 5a bit contact hole 5b conductive film 6a first high dielectric constant insulating film 6a ′ damage film 6b second high dielectric constant insulating film 6c metal gate 6d conductive film 6e mask oxide film 6f conductive film (WN / W)
6g Cap insulating film 6h Side wall insulating film 7 Second interlayer insulating film 7a SOD film 7b Silicon oxide film 8 Capacitor contact plug 8 'Peripheral transistor contact 8a Contact hole 8b Side wall 8c Polysilicon layer 8d CoSi layer 8f Tungsten plug 9 Third Interlayer insulating film 10 Capacitor 10a Capacitance contact pad 10a 'Peripheral wiring 10b Stopper film 10c Capacitance cylinder opening 10d Lower electrode (TiN)
10e capacitive insulating film 10f upper electrode (TiN)
11 Fourth interlayer insulating film 12 Wiring contact 12a Contact hole 13 Wiring 13a Conductive film 13b Mask insulating film 14 Protective insulating film 15a Eaves portion 15b Remaining portion of polysilicon film 20 Bit line 21 Gate electrode R Resist mask M Memory cell region Tr Transistor C Peripheral circuit region Cn NMOS region Cp PMOS region

Claims (11)

A first step of forming a first high dielectric constant insulating film on a peripheral circuit region having a memory cell region and an element isolation region of a semiconductor substrate;
A second step of removing the first high dielectric constant insulating film by wet etching after performing a damage etching process on at least a part of the first high dielectric constant insulating film on the memory cell region;
A third step of forming a first conductive film on the memory cell region and the peripheral circuit region;
A method for manufacturing a semiconductor device, comprising: In the second step,
After the damage / etching process is performed on the first high dielectric constant insulating film at a position corresponding to the bit contact hole on the memory cell region, the first high dielectric constant insulating film is formed by the wet etching. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is removed. In the second step,
2. The first high dielectric constant insulating film is removed by the wet etching after the damage etching process is performed on the first high dielectric constant insulating film on the memory cell region. Semiconductor device manufacturing method. After the first step and before the second step,
4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an independent second conductive film on each of the P well and the N well on the peripheral circuit region. 5. The P well and the N well are positioned so as to sandwich the element isolation region between these wells,
In the step of forming the second conductive film,
5. The method of manufacturing a semiconductor device according to claim 4, wherein each of the second conductive films on the P well and the N well is formed to extend to the element isolation region. The P well and the N well are positioned so as to sandwich the element isolation region between these wells,
In the step of forming the second conductive film,
5. The method of manufacturing a semiconductor device according to claim 4, wherein each of the second conductive films on the P well and the N well is formed so as not to extend to the element isolation region.   7. The method further comprises forming a second high dielectric constant insulating film on the first high dielectric constant insulating film located on one of the P well and the N well. The method for manufacturing a semiconductor device according to any one of the above. Before the second step,
Forming a transistor having a source and drain and a buried gate electrode in the memory cell region;
In the second step,
Removing the first high dielectric constant insulating film located on one of the source and drain;
After the second step and before the third step,
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a bit contact hole so that one of the source and the drain is exposed. After the third step,
By patterning the first conductive film, a bit contact connected to one of the source and drain in the memory cell region and a bit line connected to the bit contact are formed, and a gate electrode is formed in the peripheral circuit region. The method for manufacturing a semiconductor device according to claim 8, further comprising a fourth step of forming the semiconductor device. After the fourth step,
The method for manufacturing a semiconductor device according to claim 9, further comprising forming a capacitor so as to be connected to the other of the source and the drain in the memory cell region.   11. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive film is a stacked film of a polysilicon film containing impurities, a tungsten nitride film, and a tungsten film.

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