JP2007324489A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can be manufactured by a simplified process and having an MISFET having a groove type gate electrode and a groove type capacitor, and provide its manufacturing method. <P>SOLUTION: There is provided a groove formation process of simultaneously forming a gate groove for embedding a gate electrode of an MISFET and a capacitor forming groove for forming a capacitor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a MISFET and a MIS capacitor and a manufacturing method thereof.

  In semiconductor devices, the demand for miniaturization has progressed, and there is a demand for reduction in area for MIS (Metal Insulator Semiconductor) capacitors used in booster circuits and the like. In response to such a requirement, it is known to improve the capacitance per unit area by forming an uneven groove in the capacitor formation region.

  In addition, with the miniaturization of semiconductor devices, countermeasures for lowering the threshold and lowering the punch-through breakdown voltage are required. As a countermeasure, a trench type MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a gate electrode is buried in a trench is known. As a trench-type MISFET, for example, in Patent Document 1, a channel is formed on the sidewall of a trench dug in a semiconductor substrate, and the distance from the bottom of the trench to the diffusion layer of the semiconductor device is greater than the planar dimension of the trench in the channel direction. A semiconductor device characterized by a long time is disclosed.

  By the way, with the miniaturization of semiconductor devices, the manufacturing process has become complicated. From the viewpoint of cost reduction and throughput improvement, it is desirable that the manufacturing process be simplified.

  In order to simplify the manufacturing process, Patent Document 2 is formed with a semiconductor element, an element isolation groove for separating the semiconductor elements, a capacitor formation groove, and a dielectric film in the capacitor formation groove. In a method for manufacturing a semiconductor device having a capacitor electrode, there is disclosed a method for manufacturing a semiconductor device, wherein the capacitor forming groove is formed in the step of forming the element isolation groove in the semiconductor substrate.

However, a technique that can simplify the manufacturing process in a semiconductor device having a MISFET having a trench gate electrode and a MIS capacitor has not been disclosed yet.
Japanese Patent Laid-Open No. 5-167033 JP 2003-309182 A

  An object of the present invention is to provide a semiconductor device having a MISFET having a groove-type gate electrode and a groove-type capacitor, and a method for manufacturing the same, which can be manufactured by a simplified process.

  In the following, means for solving the problem will be described using the numbers used in [Best Mode for Carrying Out the Invention] in parentheses. These numbers are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a MISFET (30A) having a groove type gate electrode (16a) and a groove type capacitor (30B). A groove forming step (step S80) for simultaneously forming a gate groove (7a) for embedding the gate electrode (16a) of the MISFET (30A) and a capacitor forming groove (7b) for forming the capacitor (30B); It comprises.
By forming the gate groove (7a) and the capacitor formation groove (7b) in the same process, the manufacturing process can be simplified.

In the semiconductor device manufacturing method, an insulating film forming step (step S110) for simultaneously forming a gate insulating film (10a) of the MISFET (30A) and a capacitor dielectric film (10b) of the capacitor (30B); It is preferable to comprise.
By simultaneously forming the gate insulating film (10a) and the capacitor dielectric film (10b), the manufacturing process can be further simplified.

In the method for manufacturing a semiconductor device, the gate insulating film (10a) and the capacitor dielectric film (10b) are preferably silicon oxide films.
The silicon oxide film can be used as both the gate insulating film (10a) and the capacitor dielectric film (10b). By using the silicon oxide film, the gate insulating film (10a) and the capacitor dielectric film (10b) can be formed simultaneously.

In the semiconductor device manufacturing method, an electrode forming step (steps S120 to S180) for simultaneously forming the gate electrode (16a) of the MISFET (30A) and the upper electrode (16b) of the capacitor (30B) is further performed. It is preferable to comprise.
By simultaneously forming the gate electrode (16a) and the upper electrode (16b) of the capacitor, the manufacturing process can be further simplified.

  In the semiconductor device manufacturing method, the electrode forming step (steps S120 to S180) includes a step of stacking polycrystalline silicon on the gate insulating film (10a) and the capacitor dielectric film (10b) (step S120), A step of stacking tungsten on the polycrystalline silicon (step S130).

The semiconductor device (100) according to the present invention includes a MISFET (30A) having a groove-type gate electrode (16a) and a groove-type capacitor (30B). The gate electrode (16a) and the upper electrode (16b) of the capacitor (30B) are formed of the same material.
By using the same material for the gate electrode (16a) and the upper electrode (16b) of the capacitor, the gate electrode (16a) and the upper electrode (16b) can be formed in the same process.

In the semiconductor device (100), the gate insulating film (10a) of the MISFET (30A) and the capacitor dielectric film (10b) of the capacitor (30B) are preferably formed of the same material.
Since the gate insulating film (10a) and the capacitor dielectric film (10b) are made of the same material, the gate insulating film 10a and the capacitor dielectric film (10b) can be formed in the same process.

  In the semiconductor device (100), the gate insulating film (10a) and the capacitor dielectric film (10b) are preferably silicon oxide films.

In the semiconductor device (100), the gate electrode (16a) of the MISFET (30A) and the upper electrode (16b) of the capacitor (30B) are preferably formed of the same material.
By using the same material for the gate electrode (16a) and the upper electrode (16b), the gate electrode (16a) and the upper electrode (16b) can be formed in the same process.

  In the semiconductor device (100), the gate electrode (16a) and the upper electrode (16b) of the capacitor are formed of polycrystalline silicon (11) provided on the gate insulating film (10a) and the capacitor dielectric film (10b), And tungsten (12) provided on the polycrystalline silicon (11).

  According to the present invention, there are provided a semiconductor device having a MISFET having a trench gate electrode and a capacitor, which can be manufactured by a simplified process, and a manufacturing method thereof.

  A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of the semiconductor device 100, and FIG. 2 is a view showing an AA 'section and a BB' section of FIG. An example of the semiconductor device 100 according to the present embodiment is a DRAM. The semiconductor device 100 has a MISFET and a capacitor. These are formed on a semiconductor substrate 1 of single crystal silicon. In FIG. 1, the left diagram shows a memory cell portion including MISFET (hereinafter, MISFET formation region), and the right diagram shows a capacitor formation region.

  As shown in FIG. 1, in the MISFET formation region, the word line (WL) and the bit line (BL) are arranged on the semiconductor substrate 1 so as to intersect each other. WL is connected to the gate electrode 16a of the MISFET 30A, and BL is connected to the source / drain region via plugs. In FIG. 1, the source / drain regions are not shown.

  On the other hand, at least one capacitor groove is formed in the capacitor formation region on the semiconductor substrate 1. In the present embodiment, the case where the plurality of capacitor grooves have a stripe shape extending in parallel on the substrate plane will be described. However, other shapes such as a hole shape and a lattice shape may be used. Is not limited.

  Please refer to FIG. In FIG. 2, the diagram on the left side is a diagram showing the AA ′ cross section of FIG. 1. That is, the cross-sectional structure of the MISFET 30A portion is shown. For convenience of explanation, only an N-channel type MISFET is shown, but a P-channel type MISFET is also formed in another region. The MISFET 30A includes a P-type impurity layer 8, source / drain regions 17, 19a, a gate insulating film 10a, and a gate electrode 16a.

  The upper surface portion of the semiconductor substrate 1 is a P-type impurity layer 8 doped with P-type impurities.

  The P-type impurity layer 8 is provided with source / drain regions 17 and 19a doped with N-type impurities. The source / drain regions 17 and 19 a are electrically connected to plugs 22 b and 22 a provided on the semiconductor substrate 1. Examples of the material of the plugs 22b and a include polycrystalline silicon doped with impurities.

  An element isolation groove is further formed on the semiconductor substrate 1. An element isolation oxide film 4 is embedded in the element isolation trench. The element isolation trench separates semiconductor elements such as a MISFET and a capacitor.

  A gate groove 7 a is formed on the semiconductor substrate 1. A gate electrode 16a is embedded in the gate trench 7a via a gate insulating film 10a. The gate insulating film 10a is a silicon oxide film. In this way, the groove-type gate electrode 16a is formed.

  The gate electrode 16 a includes polycrystalline silicon 11 and tungsten 12. The polycrystalline silicon 11 is embedded in the gate groove 7a and is also provided on the gate insulating film 10a around the gate groove 7a. Tungsten 12 is formed on polycrystalline silicon 11.

  A silicon nitride film 13 is formed on the tungsten 12 of the gate electrode 16a. The gate electrode 16a can be made of an alloy film such as a refractory metal or silicide in addition to polycrystalline silicon and tungsten. In this case, the capacitor dielectric described later needs to be made of the same material.

  A silicon nitride film 15 is provided on the sides of the tungsten 12 and the silicon nitride film 13. Further, a silicon nitride film 18 is formed on the side portion of the silicon nitride film 15 and the side portion of the polycrystalline silicon.

  An interlayer insulating film 20 is provided around the gate electrode 16a and the plugs 22a and 22b. That is, the gate electrode 16 a and the plugs 22 a and 22 b are arranged so as to be embedded in the interlayer insulating film 20. An interlayer insulating film 23 is provided on the interlayer insulating film 20. In the interlayer insulating film 23, a wiring lead plug 24a is buried at a position corresponding to the plug 22a.

  Since the MISFET 30A having the groove-type gate electrode configured as described above can use the side wall of the groove as a channel, the effective channel length is increased. It is possible to suppress the short channel effect, which becomes a problem with miniaturization of semiconductor devices.

  Next, the configuration of the capacitor 30B will be described with reference to the diagram on the right side of FIG. The capacitor 30B is provided on the same semiconductor substrate 1 on which the MISFET 30A is formed. The capacitor 30B includes a capacitor lower electrode 9, a capacitor upper electrode 16b, a capacitor dielectric film 10b, and a capacitor lower electrode pulling portion diffusion layer 19b. The capacitor 30b is electrically connected to surrounding semiconductor elements by two plugs 24c and 24b.

  The capacitor lower electrode 9 is formed on the surface side of the semiconductor substrate 1. The capacitor lower electrode 9 is a semiconductor layer doped with N-type impurities.

  A plurality (two in the figure) of capacitor grooves 7 b are dug in the capacitor formation region of the semiconductor substrate 1. The depth of the capacitor trench 7b is substantially the same as that of the gate trench 7a. Although details will be described later, the capacitor trench 7b is formed in the same process as the gate trench 7a.

  A capacitor dielectric film 10b is provided on the semiconductor substrate 1 (on the capacitor lower electrode 9) so as to follow the capacitor groove 17b. The capacitor dielectric film 10b is the same silicon oxide film as the gate insulating film 10a. Although details will be described later, the capacitor dielectric film 10b is formed in the same process as the gate insulating film 10a.

  A capacitor upper electrode 16b is provided on the semiconductor substrate 1 (on the capacitor lower electrode 9) via the capacitor dielectric film 10b. The capacitor upper electrode 16b is disposed corresponding to the capacitor formation region. Here, the capacitor upper electrode 16b is formed so as to fill the capacitor groove 7b.

  A silicon nitride film 13 is formed on the capacitor upper electrode 16b. Further, a silicon nitride film 15 is provided at the end of the capacitor formation region so as to cover the side portions of the silicon nitride film 13 and the tungsten 12. Further, a silicon nitride film 18 is provided on the sides of the silicon nitride film 15 and the polycrystalline silicon 11.

  The capacitor lower electrode pulling portion diffusion layer 19b is provided outside the region (capacitor forming region) where the capacitor upper electrode 16b is formed on the semiconductor substrate 1. The capacitor lower electrode pulling portion diffusion layer 19b is an N-type impurity region doped with an N-type impurity (such as phosphorus). The capacitor lower electrode pulling portion diffusion layer 19b is connected to the plug 24b.

  Two layers of interlayer insulating films 20 and 23 are formed on the semiconductor substrate 1 on which the capacitor 30B is formed. That is, the space above the silicon nitride 13 is filled with the interlayer insulating film 20. An interlayer insulating film 23 is formed on the interlayer insulating film 20.

  The two plugs 24b and 24c are arranged so as to be embedded in the interlayer insulating films 20 and 23. The plug 24b is connected to the capacitor dielectric film 10b formed on the capacitor lower electrode pulling portion diffusion layer 19b. The plug 24c penetrates the silicon nitride film 13 and is connected to the capacitor upper electrode 16b (tungsten 12). The plugs 24b and c include tungsten, Ti, and TiN.

  In the capacitor 30B having the above-described configuration, the capacitor surface area is increased by providing the capacitor groove 7b, and the capacitance per unit area can be improved.

  Next, a method for manufacturing a semiconductor device having the MISFET 30A and the capacitor 30B will be described. FIG. 10 is a flowchart of the semiconductor device manufacturing method. The manufacturing method of the semiconductor device has steps S10 to 230 shown in FIG. Details of each step will be described below with reference to FIGS. 3 to 9, the left diagram is a configuration including a MISFET, and the right diagram is a cross-sectional view illustrating a configuration including a capacitor.

  Steps from S10 to S40 will be described.

Step S10: Formation of Silicon Oxide Film First, a P-type single crystal silicon semiconductor substrate 1 is prepared. The semiconductor substrate 1 is thermally oxidized to form a silicon oxide film 2 on the surface. The film thickness of the silicon oxide film 2 formed at this time is, for example, 9 nm.

Step S20: Formation of the silicon nitride film 3 Subsequently, the silicon nitride film 3 is deposited on the silicon oxide film 2. The silicon nitride film 3 can be deposited by, for example, a CVD method. The film thickness of the silicon nitride film 3 is, for example, 120 nm.

Step S30: Formation of Element Isolation Groove Subsequently, a resist (not shown) is formed on the silicon nitride film 3 and patterned. Using the patterned resist as a mask, the silicon nitride film 3, the silicon oxide film 2, and the semiconductor substrate 1 are sequentially dry etched to form element isolation grooves in the semiconductor substrate 1.

Step S40; Formation of Element Isolation Oxide Film Subsequently, a silicon oxide film is deposited on the semiconductor substrate 1. The silicon oxide film is deposited so as to fill the element isolation trench. The silicon oxide film at this time can be deposited using, for example, a CVD method. Further, the element isolation oxide film 4 embedded in the element isolation trench is formed by polishing the silicon oxide film deposited other than the element isolation trench using the CMP method. Further, the thickness of the element isolation oxide film 4 is adjusted using hydrofluoric acid. A cross-sectional view after the element isolation oxide film 4 is formed is shown in FIG.

  Steps S50 to S80 will be described.

Step S50: Deposition of the silicon nitride film 5 The silicon nitride film 3 is removed using hot phosphoric acid. Then, a silicon nitride film 5 is deposited on the silicon oxide film 2. The silicon nitride film 5 can be deposited by, for example, a CVD method. The film thickness of the silicon nitride film 5 is, for example, 120 nm.

Step S60: Forming an opening in the silicon nitride 5 Subsequently, a resist (not shown) is formed on the silicon nitride film 5 and patterned. At this time, the resist is patterned so that openings are provided at positions to be gate grooves and capacitor grooves. Using the patterned resist as a mask, the silicon nitride film 5 is etched to form an opening reaching the silicon oxide film 2.

Step S70: Formation of Side Wall Mask Subsequently, after removing the resist, a silicon nitride film is deposited using the CVD method. Then, the deposited silicon nitride film is subjected to anisotropic dry etching on the entire surface. Thereby, the silicon nitride film 6 remains only on the side wall of the opening.

Step S80: Formation of Gate Groove and Capacitor Groove Subsequently, the silicon oxide film 2 and the semiconductor substrate 1 are dry-etched using the silicon nitride films 5 and 6 as a mask. By this step, the gate groove 7a is formed in the MISFET formation region of the semiconductor substrate 1, and the capacitor groove 7b is formed in the capacitor formation region. A cross-sectional view after the gate groove 7a and the capacitor groove 7b are formed is shown in FIG.

  Steps S90 to S110 will be described.

Step S90: Removal of the silicon nitride films 5 and 6 The silicon nitride films 5 and 6 are removed by hot phosphoric acid. Furthermore, cleaning and sacrificial oxidation are performed to remove contamination and damage caused by substrate processing.

Step S100: Impurity Implantation Subsequently, a resist is formed, and using this as a mask, impurity implantation is performed by, for example, ion implantation. A P-type impurity such as boron is implanted into a region where the memory cell and the N-channel MISFET are formed, and a P-type impurity layer 8 is formed on the surface side of the semiconductor substrate 1. On the other hand, N-type impurities such as phosphorus and arsenic are implanted into the capacitor formation region, and an N-type impurity layer is formed on the surface side of the semiconductor substrate 1. This N-type impurity layer becomes the capacitor lower electrode 9. Although not shown, an N-type impurity layer is formed by implanting an N-type impurity in the region where the P-channel MISFET is formed, as in the capacitor formation region.

  Impurity implantation in this step (S100) is not limited as long as the MISFET exhibits a desired operation and the lower electrode of the capacitor can be formed, and the impurity implantation process and the impurity profile can be changed. That is, the impurity may be implanted by a method other than the ion implantation method. A P-type impurity other than boron may be used. Other than phosphorus and arsenic can be used as the N-type impurity.

Step S110: Formation of Gate Insulating Film and Capacitor Dielectric Film Subsequently, the semiconductor substrate 1 is thermally oxidized. By this thermal oxidation, a silicon oxide film is formed on the surface. This silicon oxide film is formed following the gate groove 7a and the capacitor groove 7b. The silicon oxide film formed in the MISFET formation region becomes the gate insulating film 10a, and the silicon oxide film formed in the capacitor formation region becomes the capacitor dielectric film 10b. A cross-sectional view after the gate insulating film 10a and the capacitor dielectric film 10b are formed is shown in FIG.

  When the semiconductor device 100 includes a plurality of MISFETs having different gate insulating film thicknesses, each of the capacitor dielectric films formed in the plurality of capacitor grooves is formed in any MISFET gate insulating film forming step. By taking these into consideration, the capacitor dielectric film thickness can be varied. That is, the capacitance and breakdown voltage of the capacitor dielectric film can be adjusted to desired values.

  When the gate insulating film 10a and the capacitor dielectric film 10b have different thicknesses, the other may be etched while either one is masked.

  Steps S120 to S140 will be described.

Step S120: Deposition of Polycrystalline Silicon Film Polycrystalline silicon film 11 is deposited on gate insulating film 10a and capacitor dielectric film 10b. The polycrystalline silicon film 11 is deposited so as to fill the gate trench 7a and the capacitor trench 7b. The polycrystalline silicon film 11 can be deposited by, for example, a CVD method.

Step S130: Deposition of Tungsten Film 12 Subsequently, the tungsten film 12 is deposited on the polycrystalline silicon film 11. The tungsten film 12 can be deposited by sputtering, for example.

Step S140: Deposition of the silicon nitride film 13 and the silicon oxide film 14 Subsequently, the silicon nitride film 13 and the silicon oxide film 14 are deposited in this order on the tungsten film 12. The silicon nitride film 13 and the silicon oxide film 14 can be deposited by, for example, a CVD method. FIG. 6 shows a cross-sectional structure of the semiconductor device after the silicon oxide film 14 is deposited.

  The steps from S150 to S180 will be described.

Step S150: Patterning of silicon nitride film 13 and silicon oxide film 14 A resist (not shown) is formed on the silicon oxide film 14 and patterned. The silicon oxide film 14 and the silicon nitride film 13 are sequentially dry etched using the patterned resist as a mask. At this time, the silicon oxide film 14 and the silicon nitride film 13 which have not been removed serve as a mask when processing the gate electrode and the capacitor upper electrode.

Step S160: Opening in Tungsten Subsequently, the tungsten film 12 is etched using the silicon oxide film 14 as a mask. By this etching, an opening that penetrates the tungsten film 12 and reaches the upper surface of the polycrystalline silicon film 11 is formed.

Step S170: Silicon nitride deposition on the tungsten side Next, a silicon nitride film is deposited on the silicon oxide film 14 over the entire surface, and anisotropic etching is performed to form the silicon nitride film 15 on the tungsten film 12 side.

Step S180; Etching of Polycrystalline Silicon Subsequently, the polycrystalline silicon film 11 is etched using the silicon nitride films 13 and 15 as a mask. The portions of the polycrystalline silicon film 11 and the tungsten film 12 that are not removed by etching are the gate electrode 16a and the capacitor upper electrode 16b. FIG. 7 shows a cross-sectional structure of the semiconductor device after the gate electrode 16a and the capacitor upper electrode 16b are formed.

Step S190: Formation of Source / Drain Region The capacitor formation region is covered with a resist (not shown). Then, an N-type impurity such as arsenic is implanted into the MISFET formation region by ion implantation. Thereby, an N-type impurity layer that becomes the source / drain region 17 of the MISFET is formed in a self-aligned manner.

  Subsequently, a silicon nitride film is deposited on the entire surface of the MISFET formation region and the capacitor formation region by a CVD method, and the entire surface is etched to form a silicon nitride film 18 on the sides of the gate electrode 16a and the capacitor upper electrode 16b. Let it form. Then, an N-type impurity such as phosphorus is implanted into the MISFET formation region and the capacitor formation region by an ion implantation method. As a result, an N-type impurity layer to be the source / drain region 19a of the MISFET and an N-type impurity layer to be the capacitor lower electrode pulling portion diffusion layer 19b are formed in a self-aligned manner. A subsequent cross-sectional view is shown in FIG.

  Steps S200 to S210 will be described.

Step S200: Formation of Interlayer Insulating Film 20 A silicon oxide film is deposited on the entire surface of the MISFET formation region and the capacitor formation region by the CVD method. Then, the interlayer insulating film 20 is formed by planarizing the surface by CMP.

Step S210: Formation of Connection Hole Subsequently, a resist is formed on the interlayer insulating film 20 and patterned. The interlayer insulating film 20 is dry-etched using the patterned resist as a mask. Thereby, a connection hole that penetrates the interlayer insulating film 20 and reaches the source / drain region 19a of the MISFET is formed. Further, a silicon nitride film is deposited on the interlayer insulating film 20 including the inside of the connection hole by a CVD method, and anisotropic silicon etching is performed to form the silicon nitride film 21 on the side wall of the connection hole. Further, a polycrystalline silicon film containing impurities is deposited on the interlayer insulating film 20 including the connection holes by using a CVD method. Next, the polycrystalline silicon film on the interlayer insulating film 20 is removed by CMP to leave the polycrystalline silicon only in the connection hole. The polycrystalline silicon film remaining in this connection hole becomes plugs 22a and 22b. FIG. 9 shows a cross-sectional structure after the plugs 22a and 22b are formed.

  Steps S220 to S230 will be described.

Step S220: Formation of Interlayer Insulating Film 23 A silicon oxide film is deposited on the interlayer insulating film 20 and the plugs 22a and 22b by using the CVD method to form the interlayer insulating film 23.

Step S230: Formation of Plugs 24a, 24b, and 24c Subsequently, a resist is formed on the interlayer insulating film 23 and patterned. Using the patterned resist as a mask, the interlayer insulating film 23 is etched to form a lead-out wiring hole of the plug 22a and a hole reaching the N-type impurity region 20b serving as a diffusion layer of the capacitor lower electrode pulling portion 19b. . Further, using the patterned resist as a mask, the interlayer insulating film 23, the interlayer insulating film 20, and the silicon nitride film 13 are sequentially dry etched to form a connection hole reaching the tungsten film 12 of the capacitor upper electrode 16b. Then, a TiN film and a Ti film are deposited on the interlayer insulating film 23 by sputtering. Further, a tungsten film is deposited on the Ti film using the CVD method. Thus, plugs 24a, 24b, and 24c made of a tungsten film, a Ti film, and a TiN film are formed in each hole provided in the interlayer insulating film 23.

  In step S230 described above, the hole for the plug 24a and the hole for the 24b are the same process, and the hole for the plug 24c is a separate process. This is the process of connecting the peripheral circuit of the DRAM to the MISFET. This is because it is assumed to be connected to the capacitor upper electrode, and is not necessarily performed in a separate process. It is also possible to form the holes for the plugs 24a, 24b, 24c in the same process.

  As described above, the semiconductor device 100 having the structure shown in FIG. 2 is formed by the operations in steps S10 to S230. According to the manufacturing method of the semiconductor device according to the present embodiment, in the process of S80, the gate groove 7a and the capacitor groove 7b are not formed in separate processes, but are formed in the same process. The process is simplified.

  Further, since the gate insulating film 10a and the capacitor dielectric film 10b are made of the same material, the gate insulating film 10a and the capacitor dielectric film 10b can be formed in the same process in the process of S110.

  Further, since the gate electrode 16a and the capacitor upper electrode 16b are made of the same material, the gate electrode 16a and the capacitor upper electrode 16b can be formed in the same process in the processing of S120 to S180.

  In the case where the capacitor forming groove and the element isolation groove are formed in the same process as in the conventional example shown in the cited document 2, in the step of embedding an oxide film in the element isolation groove, the capacitor groove is also formed in the capacitor groove. A silicon oxide film is buried. Therefore, the silicon oxide film embedded in the capacitor formation groove is removed and a new capacitor dielectric film is formed, or the silicon oxide film embedded in the capacitor formation groove is processed to follow the capacitor formation groove. There is a need to. On the other hand, in the present embodiment, since the gate trench and the capacitor trench are formed in the same process, there is no need to add such a process, which is advantageous from the viewpoint of simplifying the manufacturing process.

It is a top view of the semiconductor device concerning the present invention. It is sectional drawing of the semiconductor device concerning this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device concerning this invention. It is a figure which shows the operation | movement flow of the manufacturing method of the semiconductor device concerning this invention. It is a figure which shows the operation | movement flow of the manufacturing method of the semiconductor device concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Silicon oxide film 3 Silicon nitride film 4 Element isolation oxide film 5 Silicon nitride film 6 Silicon nitride film 7a Gate groove 7b Capacitor groove 8 P-type impurity layer 9 Capacitor lower electrode 10a Gate insulating film 10b Capacitor dielectric film 11 Polycrystal Silicon film 12 Tungsten film 13 Silicon nitride film 14 Silicon oxide film 15 Silicon nitride film 16a Gate electrode 16b Capacitor upper electrode 17 Source / drain region 18 Silicon nitride film 19a Source / drain region 19b Capacitor lower electrode pull-up diffusion layer 20 Interlayer insulating film 21 silicon nitride film 22a plug 22b plug 23 interlayer insulating film 24a plug 24b plug 24c plug 30A MISFET
30B Capacitor 100 Semiconductor Device

Claims (10)

A method of manufacturing a semiconductor device having a MISFET having a trench-type gate electrode and a trench-type capacitor,
A groove forming step of simultaneously forming a gate groove for embedding the gate electrode of the MISFET and a capacitor forming groove for forming the capacitor;
A method for manufacturing a semiconductor device comprising: A method of manufacturing a semiconductor device according to claim 1,
Furthermore,
A method of manufacturing a semiconductor device, comprising: an insulating film forming step of simultaneously forming a gate insulating film of the MISFET and a capacitor dielectric film of the capacitor. A method of manufacturing a semiconductor device according to claim 2,
The method for manufacturing a semiconductor device, wherein the gate insulating film and the capacitor dielectric film are silicon oxide films. A method of manufacturing a semiconductor device according to any one of claims 1 to 3,
Furthermore,
A method of manufacturing a semiconductor device comprising an electrode forming step of simultaneously forming a gate electrode of the MISFET and an upper electrode of the capacitor. A method of manufacturing a semiconductor device according to claim 4,
The electrode forming step includes
Stacking polycrystalline silicon on the gate insulating film and the capacitor dielectric film;
Stacking tungsten on the polycrystalline silicon;
A method for manufacturing a semiconductor device comprising: A MISFET having a trench-type gate electrode;
A groove-type capacitor;
Comprising
A semiconductor device in which the gate electrode and the upper electrode of the capacitor are formed of the same material. A semiconductor device according to claim 6,
Furthermore,
A semiconductor device in which a gate insulating film of the MISFET and a capacitor dielectric film of the capacitor are formed of the same material. A semiconductor device according to claim 7,
The semiconductor device, wherein the gate insulating film and the capacitor dielectric film are silicon oxide films. A semiconductor device according to any one of claims 6 to 8,
A semiconductor device in which a gate electrode of the MISFET and an upper electrode of the capacitor are formed of the same material. A semiconductor device according to claim 9, wherein
The gate electrode and the upper electrode of the capacitor are:
Polycrystalline silicon provided on the gate insulating film and the capacitor dielectric film;
Tungsten provided on the polycrystalline silicon;
A semiconductor device.

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