US20100199144A1 - Method and device for indicating an uncorrectable data block - Google Patents

Method and device for indicating an uncorrectable data block Download PDF

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Publication number
US20100199144A1
US20100199144A1 US12/798,546 US79854610A US2010199144A1 US 20100199144 A1 US20100199144 A1 US 20100199144A1 US 79854610 A US79854610 A US 79854610A US 2010199144 A1 US2010199144 A1 US 2010199144A1
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United States
Prior art keywords
data
character
data blocks
synchronization
blocks
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/798,546
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English (en)
Inventor
Jing Li
Dongyu Geng
Dongning Feng
Raymond W.K. Leung
Frank Effenberger
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
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Assigned to HUAWEI TECHNOLOGIES CO., LTD. reassignment HUAWEI TECHNOLOGIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: EFFENBERGER, FRANK, FENG, DONGNING, GENG, DONGYU, LI, JING, LEUNG, RAYMOND W.K.
Publication of US20100199144A1 publication Critical patent/US20100199144A1/en
Priority to US13/473,196 priority Critical patent/US8560914B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission
    • H04B10/2507—Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/25—Arrangements specific to fibre transmission
    • H04B10/2581—Multimode transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0079—Formats for control data
    • H04L1/0082—Formats for control data fields explicitly indicating existence of error in data being transmitted, e.g. so that downstream stations can avoid decoding erroneous packet; relays

Definitions

  • synchronization character and control character of the two line coding mechanisms utilize a scrambler, where the synchronization character and control character of the two line coding mechanisms bypass the scrambler, i.e. the synchronization character does not change.
  • a two-bit synchronization character (synchronization header) is added on the basis of 64-bit information.
  • the two-bit synchronization character has only two values, “01” and “10”.
  • the synchronization character “01” indicates that all of the 64-bit information is data information
  • the synchronization character “10” indicates that the 64-bit information includes data information and control information.
  • the synchronization character “00” or “11” indicates that error occurs during the transmission.
  • the RS Reconciliation Sublayer
  • the data received from the 10 GIGABIT MEDIA INDEPENDENT INTERFACE (XGMII) by the Reconciliation Sublayer (RS) includes a control character /E/, it indicates that error occurs to the received data where the /E/ locates.
  • the RS needs to preprocess the received data.
  • One of processing methods is to replace part of the data so that the error can be checked by CRC.
  • FIG. 13 is a data structure diagram of the synchronization header of any block of the data portion of the FEC codeword is set to “00” or “11” according to a second embodiment of the present invention
  • FIG. 18 is another data structure diagram of an FEC codeword after synchronization headers of multiple blocks including the first and last blocks of the data portion of the FEC codeword are set to “1” according to the third embodiment of the present invention.
  • each block is input to the descrambler, the data information of the block changes, but synchronization header bits of the block bypass the descrambler such that the synchronization header bits do not change.
  • Each descrambled block including the synchronization header and descrambled data information is then sent to a line decoder.
  • the line decoder detects errors within part or all of blocks according to the synchronization characters of part or all of the blocks having a value of “11” or “00” or according to the synchronization characters of a part or all of the blocks having a value of “10” or “1” but control characters included in the part or all of the blocks do not conform with a line decoding rule.
  • the line decoder replaces the descrambled data of the part or all of the blocks, and outputs the decoded data.
  • synchronization headers of part or all of blocks of the data portion of the FEC codeword as illustrated in FIG. 4 are set to a control synchronization character “10” or an invalid synchronization header “00” or “11”, in order to indicate the uncorrectable data block.
  • the synchronization header recovery process is not required and the setting of synchronization header can be performed in the FEC decoding module. If the FEC decoding fails, in order to indicate that error occurs, synchronization headers of part of blocks of the FEC codeword as illustrated in FIG. 4 are set to a control block synchronization header “10” or an invalid synchronization header “00” or “11”, for indicating the uncorrectable data block.
  • a data structure of the FEC decoding output after the setting is illustrated in FIG. 13 .
  • a data structure of the FEC decoding output after the setting is illustrated in FIG. 14 .
  • a data structure of the FEC decoding output after the setting is illustrated in FIG. 15 .
  • a data structure of the FEC decoding output after the setting is illustrated in FIG. 16 .
  • a third embodiment provides a method for setting a synchronization header once an FEC decoding fails if a 64 / 65 b line coding is employed at the physical layer and two bits of the synchronization header involve in the FEC coding,
  • the synchronization header is in the form of only “0” or “1”, where “0” indicates that 64 bits are all data information, and “1” indicates that 64 bits includes data information and control information. Therefore, only “1” may be used to set synchronization header to indicate the uncorrectable data block once the FEC decoding fails.
  • the line decoding module replaces part or all blocks with /E/ by replacing all eight bytes of each block with /E/, thereby indicating the uncorrectable data block by utilizing /E/, so that the MAC layer can detect the error via its own CRC verification.
  • the device includes a first character setting module and a line decoding module, and may further include a descrambling module.
  • the descrambling module is adapted to descramble data information of each block containing the first character before the line decoding module decodes the data block containing the first character.
  • the first character setting module may further include a control character setting module, which is adapted to set synchronization characters of part or all of data blocks of the error data to a synchronization character of a data block including control information.
  • a control character setting module which is adapted to set synchronization characters of part or all of data blocks of the error data to a synchronization character of a data block including control information.
  • the synchronization character is to be set to “10”.
  • the synchronization character is to be set to “1”.
  • the first character setting module may include both of the illegal character setting module and the control character setting module.
  • the line decoding module may include the first decoding module, which is adapted to determine part or all of data blocks of the error data with illegal synchronization characters, replace the descrambled data information of the part or all of data blocks, then output the replaced data; or determine part or all of data blocks of the error data with legal synchronization characters and perform line decoding on the part or all of blocks, then output decoded blocks.
  • the first decoding module is adapted to replace the descrambled data of the part or all of data blocks, perform line decoding on the part or all of data blocks, and output the replaced data, after the first decoding module determines the part or all of data blocks of the error data with illegal synchronization characters;
  • the embodiment of the present invention provides an easy and effective mechanism for indicating the uncorrectable data block to the line decoding module in the case of failure of FEC decoding. Therefore, the line decoding module can utilize the existing error report function of the control character /E/ of the Ethernet system to report error to the RS layer where the error data can be preprocessed, so that the MAC layer can detect the error via its own CRC verification.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Error Detection And Correction (AREA)
US12/798,546 2008-01-14 2010-04-06 Method and device for indicating an uncorrectable data block Abandoned US20100199144A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/473,196 US8560914B2 (en) 2008-01-14 2012-05-16 Method and device for indicating an uncorrectable data block

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN200810056163.6 2008-01-14
CN200810056163.6A CN101488827B (zh) 2008-01-14 2008-01-14 实现数据报错的方法和装置
PCT/CN2008/073506 WO2009092231A1 (zh) 2008-01-14 2008-12-15 实现数据报错的方法和装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2008/073506 Continuation WO2009092231A1 (zh) 2008-01-14 2008-12-15 实现数据报错的方法和装置

Related Child Applications (1)

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US13/473,196 Continuation US8560914B2 (en) 2008-01-14 2012-05-16 Method and device for indicating an uncorrectable data block

Publications (1)

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US20100199144A1 true US20100199144A1 (en) 2010-08-05

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US12/798,546 Abandoned US20100199144A1 (en) 2008-01-14 2010-04-06 Method and device for indicating an uncorrectable data block
US13/473,196 Active US8560914B2 (en) 2008-01-14 2012-05-16 Method and device for indicating an uncorrectable data block

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US (2) US20100199144A1 (ja)
EP (1) EP2187566B1 (ja)
JP (2) JP5006351B2 (ja)
KR (1) KR101023463B1 (ja)
CN (1) CN101488827B (ja)
AT (1) ATE554552T1 (ja)
HK (1) HK1130376A1 (ja)
WO (1) WO2009092231A1 (ja)

Cited By (5)

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US20140341577A1 (en) * 2013-05-15 2014-11-20 Broadcom Corporation Ethernet Passive Optical Network Over Coaxial (EPoC) System Rate Mechanism
US20170075760A1 (en) * 2015-09-11 2017-03-16 Arm Limited Error protection
US20210152284A1 (en) * 2018-08-03 2021-05-20 Sony Corporation Transmission apparatus and method, receiving apparatus and method for latency reduction using fec packets at mac layer
US11245490B2 (en) 2017-12-01 2022-02-08 Huawei Technologies Co., Ltd. Data encoding method and apparatus, data decoding method and apparatus, OLT, ONU, and PON system
US11387940B2 (en) 2018-03-31 2022-07-12 Huawei Technologies Co., Ltd. Transmitting fragments of ethernet frame with indicating error occurring in ethernet frame

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KR101278651B1 (ko) * 2012-11-12 2013-06-25 스텝시스템주식회사 인쇄회로기판의 설계오류 검사방법 및 그 시스템
US10164733B2 (en) * 2014-06-30 2018-12-25 International Business Machines Corporation Integrated physical coding sublayer and forward error correction in networking applications
CN110474718B (zh) * 2019-08-30 2021-10-19 烽火通信科技股份有限公司 一种数据编码方法、同步方法、系统及通信系统
CN113938247A (zh) * 2020-07-14 2022-01-14 中国移动通信有限公司研究院 一种码块处理方法、节点及介质

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US6650638B1 (en) * 2000-03-06 2003-11-18 Agilent Technologies, Inc. Decoding method and decoder for 64b/66b coded packetized serial data
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US20060143548A1 (en) * 2004-04-05 2006-06-29 Delregno Nick Error detection and reporting
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140341577A1 (en) * 2013-05-15 2014-11-20 Broadcom Corporation Ethernet Passive Optical Network Over Coaxial (EPoC) System Rate Mechanism
US9148224B2 (en) * 2013-05-15 2015-09-29 Broadcom Corporation Ethernet passive optical network over coaxial (EPoC) system rate mechanism
US20170075760A1 (en) * 2015-09-11 2017-03-16 Arm Limited Error protection
US10108486B2 (en) * 2015-09-11 2018-10-23 Arm Limited Error protection
US11245490B2 (en) 2017-12-01 2022-02-08 Huawei Technologies Co., Ltd. Data encoding method and apparatus, data decoding method and apparatus, OLT, ONU, and PON system
US11387940B2 (en) 2018-03-31 2022-07-12 Huawei Technologies Co., Ltd. Transmitting fragments of ethernet frame with indicating error occurring in ethernet frame
US11799587B2 (en) 2018-03-31 2023-10-24 Huawei Technologies Co., Ltd. Transmitting fragments of ethernet frame with indicating error occurring in ethernet
US20210152284A1 (en) * 2018-08-03 2021-05-20 Sony Corporation Transmission apparatus and method, receiving apparatus and method for latency reduction using fec packets at mac layer

Also Published As

Publication number Publication date
JP5522547B2 (ja) 2014-06-18
US8560914B2 (en) 2013-10-15
EP2187566B1 (en) 2012-04-18
CN101488827A (zh) 2009-07-22
JP2012161103A (ja) 2012-08-23
CN101488827B (zh) 2015-07-08
EP2187566A1 (en) 2010-05-19
WO2009092231A1 (zh) 2009-07-30
KR20090078313A (ko) 2009-07-17
ATE554552T1 (de) 2012-05-15
JP5006351B2 (ja) 2012-08-22
JP2009239897A (ja) 2009-10-15
EP2187566A4 (en) 2011-06-29
US20120257887A1 (en) 2012-10-11
KR101023463B1 (ko) 2011-03-24
HK1130376A1 (en) 2009-12-24

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