US20080317154A1 - Semiconductor integrated circuit device and radio frequency module - Google Patents

Semiconductor integrated circuit device and radio frequency module Download PDF

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Publication number
US20080317154A1
US20080317154A1 US11/765,236 US76523607A US2008317154A1 US 20080317154 A1 US20080317154 A1 US 20080317154A1 US 76523607 A US76523607 A US 76523607A US 2008317154 A1 US2008317154 A1 US 2008317154A1
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Prior art keywords
coupled
node
antenna
transistors
signal
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Inventor
Akishige Nakajima
Yasushi Shigeno
Takashi Ogawa
Shinnichirou Takatani
Shinya Osakabe
Tomoyuki Ishikawa
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Renesas Electronics Corp
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Renesas Technology Corp
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Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OGAWA, TAKASHI, TAKATANI, SHINNICHIROU, ISHIKAWA, TOMOYUKI, NAKAJIMA, AKISHIGE, OSAKABE, SHINYA, SHIGENO, YASUSHI
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION MERGER AND CHANGE OF NAME Assignors: RENESAS TECHNOLOGY CORP.
Priority to US12/910,071 priority Critical patent/US8824974B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H04B1/0053—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band
    • H04B1/006—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges with common antenna for more than one band using switches for selecting the desired band
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H03K17/005—Switching arrangements with several input- or output terminals with several inputs only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H03K17/007—Switching arrangements with several input- or output terminals with several outputs only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K2017/066—Maximizing the OFF-resistance instead of minimizing the ON-resistance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

Definitions

  • the present invention relates to a semiconductor integrated circuit device and a radio frequency module and, more particularly, to a technique effectively applied to a semiconductor integrated circuit device and a radio frequency module including an antenna switch mounted on a mobile communication device or the like.
  • Japanese Unexamined Patent Publication No. Hei 8 discloses an SPDT (Single Pole Double Throw) switch formed by an FET.
  • a dual gate FET is used as the FET, a capacitive element is coupled between a first gate and the source, and a capacitive element is coupled between a second gate and the drain.
  • a radio frequency switch (antenna switch) having a low distortion characteristic and capable of operating with low voltage can be realized.
  • reference document 1 Japanese Unexamined Patent Publication No. 2006-165224
  • reference document 2 Japanese Unexamined Patent Publication No. 2007-005970
  • reference document 3 Japanese Unexamined Patent Publication No. 2007-067762
  • reference document 4 Japanese Unexamined Patent Publication No. 2007-067720
  • a cellular phone system is developing for realizing higher functions such as voice communication and the wireless Internet with the advent of the second-generation cellular phone and, moreover, TV telephone and voice (sound) and video distribution by using wireless Internet with the advent of the third-generation cellular phone.
  • EDGE Enhanced Data rate for GMS Evolution
  • GSM Global System for Mobile Communications
  • W-CDMA Wideband Code Division Multiple Access
  • the frequency band is also widened as the number of subscribers increases and the variety of communication methods increases.
  • EGSM Extended GSM
  • DCS Digital Cellular System
  • PCS Personal Communication Service
  • W-CDMA Wideband Code Division Multiple Access
  • 2 GHz band is added, and the multi bands and multi modes are essential conditions of a cellular phone.
  • radio frequency modules such as a high frequency power amplifier (HPA) module are requested to have multi-bands and multi-modes and realize miniaturization.
  • HPA high frequency power amplifier
  • a high-performance switch device capable of switching a plurality of high frequency signals is demanded.
  • an antenna switch mounted on a radio frequency module is having higher functions such as SP 4 T and SP 6 T from SPDT so as to address such requirements for multi bands and multi modes.
  • An antenna switch is requested to have high linearity due to introduction of GSM using phase modulation and, in addition, EDGE using phase modulation and amplitude modulation, and main technical tasks are miniaturization and a distortion reducing technique.
  • An example of circuit means realizing distortion reduction is FETs coupled in multiple stages (a multi-gate configuration is effective from the viewpoint of prevention of an insertion loss), as devices for coupling/decoupling between a receiver and an antenna like an FET 2 in FIG. 1 in the patent document 1.
  • an FET in the off state (the FET 2 in FIG. 1 in the patent document 1) is not turned on. Consequently, the power supplied from the transmitter is output to the antenna without being leaked to a reception system, so that a low-loss switch can be realized for the following reasons.
  • multi-stage coupling an RF voltage applied to the FET is dispersed and the RF voltage per stage can be reduced.
  • gate-source capacitance Cgs
  • gate-drain capacitance Cgd
  • RF voltage applied to an on resistor as causes of harmonic distortion decrease. Therefore, the FET in the off state is not erroneously turned on by power input from the transmitter.
  • a technique of providing a potential supply line at an intermediate point of the gates of a dual gate FET can be mentioned.
  • intermediate potential is stabilized, so that harmonic distortion can be reduced.
  • the reference document 2 by changing a method of coupling the potential supply line in the reference document 1, amount of a potential drop caused by leak current is suppressed, and harmonic distortion is further reduced.
  • a booster circuit is provided for the gate of an FET for further reducing distortion.
  • GSM voice communication
  • EDGE Data communication
  • the antenna switch has to increase the circuit scale from conventional SP 6 T to SP 7 T. Since the W-CDMA system is a system adapted to high-speed data communication, it is requested to have high linearity (low distortion) in a band wider than the conventional one.
  • IMD intermodulation distortion
  • FIG. 5 is a simplified block diagram showing an example of the configuration of a W-CDMA unit.
  • a transmission system (transmission terminal) Tx and a reception system (reception terminal) Rx for W-CDMA are coupled to an antenna switch circuit SW via a duplexer DUP.
  • the problem in the configuration is that an out-of-band blocker signal (disturbing wave) entering from an antenna is mixed with a Tx signal having transmission frequency of Tx in the W-CDMA band due to nonlinearity of the antenna switch circuit SW, and a distortion signal is leaked to an Rx signal band.
  • the leakage amount is called IMD and has to be reduced.
  • IMD is an extremely small value as ⁇ 90 dBm or less as compared with ⁇ 40 dBm or less of high-order harmonic distortion (second-order: 2HD, and third-order: 3HD) as a distortion characteristic requested for the GSM and PCS bands.
  • second-order: 2HD, and third-order: 3HD high-order harmonic distortion
  • the high-order harmonic distortion is caused mainly by a device in an off state (a device for coupling/decoupling between the antenna and the transmission system or the reception system).
  • a device in an off state a device for coupling/decoupling between the antenna and the transmission system or the reception system.
  • the IMD occurrence mechanism is the same as that of high-order harmonic distortion.
  • the major part of the distortion is distortion caused by nonlinear elements of an off-state device (mainly, nonlinearity of voltage dependence of gate-source capacitance and gate-drain capacitance).
  • FIGS. 6A , 6 B, and 6 C show an example of a switch circuit examined as the ground of the present invention.
  • FIG. 6A is a circuit diagram showing a configuration example of the switch circuit
  • FIG. 6B is an equivalent circuit diagram of on devices
  • FIG. 6C is a diagram illustrating an operation example.
  • the switch circuit shown in FIG. 6A has a transistor Q 1 between an antenna terminal ANT and a signal terminal Tx 1 a , and a transistor Q 2 between ANT and a signal terminal Tx 2 a .
  • the transistor Q 1 is turned on when a control voltage Vdd (approximately 3.0V) is applied to the gate, and the transistor Q 2 is turned off when 0V is applied to the gate.
  • Vdd approximately 3.0V
  • An equivalent circuit of Q 1 in an on state can be expressed by a Schottky diode, an on resistor (Ron), and the like as shown in FIG. 6B .
  • Vdd When Vdd is applied to the gate, the Schottky diode is forward-biased and becomes conductive, and voltage is applied to the antenna terminal ANT.
  • Ileak When current leaked via the gate and source and the gate and drain of the transistor Q 2 in the off state is Ileak, the forward voltage of the Schottky diode is Vf, and a resistive element coupled to the gate of Q 1 is Rg_Q 1 , the relation between the antenna voltage Vant and Vdd is expressed as the following equation (1).
  • Vant Vdd ⁇ Rg — Q 1 ⁇ I leak ⁇ Vf Equation (1)
  • Vf is approximately 0.4V
  • Rg_Q 1 is approximately 15 k ⁇
  • Ileak is approximately 10 ⁇ A.
  • the gate-source voltage Vgs (gate-drain voltage Vgd) of the transistor Q 2 in the off state is designed to become ⁇ Vant which is deeper than a pinch-off voltage Vth (approximately ⁇ 1.0V).
  • Vth pinch-off voltage
  • Vgs Vgd
  • the voltage dependency of the gate-source capacitance Cgs of Q 2 has nonlinearity shown in FIG. 6C .
  • the distortion (1MD, 2HD, and 3HD) occurs due to the nonlinearity or a pseudo on state of Q 2 caused when Vgs becomes close to Vth.
  • Methods of reducing distortion include (1) to decrease the high frequency voltage Vin/2 of Vgs, (2) to deepen ⁇ Vant so as to be apart from Vth, (3) to reduce the voltage dependency of Cgs, and (4) to make Vth shallow so as to be apart from ⁇ Vant.
  • solving methods which can be realized with a circuit configuration are the methods (1) and (2).
  • FIGS. 7A and 7B show an example of the configuration and operation as a modification of the switch circuit of FIG. 6 .
  • FIG. 7A is a circuit diagram showing a configuration example
  • FIG. 7B is a diagram illustrating an operation example of FIG. 7A .
  • a switch circuit shown in FIG. 7A has a configuration obtained by replacing the transistor Q 2 in FIG. 6A with, for example, single-gate transistors Q 2 _ 1 , Q 2 _ 2 , and Q 2 _ 3 coupled in three stages. Since Vin is unchanged, high frequency voltage applied to one stage of Q 2 _ 1 is 1 ⁇ 3. As shown in FIG. 7B , Vgs has 1 ⁇ 3 as large as that in the 1-stage configuration and has a small voltage amplitude, and the switch circuit can operation in a region where voltage nonlinearity of Cgs is low. Since Vgs can be separated from Vth, a deep off-state can be assured, and distortion can be reduced.
  • the multi-stage coupling (or multi-gate configuration) has the relation of a tradeoff with an insertion loss in the on state.
  • the inventors of the present invention have examined and found that a triple-gate two-stage configuration (equivalent to six stages of single gates) is optimum.
  • V′ant in a circuit configuration of SP 7 T, for example, V′ant is approximately 1.9V
  • a region of high nonlinearity of Cgs and a pseudo on region are created, and distortion increases.
  • An object of the present invention is to provide a semiconductor integrated circuit device and a radio frequency module realizing reduced high-order harmonic distortion or IMD.
  • a semiconductor integrated circuit device has a configuration that, in a antenna switch having an antenna node, a plurality of signal nodes, and a plurality of transistors coupled between the antenna node and the signal nodes, voltage is supplied from a voltage supply node to which bias voltage is applied to at least two signal nodes out of the signal nodes via resistive elements.
  • the bias voltage can be supplied to the antenna node from the voltage supply node via the parallel coupling of the resistive elements and the transistors (the resistive elements between the sources and drains).
  • a transistor in an off state enters a deeper off state without becoming a pseudo on state and operates in a region where nonlinearity of Cgs is low, so that high-order harmonic distortion or IMD can be reduced.
  • the resistance value of the resistive element coupled to the voltage supply node can be set to be larger than that in the case of supplying the bias voltage directly to the antenna node via the resistive element, so that the influence on the high-order harmonic distortion or IMD caused by the resistive element itself can be reduced.
  • the plurality of signal nodes include a signal node for the W-CDMA method of a low frequency band, a signal node for a frequency band higher than the low frequency band, and a signal node for the GSM method using power higher than that of the W-CDMA method, it is sufficient to use the W-CDMA method of the low frequency band as one of signal nodes selected.
  • the semiconductor integrated circuit device has a common transistor for coupling a plurality of reception nodes to an antenna node, it is sufficient to select, as another signal node to be selected, a node on the side opposite to the side of the antenna node in the common transistor.
  • FIG. 1 is a circuit diagram illustrating a basic concept of a semiconductor integrated circuit device as an embodiment of the invention.
  • FIG. 2 is a block diagram illustrating an example of the general configuration of the semiconductor integrated circuit device as the embodiment of the invention.
  • FIG. 3 is a circuit diagram showing a detailed configuration example of a switch circuit in the semiconductor integrated circuit device in FIG. 2 .
  • FIGS. 4A to 4C are cross sections each schematically showing a device structure at each of manufacturing stages as an example of a method of manufacturing a resistive element and a triple gate transistor in a voltage supply circuit shown in FIG. 3 .
  • FIG. 5 is a simplified block diagram illustrating a configuration example of a W-CDMA unit.
  • FIGS. 6A to 6C show an example of a switch circuit examined as the pre-condition of the present invention, in which FIG. 6A is a circuit diagram showing an example of the configuration of the switch circuit, FIG. 6B is an equivalent circuit device of an on-device in FIG. 6A , and FIG. 6C is a diagram showing an example of the operation of the circuit.
  • FIGS. 7A and 7B show an example of the configuration and operation of a modification of the switch circuit of FIGS. 6A to 6C , and respectively show a circuit diagram showing an example of the configuration, and a diagram showing an example of the operation.
  • the elements are not always essential except for the case where an element is clearly specified as an essential one or is obviously essential.
  • the shape, position, and the like of a component include similar shapes and similar positions except for the case where the shape, position, and the like are clearly specified or obviously limited. This rule also applies to the numerical values and the ranges.
  • FIG. 1 is a circuit diagram showing the basic concept of a semiconductor integrated circuit device as an embodiment of the invention.
  • the semiconductor integrated circuit device shown in FIG. 1 includes, for example, transistors Qa whose sources and drains are coupled between an antenna terminal (antenna node) ANT and a signal terminal (signal node) Txa, transistors Qb whose sources and drains are coupled between the antenna terminal ANT and a signal terminal Rxb, and transistors Qc whose sources and drains are coupled between the antenna terminal ANT and a signal terminal Rxc.
  • the signal terminal Txa is a transmission terminal (transmission node)
  • the signal terminals Rxb and Rxc are reception terminals (reception nodes).
  • the signal terminals Rxb and Rxc are coupled to terminating resistors of 50 ⁇ or the like via capacitative elements Cb and Cc, respectively.
  • the transistors Qa are, for example, single-gate transistors Q 1 a , Q 2 a , and Q 3 a coupled in three stages.
  • Resistive elements Rg 1 a , Rg 2 a , and Rg 3 a are coupled to the gates of the transistors Q 1 a , Q 2 a , and Q 3 a , respectively.
  • Resistive elements Rd 1 a , Rd 2 a , and Rd 3 a are coupled between the source and drain of Q 1 a , Q 2 a , and Q 3 a , respectively.
  • the transistors Qb and Qc are also single-gate transistors Q 1 b , Q 2 b , and Q 3 b coupled in three stages and single-gate transistors Q 1 c , Q 2 c , and Q 3 c coupled in three stages, respectively.
  • Resistive elements Rg 1 b , Rg 2 b , and Rg 3 b are coupled to the gates of the transistors Q 1 b , Q 2 b , and Q 3 b , respectively.
  • Resistive elements Rd 1 b , Rd 2 b , and Rd 3 b are coupled between the source and drain of Q 1 b , Q 2 b , and Q 3 b , respectively.
  • Resistive elements Rg 1 c , Rg 2 c , and Rg 3 c are coupled to the gates of the transistors Q 1 c , Q 2 c , and Q 3 c , respectively.
  • Resistive elements Rd 1 c , Rd 2 c , and Rd 3 c are coupled between the source and drain of Q 1 c , Q 2 c , and Q 3 c , respectively.
  • the semiconductor integrated circuit device of FIG. 1 is mainly characterized in that a voltage supply circuit VD_BK is coupled to the signal terminals Rxb and Rxc.
  • the voltage supply circuit VD_BK is constructed by a voltage supply terminal (voltage supply node and voltage) Vdd, a resistive element Radd 1 coupling Vdd and Rxb, and a resistive element Radd 2 coupling Vdd and Rxc.
  • a method of directly supplying bias voltage to the antenna terminal ANT is considered.
  • a usable voltage is only Vdd (approximately 3.0V) same as the control voltage for turning on/off transistors. Therefore, a circuit for supplying the voltage Vdd directly to the antenna terminal ANT via a resistor having a high resistance value may be used. The issues rising in this case are the coupling position and the resistance value of the resistor.
  • the resistance value is desired to be as large as possible so as not to exert an influence on a high frequency signal due to the resistance value itself.
  • the resistance value has to be set to 100 k ⁇ or larger so as not to exert an influence on higher-order harmonic distortions (2HD and 3HD). Therefore, in the coupling position of a circuit REF shown in FIG. 1 or the like, without exerting an influence is exerted on the high-order harmonic distortion, it is difficult to determine the value of a proper resistive element Radd for making Vant close to 2.7V.
  • Means for solving the problem is, like the voltage supply voltage VD_BK in FIG. 1 , to provide resistive elements for the signal terminal Rxb coupled to the antenna terminal ANT via the transistors Qb and the signal terminal Rxc coupled to the antenna terminal ANT via the other transistors Qc and supply voltage to the terminals via the resistive elements.
  • the state is equivalent to a state where the two resistive elements Radd 1 and Radd 2 are coupled in parallel via the resistive elements Rd coupled between the drains and sources of the transistors Qb (Q 1 b , Q 2 b , and Q 3 b ) and the transistors Qc (Q 1 c , Q 2 c , and Q 3 c ) which are off. Therefore, the resistance value of each of the resistive elements Radd 1 and Radd 2 can be set to, for example, 100 k ⁇ corresponding to twice as large as 50 k ⁇ .
  • the resistive elements are coupled in parallel from the voltage supply terminal Vdd to the two signal terminals.
  • the resistive elements can be also coupled in parallel from the voltage supply terminal Vdd to three or more signal terminals.
  • the resistance value of each of the resistive elements can be further increased.
  • the circuit area increases accordingly, and it is feared that unnecessary reactance components such as parasitic capacitance and parasitic inductance increase. From the viewpoint, it is desirable to provide two signal terminals to which the resistive elements are coupled. Since the actual resistive elements have a reactance component, it is effective to couple the resistive element to a signal terminal using a low frequency band or a signal terminal having passing power.
  • the antenna voltage Vant which drops due to leak current can be increased.
  • the transistors Qb (Q 1 b , Q 2 b , and Q 3 b ) and Qc (Q 1 c , Q 2 c , and Q 3 c ) in the off state enter a deeper off state, and operate in a region where nonlinearity of Cgs is small without entering a false on state.
  • high-order harmonic distortion or IMD can be reduced. Since the resistive elements coupled to the signal terminals have a large resistance value (for example, 100 k ⁇ ), a characteristic degradation in high-order harmonic distortion or IMD caused by the resistive elements themselves does not become an issue.
  • FIG. 2 is a block diagram showing an example of the general configuration of the semiconductor integrated circuit device as an embodiment of the invention.
  • An example of the semiconductor integrated circuit device shown in FIG. 2 is a radio frequency module RF_ML used in a cellular phone as one of the radio communication systems.
  • the radio frequency module RF_ML includes a power amplifying unit HPA_ML, a signal processing unit RF_IC, SAW (Surface Acoustic Wave) filters SAW 1 to SAW 3 , power amplifiers W_PA 1 and W_PA 2 for W-CDMA, and duplexers DUP 1 and DUP 2 .
  • RF_IC includes low noise amplifiers LNA 1 to LNA 5 .
  • HPA_ML includes power amplifiers HPA 1 and HPA 2 , low pass filters LPF 1 and LPF 2 , a control unit CNT_IC, and a switch circuit SW.
  • the switch circuit SW has a so-called SP 7 T configuration of coupling any of the seven signal terminals (transmission terminals Tx 1 and Tx 2 , reception terminals Rx 2 to Rx 4 , and transmission/reception terminals TRx 1 and TRx 5 ) to the antenna terminal ANT to which the antenna is coupled.
  • the signal terminal to be coupled is selected by the control unit CNT_IC on the basis of a control signal from a baseband circuit (not shown).
  • a transmission signal in the PCS system or DCS system using the 1.71 GHz to 1.91 GHz band is amplified by HPA 1 , and the amplified signal is input to the transmission terminal Tx 1 via LPF 1 .
  • a transmission signal in the GSM system using the 900 MHz band is amplified by HPA 2 , and the amplified signal is input to the transmission terminal Tx 2 via LPF 2 .
  • a selected one of the transmission signals is selected by the control unit CNT_IC and output via the antenna terminal ANT.
  • the control unit CNT_IC also controls the amplification factor of HPA 1 or HPA 2 and the like on the basis of a control signal from the baseband circuit.
  • a signal having a specific frequency (PCS: 1.9 GHz band) is selected by SAW 1 among reception signals input to the reception terminal Rx 4 from the antenna terminal ANT, and amplified by LNA 1 .
  • the amplified signal is output to a demodulation circuit (not shown) and the like.
  • a reception signal having a specific frequency (DCS: 1.8 GHZ band) is selected by SAW 2 and amplified by LNA 2 .
  • a reception signal having a specific frequency (GSM: 900 MHz band) is selected by SAW 3 and amplified by LNA 5 .
  • the amplified signals are output to the not-shown demodulation circuit and the like.
  • a transmission signal in the W-CDMA system using the 2.1 GHz band is amplified by W_PA 1 .
  • the amplified signal undergoes discrimination of transmission/reception signals in DUP 1 and is input to the transmission/reception terminal TRx 1 .
  • the signal is output via ANT.
  • the reception signal input from ANT to TRx 1 undergoes discrimination in DUP 1 and is amplified by LNA 3 , and the amplified signal is output to a not-shown demodulation circuit and the like.
  • a transmission signal in the W-CDMA system using the 900 MHz band is amplified by W_PA 2 .
  • the amplified signal undergoes discrimination of transmission/reception signals in DUP 2 and is input to the transmission/reception terminal TRx 5 . According to selection of CNT_IC, the signal is output via ANT. On the other hand, the reception signal input from ANT to TRx 5 undergoes discrimination in DUP 1 and is amplified by LNA 4 , and the amplified signal is output to a not-shown demodulation circuit and the like.
  • FIG. 3 is a circuit diagram showing a detailed configuration example of the switch circuit in the semiconductor integrated circuit device of FIG. 2 .
  • the switch circuit SW shown in FIG. 3 has Tx 1 for PCS/DCS transmission, Tx 2 for GSM transmission, antenna terminal (antenna node) ANT, TRx 5 for W-CDMA (900 MHz band) transmission/reception, TRx 1 for W-CDMA (2.1 GHz band) transmission/reception, Rx 4 for PCS reception, Rx 3 for DCS reception, and Rx 2 for GSM reception.
  • a transistor circuit Q_t 1 made of triple-gate transistors Q_t 11 and Q_t 12 in two stages is coupled between Tx 1 and ANT.
  • a transistor circuit Q 5 _t 1 made of double-gate transistors Q 5 _t 11 and Q 5 _t 12 coupled in two stages is coupled between Tx 1 and the ground terminal GND.
  • a transistor circuit Q_t 2 made of triple-gate transistors Q_t 21 and Q_t 22 in two stages is coupled between Tx 2 and ANT.
  • a transistor circuit Q 5 _t 2 made of double-gate transistors Q 5 _t 21 and Q 5 _t 22 in two stages is coupled between Tx 2 and GND.
  • a transistor circuit Q_tr 5 made of triple-gate transistors Q_tr 51 and Q_tr 52 in two stages is coupled between TRx 5 and ANT.
  • a transistor circuit Q 5 _tr 5 made of triple-gate transistors Q 5 _tr 51 and Q 5 _tr 52 in two stages is coupled between TRx 5 and GND.
  • a transistor circuit Q_tr 1 made of triple-gate transistors Q_tr 11 and Q_tr 12 in two stages is coupled between TRx 1 and ANT.
  • a transistor circuit Q 5 _tr 1 made of triple-gate transistors Q 5 _tr 11 and Q 5 _tr 12 in two stages is coupled between TRx 1 and GND.
  • a transistor circuit Qcom made of triple-gate transistors Qcom 1 and Qcom 2 in two stages is coupled between ANT and a reception common node Ncom.
  • a single-gate transistor Q_r 2 is coupled between the reception common node Ncom and Rx 2
  • a single-gate transistor Q 5 _r 2 is coupled between Rx 2 and GND.
  • a single-gate transistor Q_r 3 is coupled between Ncom and Rx 3
  • a single-gate transistor Q 5 _r 3 is coupled between Rx 3 and GND.
  • a single-gate transistor Q_r 4 is coupled between Ncom and Rx 4
  • a single-gate transistor Q 5 _r 4 is coupled between Rx 4 and GND.
  • a transistor (or transistor circuit) Q to be coupled to ANT and a transistor (or transistor circuit) Q 5 to be coupled to GND are provided for each of the signal terminals. Since high power is applied to the transistors Q_ ⁇ l, Q_t 2 , Q_tr 1 , Q_tr 5 , and Qcom, the transistors have the triple-gate two-stage configuration (corresponding to single transistors in six stages) for reducing distortion.
  • the number of gates or the number of stages are basically similar although they may vary according to the influence of such distortion, passing power, and the like. Consequently, the configuration of the transistors Q_tr 1 and Q 5 _ ⁇ l, as a representative, coupled to the transmission terminal Tx 1 will be described in detail. The others will be briefly described. First, in Q_ ⁇ l, one end of the source and drain of Q_t 11 is coupled to ANT, one end of the source and drain of Q_t 12 is coupled to Tx 1 , and the other end of Q_t 11 and the other end of Q_t 12 are commonly coupled.
  • the three gates of Q_t 11 are coupled to a control terminal Tx 1 c L via resistive elements Rg 1 , Rg 2 , and Rg 3 .
  • a capacitive element C 3 is coupled between one end (on the ANT side) of the source and drain of Q t 11 and a gate closest to the one end.
  • the three gates of Q_t 12 are coupled to Tx 1 c L via resistive elements Rg 4 , Rg 5 , and Rg 6 .
  • a capacitive element C 4 is coupled between one end (on the Tx 1 side) of the source and drain of Q_t 12 and a gate closest to the one end.
  • Resistive elements Rd 1 , Rd 2 , and Rd 3 are coupled in series between one end and the other end of the source and drain of Q_t 11 .
  • a bias is supplied to an intermediate point of two gates in Q_t 11 from a connection node between Rd 1 and Rd 2 and a connection node between Rd 2 and Rd 3 .
  • resistive elements Rd 4 , Rd 5 , and Rd 6 are coupled in series between one end and the other end of the source and drain of Q_t 12 .
  • a bias is supplied to an intermediate point of two gates in Q_t 12 from a connection node between Rd 4 and Rd 5 and a connection node between Rd 5 and Rd 6 .
  • the multi-gate configuration addition of the capacitive elements, and supply of bias to the intermediate point between two gates, the low distortion characteristic as described in the patent document 1 and the reference documents 1 to 4 can be realized.
  • the configuration of coupling transistors in multiple stages high frequency voltage applied per stage can be lowered.
  • high-order harmonic distortion can be reduced.
  • a control voltage input from the control unit CNT_IC to the control terminal Tx 1 c in FIG. 1 is applied via a diode D 1 (the Tx 1 c side is the anode and the Tx 1 c L side is the cathode).
  • the diode D 1 has the function of preventing backflow from the gate of Q_t 1 as described in the reference document 4. Since high power is input to the transmission terminal Tx 1 , a booster circuit CP 1 is coupled between the gate of Q_ ⁇ l and Tx 1 . By CP 1 , the gate voltage for turning on Q_ ⁇ l can be boosted.
  • Q 5 _t 1 one end of the source and drain of Q 5 _t 11 is coupled to Tx 1 (accurately, an AC signal is coupled via a capacitor C 5 ), one end of the source and drain of Q 5 _t 12 is coupled to GND (accurately, an AC signal is coupled via a capacitor C 6 ), and the other end of Q 5 _t 11 and the other end of Q 5 _t 12 are commonly coupled.
  • Each of the transistors Q 5 _t 11 and Q 5 _t 12 has a double-gate configuration. Each of the gates is coupled to GND via a resistive element.
  • a capacitive element is coupled between one end (on the Tx 1 side) of the source and drain of Q 5 _t 11 and the gate close to the one end.
  • a capacitive element is also coupled between one end (on the GND side) of the source and drain of Q 5 _t 12 and the gate close to the one end.
  • two resistive elements are coupled in series between the source and drain of each of Q 5 _t 11 and Q 5 _t 12 . From the connection node of the resistive elements, a bias is supplied to an intermediate point of the gates.
  • the transistor circuit Q 5 _t 1 is turned off when the ‘H’ level voltage is applied to Tx 1 c L and the transistor circuit Q_ ⁇ l is turned on.
  • the transistor circuit Q 5 _ ⁇ l is turned on when the ‘L’ level voltage is applied to Tx 1 c L and the transistor circuit Q_ ⁇ l is turned off. Therefore, when Q_t 1 is turned off, Tx 1 is coupled to GND, the influence of impedance (for example, LPF 1 and the like) after Tx 1 can be concealed, and distortion and the like accompanying fluctuations in the impedance can be prevented.
  • impedance for example, LPF 1 and the like
  • the transistor circuits Q_t 2 and Q 5 _t 2 coupled to the transmission terminal Tx 2 have a configuration similar to that of the transistors Q_t 1 and Q 5 _ ⁇ l.
  • the on/off state of Q_t 2 and the on/off state of Q 5 _t 2 are controlled by a control terminal Tx 2 c L coupled to the gate of Q_t 2 and one end of the source and drain of Q 5 _t 2 .
  • Tx 2 c L a control voltage input from the control unit CNT_IC to the control terminal Tx 2 c in FIG. 1 is applied via a diode D 2 for preventing backflow. Since high power is input to Tx 2 in a manner similar to Tx 1 , a booster circuit CP 2 is coupled between Tx 2 and the gate of Q_t 2 in a manner similar to Q_ ⁇ l.
  • the transistor circuits Q_tr 5 and Q 5 _tr 5 coupled to the transmission/reception terminal TRx 5 have configurations similar to those of the transistors Q_tr 1 and Q 5 _ ⁇ l except that Q 5 _tr 5 has a configuration of triple-gate transistors in two stages.
  • the on/off state of Q_tr 5 and the on/off state of Q 5 _tr 5 are controlled by a control terminal Rx 5 c coupled to the gate of Q_tr 5 and one end of the source and drain of Q 5 _tr 5 .
  • a diode for preventing backflow is not necessary for Rx 5 c , and a control voltage is directly applied from the control unit CNT_IC in FIG. 1 to Rx 5 c .
  • a booster circuit as described above is not provided for the gate of Q_tr 5 for the reason that, since an RF power input to TRx 5 at the time of transmission is small, the booster circuit does not function fully, and the booster circuit may deteriorate the IMD characteristic.
  • the transistor circuits Q_tr 1 and Q 5 _tr 1 coupled to the transmission/reception terminal TRx 1 also have a configuration similar to that of the transistors Q_tr 5 and Q 5 _tr 5 .
  • the on/off state of Q_tr 1 and the on/off state of Q 5 _tr 1 are controlled by a control terminal Rx 1 c coupled to the gate of Q_tr 1 and one end of the source and drain of Q 5 _tr 1 .
  • a diode for preventing backflow is also not necessary for Rx 1 c , and a control voltage is directly applied from the control unit CNT_IC in FIG. 1 to Rx 1 c .
  • a booster circuit as described above is not provided for the gate of Q_tr 1 .
  • the transistor circuit Qcom coupled to the antenna ANT has a configuration of triple-gate transistors in two stages like the transistor circuit Q_ ⁇ l.
  • the gate voltage of the transistor circuit Qcom is controlled by a control terminal Rxcc coupled to the control unit CNT_IC in FIG. 1 .
  • the transistor circuit Qcom is turned on when a signal received from the antenna terminal ANT is coupled to any of the reception terminals Rx 2 , Rx 3 , and Rx 4 .
  • a load on the antenna terminal ANT is reduced, and the high-order harmonic distortion characteristic and the like can be improved.
  • the transistors Q_r 2 and Q 5 _r 2 coupled to the reception terminal Rx 2 are single-gate transistors. One end of the source and drain of Q_r 2 is coupled to the reception common node Ncom, the other end is coupled to Rx 2 , and the gate of Q_r 2 is coupled to the control terminal Rx 2 c via a resistive element. A control voltage is applied from the control unit CNT_IC in FIG. 1 to Rx 2 c . Although a resistive element is coupled between the source and drain of Q_r 2 , because of the single gate configuration, no bias to the intermediate point of the gates exists. Since the single gate configuration is used, it is unnecessary to couple a capacitive element between the gate and the source and drain.
  • an AC signal is coupled from one end of the source and drain of Q 5 _r 2 to Rx 2 , an AC signal is coupled from the other end to GND, and the gate of G 5 _r 2 is coupled to GND via the resistive element.
  • a resistive element is provided between the source and drain of Q 5 _r 2 .
  • the transistors Q_r 3 and Q 5 _r 3 coupled to the reception terminal RX 3 are also single-gate transistors and have a configuration similar to the above-described configuration of Q_r 2 and Q 5 _r 2 .
  • the on/off state of Q_r 3 and the on/off state of Q 5 _r 3 are controlled by a control terminal Rx 3 c coupled to the gate of Q_r 3 and one end of the source and drain of Q 5 _r 3 .
  • the transistors Q_r 4 and Q 5 _r 4 coupled to the reception terminal Rx 4 are also single-gate transistors and have a configuration similar to the above-described configuration of Q_r 2 and Q 5 _r 2 .
  • the on/off state of Q_r 4 and the on/off state of Q 5 _r 4 are controlled by a control terminal Rx 4 c coupled to the gate of Q_r 4 and one end of the source and drain of Q 5 _r 4 .
  • a control voltage is directly applied from the control unit CNT_ 1 in FIG. 1 .
  • the switch circuit SW of FIG. 3 is provided with a voltage supply circuit VD_BK 1 similar to the voltage supply circuit in FIG. 1 between TRx 5 for W-CDMA (900 MHz band) transmission/reception and the reception common node Ncom as one end of the transistor circuit Qcom.
  • VD_BK 1 is constructed by the voltage supply terminal (voltage supply node, voltage) Vdd, a resistive element Radd 5 coupled between Vdd and TRx 5 , and a resistive element Rddc coupled between Vdd and Ncom.
  • the resistance value of each of the resistive elements Radd 5 and Raddc is, for example, 100 k ⁇ .
  • a parasitic component such as parasitic capacitance or parasitic inductance exists in the actual resistive element. It is therefore effective to couple the resistive element to a signal terminal of a low frequency band on which the influence of the parasitic component is small or a signal terminal in which passing power is small. Accordingly, among the signal terminals and the nodes in the switch SW in FIG. 3 , TRx 5 as the signal terminal for the W-CDMA system of low transmission power and a low frequency band (900 MHz band) and the reception common node Ncom on which the influence of high power in the GSM band is reduced by Qcom and in which only a small power signal passes are optimum.
  • the resistive elements Radd 5 and Raddc In the case of forming the resistive elements Radd 5 and Raddc on the semiconductor substrate, to generate 100 k ⁇ as standard sheet resistance (for example, 500 ⁇ / ⁇ ), the length of about 0.8 mm is necessary.
  • the cellular phone system as shown in FIG. 2 is strongly requested to achieve a large chip area and low chip cost, so that it is desirable to reduce the number of resistive elements as much as possible. Therefore, although the resistive elements may be disposed in three or more positions as described with reference to FIG. 1 , from the above-described viewpoints, it is most desirable to dispose the resistive elements in two positions shown in FIG. 3 .
  • the resistance value of each of the resistive elements Radd 5 and Raddc is set to 100 k ⁇ or higher from the viewpoint that no influence is exerted on harmonic distortion and an insertion loss of an on-transistor is permissible.
  • the resistance value of 100 k ⁇ which is the smallest in the range is used from the viewpoint of realizing deepening of ⁇ Vant in the range with a small area.
  • the optimum range of the resistance value varies according to various circuit parameters, process parameters, further, chip area parameters, and the like.
  • the suitable range of the resistance value is, for example, 100 k ⁇ to 200 k ⁇ , desirably, 100 k ⁇ to 150 k ⁇ .
  • the antenna voltage Vant dropped due to leak current can be increased, and a transistor in an off state operates in a region where nonlinearity of Cgs is small without entering a false on state.
  • high-order harmonic distortion or IMD can be reduced. Since the resistive elements coupled to the signal terminals have a large resistance value (for example, 100 k ⁇ ) and a signal of relatively low power and/or low frequency is applied to the signal terminals, a characteristic degradation in high-order harmonic distortion or IMD caused by coupling of the resistive elements does not become an issue.
  • the transistors Q_ ⁇ l, Q_t 2 , Q_tr 5 , Qcom, and Q_tr 1 in FIG. 3 have the triple-gate two-stage configuration, as described above with reference to FIG. 7 and the like, the high frequency voltage of Vgs can be lowered so that high-order harmonic distortion and IMD can be reduced. Further, by setting the number of resistive elements to be added to two, area overhead can be reduced, and increase in the area of the radio frequency module RF_ML in FIG. 2 can be suppressed. In addition, reduction in distortion of the switch circuit can be realized. Consequently, design margin of the other parts (the low-pass filter LPF, the power amplifier HPA, and the like) in RF_ML in FIG. 2 is increased, and the cost of RF_ML can be lowered.
  • FIGS. 4A , 4 B, and 4 C are cross sections schematically showing a device structure in manufacturing steps as an example of a method of manufacturing a resistive element and a triple-gate transistor in the voltage supply circuit of FIG. 3 .
  • an epitaxial layer EP made of GaAs is formed over a substrate SUB made of semi-insulating gallium arsenide (GaAs), and a buffer layer LY 1 is formed over the top face of the epitaxial layer EP.
  • GaAs semi-insulating gallium arsenide
  • LY 1 is formed over the top face of the epitaxial layer EP.
  • AlGaAs aluminum gallium arsenide
  • LY 2 is formed over the top face of the layer LY 2 .
  • an n-type gallium arsenide (GaAs) layer LY 3 is formed.
  • the AlGaAs layer LY 2 and the n-type GaAs layer LY 3 in a right part in FIG. 4A is etched and an insulating film IS 1 made of, for example, PSG (Phospho Silicate Glass)/SiO is formed.
  • the resistive element Radd made of, for example, WSiN is formed in the position where the layers LY 2 and LY 3 were etched.
  • the insulating film IS 1 in positions where source/drain lines SD 1 and SD 2 are to be disposed is etched, and the source/drain lines SD 1 and SD 2 are formed by metal wires or the like.
  • the insulating film LS 1 and the n-type GaAS layer LY 3 in the positions where three gate lines G 1 , G 2 , and G 3 are to be disposed in the area sandwiched by the source/drain lines SD 1 and SD 2 are etched, and the three gate lines G 1 , G 2 , and G 3 are formed by metal lines or the like.
  • the insulating film IS 1 between the gate lines G 1 and G 2 and between the gate lines G 2 and G 3 is etched, and power supply lines SH 12 and SH 23 made by an n + layer or the like are formed.
  • the power supply lines SH 12 and SH 23 a bias at an intermediate point between gates as described with reference to FIG. 3 is supplied. In such a manner, an HEMT (High Electron Mobility Transistor) and a resistive element having a triple-gate configuration as shown in FIG. 4 are formed.
  • HEMT High Electron Mobility Transistor
  • the invention has been described by using the example of the switch circuit used for a multi-band cellular phone system.
  • the invention is not limited to the switch circuit but can be similarly applied to various radio communication systems including a wireless LAN antenna switch adapted to a plurality of bands (for example, the 2.4 GHz band and 5 GHz band).
  • the semiconductor integrated circuit device and the radio frequency module according to the present invention are techniques particularly useful when applied to a switch circuit of SP 7 T or newer version and a radio frequency module for a cellular phone including the switch circuit.
  • the invention is not limited to them but can be widely applied to a switch circuit for a cellular phone of SP 6 T or older version, an antenna switch for a wireless LAN, and the like.

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Transceivers (AREA)
  • Electronic Switches (AREA)
  • Waveguide Switches, Polarizers, And Phase Shifters (AREA)
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TW200818594A (en) 2008-04-16
KR101394699B1 (ko) 2014-05-15
JP2008011131A (ja) 2008-01-17
US20110034137A1 (en) 2011-02-10
CN101098135B (zh) 2011-12-14
CN101098135A (zh) 2008-01-02
US8824974B2 (en) 2014-09-02
TWI459629B (zh) 2014-11-01
KR20080001668A (ko) 2008-01-03
JP4939125B2 (ja) 2012-05-23

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