US20080283979A1 - Semiconductor Package Having Reduced Thickness - Google Patents

Semiconductor Package Having Reduced Thickness Download PDF

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US20080283979A1
US20080283979A1 US11947505 US94750507A US2008283979A1 US 20080283979 A1 US20080283979 A1 US 20080283979A1 US 11947505 US11947505 US 11947505 US 94750507 A US94750507 A US 94750507A US 2008283979 A1 US2008283979 A1 US 2008283979A1
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Prior art keywords
leads
lead
surface
chip
paddle
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Abandoned
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US11947505
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Tae Heon Lee
Mu Hwan Seo
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Amkor Technology Inc
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Amkor Technology Inc
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • Y10T29/49121Beam lead frame or beam lead device

Abstract

A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • The present application is a continuation of U.S. application Ser. No. 11/492,481 entitled SEMICONDUCTOR PACKAGE HAVING REDUCED THICKNESS filed Jul. 25, 2006, which is a divisional of U.S. application Ser. No. 10/763,859 entitled SEMICONDUCTOR PACKAGE HAVING REDUCED THICKNESS filed Jan. 23, 2004 and issued as U.S. Pat. No. 7,115,445 on Oct. 3, 2006, which is a divisional of U.S. application Ser. No. 09/687,585 entitled SEMICONDUCTOR PACKAGE HAVING REDUCED THICKNESS filed Oct. 13, 2000 and issued as U.S. Pat. No. 6,696,747 on Feb. 24, 2004.
  • STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
  • Not Applicable
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor package and, more particularly, but not by way of limitation, to a semiconductor package that has a reduced thickness.
  • 2. History of Related Art
  • It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal leadframes for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the leadframe are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
  • As set forth above, the semiconductor package therein described incorporates a leadframe as the central supporting structure of such a package. A portion of the leadframe completely surrounded by the plastic encapsulant is internal to the package. Portions of the leadframe extend internally from the package and are then used to connect the package externally. More information relative to leadframe technology may be found in Chapter 8 of the book Micro Electronics Packaging Handbook, (1989), edited by R. Tummala and E. Rymaszewski. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y., which is herein incorporated by reference.
  • Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, which has resulted in increased consumer demand. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
  • According to such miniaturization tendency, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a size of about 1×1 mm.
  • One obstacle to reducing the thickness of conventional semiconductor packages is the internal leads are as thick as the chip paddle. Under the condition that the thickness of the internal leads is identical to that of the chip paddle, the bond pads on the semiconductor chip that is mounted onto the chip paddle are positioned at a far higher level than are the internal leads, so that the loop height of the conductive wires for connecting the semiconductor chip and the internal leads is elevated. The loop height results in an increase in a wire sweeping phenomenon that is caused by pressure of an encapsulation material during encapsulation of the package components.
  • Previously, techniques for reducing the thickness of semiconductor packages have been utilized, such as back-grinding techniques in which a semiconductor chip is ground down before being mounted on a chip paddle. The back-grinding process, however, deleteriously affects the semiconductor chip. For example, a semiconductor chip that is thinned in this manner is apt to undergo warping, which may result in damaging the internal integrated circuits. In addition, the semiconductor chip itself may be cracked during the back-grinding.
  • BRIEF SUMMARY OF THE INVENTION
  • The various embodiments of the present invention provide a semiconductor package that is extremely thin without the need for conducting a back-grinding process or at least for reducing the amount of back-grinding that is required. In one embodiment of the present invention, there is provided a semiconductor package comprising a semiconductor chip provided with a plurality of bond pads, a chip paddle bonded to the bottom surface of the semiconductor chip via an adhesive, a plurality of leads formed at regular intervals along the perimeter of the chip paddle and conductive wires for electrically connecting the bond pads of the semiconductor chip to the leads. A package body comprises the semiconductor chip, the conductive wires, the chip paddle and the leads that are preferably encapsulated by an encapsulation material. The chip paddle, the leads and the tie bars are externally exposed at their side surfaces and bottom surfaces. The chip paddle is half-etched over the entire upper surface of the chip paddle, which results in a thinner thickness than the leads. In one embodiment of the present invention, the half-etched chip paddle is about 25-75% as thick as the leads. Accordingly, by half-etching the entire upper surface of the chip paddle, the chip paddle itself is made thinner than the leads, leading to the slimming of the semiconductor package.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • A more complete understanding of the method and apparatus of the present invention may be obtained by reference to the following detailed description, with like reference numerals denoting like elements, when taken in conjunction with the accompanying drawings wherein:
  • FIG. 1 is a cutaway perspective view of a semiconductor package incorporating the improved leadframe assembly of the present invention;
  • FIG. 2 shows a cross section of a semiconductor package wherein the semiconductor package has a chip paddle of reduced thickness according to one embodiment of the present invention;
  • FIG. 3 shows a bottom plan view of the semiconductor package of FIG. 1;
  • FIG. 4 shows a cross section of a semiconductor package wherein the semiconductor package has a chip paddle of reduced thickness and including a half-etched section according to another embodiment of the present invention; and
  • FIG. 5 shows a bottom plan view of an alternative embodiment of a leadframe which may be integrated in the semiconductor package of the present invention.
  • The present invention may be understood more readily by reference to the following detailed description of preferred embodiments of the present invention and the figures.
  • DETAILED DESCRIPTION OF THE INVENTION
  • Referring now to FIGS. 1, 2 and 3, a representative semiconductor package embodying aspects of the present invention is designated generally 10. Semiconductor package 10 comprises a semiconductor chip 12. Semiconductor chip 12 has a plurality of bond pads 14 on an upper surface of semiconductor chip 12 and along the perimeter of semiconductor chip 12. A chip paddle 16 is bonded to a bottom surface of semiconductor chip 12 via an adhesive. At a corner of chip paddle 16 is a tie bar 20 (FIGS. 1 & 2), which extends outwards toward a respective corner of the semiconductor package 10. The tie bar 20 preferably also has a half-etched portion 21 (FIG. 1 and FIG. 5).
  • A plurality of leads 22 are located along the circumference of chip paddle 16. The chip paddle 16 and the leads 22 are externally exposed at their bottom surfaces (see FIG. 2). Additionally, the leads 22 are exposed on their side faces (see FIG. 1). The externally exposed portions of the chip paddle 16 and the leads 22 may be electroplated with a corrosion minimizing material such as, but not limited to, tin lead, gold, nickel palladium, tin bismuth, or other similar materials known in the art. Each of leads 22 has a half-etched portion 24 at an end facing the chip paddle 16. As seen in FIG. 5, the half-etched portion 24 of at least some of the leads 22 may have an angled configuration to facilitate the positioning thereof closer to the chip paddle 16. The upper surface of each of leads 22 may also be electroplated with an electrical conductivity enhancing material such as, for example, gold or silver. Conductive wires 26 provide an electrical pathway between the bond pads 14 of the semiconductor chip 12 and the leads 22. The semiconductor chip 12, the conductive wires 26, the chip paddle 16 and the leads 22 are encapsulated by an encapsulation material 28 to create a package body 30 whereas the chip paddle 16, the leads 22 and the tie bars 20 are externally exposed toward the downward direction of the semiconductor package 10. The encapsulation material 28 may be thermoplastics or thermoset resins, with the thermoset resins including silicones, phenolics, and epoxies.
  • An aspect of the various embodiments of the present invention resides in the formation of a half etched surface 32 over the entire upper surface of the chip paddle 16, so as to make the thickness of the chip paddle 16, designated h2 (FIG. 2), smaller than the thickness of the lead 22, which is designated h1 (FIG. 2). Preferably, the chip paddle 16 is about 25-75% as thick as the leads 22, but this range is presented for example only and should not be construed to limit the present invention. As shown in FIG. 4, in accordance with one embodiment of the present invention, the chip paddle 16 may include a half-etched section 33 which is located a lower edge 35 of the chip paddle 16. The half-etched section 33 extends to and at least partially circumvents the bottom surface 37 of the chip paddle 16. As seen in FIG. 5, the half-etched portion 21 of each tie bar 20 may extend to the half-etched section 33 of the chip paddle 16.
  • It is also preferred that the formation of the half-etched surface 32 over the entire upper surface of the chip paddle 16 is conducted while a lower side area of the lead 22 is etched, e.g., to form half etched portion 24. However, the present invention is not limited to etching the top surface of chip paddle 16 and the half etched portion 24 of the leads 22 simultaneously.
  • By half-etching the entire upper surface of the chip paddle 16, the total height of the semiconductor package body 30 is reduced. When semiconductor chip 12 is mounted on the half-etched surface 32 of the chip paddle 16, the semiconductor chip 12 is positioned at a lower height than the semiconductor chip 12 would be if it were located on a non-etched chip paddle 16. Thus, the loop height of the conductive wires 26 is also lowered. An additional benefit is that the lower loop height of the conductive wires 26 decreases an occurrence of wire sweeping during encapsulation of the semiconductor package 10. Further, the low height of the semiconductor chip 12 results in decreasing the thickness of the semiconductor package 10.
  • The present invention has been described in an illustrative manner, and it is to be understood the terminology used is intended to be in the nature of descriptions rather than of limitation. Many modifications and variations of the present invention are possible in light of the above teachings.
  • As described hereinbefore, the chip paddle 16 is made thinner than the leads 22 by half-etching the entire upper surface of the chip paddle 16, so that the total thickness of the semiconductor package 10 can be decreased. In addition, the height of semiconductor chip 12 with respect to the bottom surface of chip paddle 16 is reduced when the semiconductor chip 12 is mounted on the half-etched chip paddle 16. Consequently, the loop height of the conductive wires 26 is also lowered, which reduces wire sweeping during the encapsulation of the semiconductor package 10.
  • The following applications are being filed on the same date as the present application and are all incorporated by reference as if wholly rewritten entirely herein, including any additional matter incorporated by reference therein:
  • Patent/ First Named
    Ser. No. Title of Application Inventor
    6,646,339 Improved Thin and Heat Radiant Jae Hun Ku
    Semiconductor Package and Method for
    Manufacturing
    6,627,976 Leadframe for Semiconductor Package Young Suk
    and Mold for Molding the Same Chung
    6,475,827 Method for Making a Semiconductor Tae Heon Lee
    Package Having Improved Defect Testing
    and Increased Production Yield
    6,639308 Near Chip Size Semiconductor Package Sean Timothy
    Crowley
    6,677,663 End Grid Array Semiconductor Package Jae Hun Ku
    09/687,048 Leadframe and Semiconductor Package Tae Heon Lee
    with Improved Solder Joint Strength
    6,555,899 Semiconductor Leadframe Assembly and Young Suk
    Method of Manufacture Chung
    6,525,406 Semiconductor Device Having Increased Young Suk
    Moisture Path and Increased Solder Joint Chung
    Strength
  • It is this believed that the operation and construction of the present invention will be apparent from the foregoing description of the preferred exemplary embodiments. It will be obvious to a person of ordinary skill in the art that various changes and modifications may be made herein without departing from the spirit and the scope of the invention.

Claims (21)

  1. 1-11. (canceled)
  2. 12. A semiconductor package, comprising:
    a leadframe comprising:
    a chip paddle defining opposed, generally planar top and bottom surfaces and a half-etched section which at least partially circumvents the bottom surface, the chip paddle having a paddle thickness between the top and bottom surfaces thereof; and
    a plurality of leads extending at least partially about the chip paddle, each of the leads having:
    opposed, generally planar upper and lower lead surfaces and a lead thickness between the upper and lower lead surfaces thereof;
    an inner lead end; and
    a half-etched portion formed within the lower lead surface and extending to the inner lead end, the half-etched portion defining an etched lead surface which is disposed in opposed relation to the upper lead surface;
    the half-etched portion of at least some of the leads having an angled configuration;
    a semiconductor chip attached to the top surface of the chip paddle and electrically connected to at least one of the leads; and
    an encapsulation material at least partially encapsulating the leadframe and the semiconductor chip such that at least portions of the lower surfaces of the leads are exposed within the encapsulation material;
    wherein the chip paddle thickness is in the range of from about 25% to about 75% of the lead thickness of each of the leads.
  3. 13. The semiconductor package of claim 12 wherein the semiconductor chip is electrically connected to the upper lead surface of the at least one of the leads via a conductive wire which is encapsulated by the encapsulation material.
  4. 14. The semiconductor package of claim 12 wherein the bottom surface of the chip paddle is exposed within the encapsulation material and extends in generally co-planar relation to the lower lead surfaces of the leads.
  5. 15. The semiconductor package of claim 14 wherein the bottom surface of the chip paddle and the lower lead surfaces of the leads are each plated with a corrosion-minimizing material.
  6. 16. The semiconductor package of claim 12 wherein portions of the upper lead surfaces of each of the leads are exposed within the encapsulation material.
  7. 17. The semiconductor package of claim 12 wherein the leadframe further includes at least one tie bar attached to and extending from the chip paddle, the tie bar having:
    opposed, generally planar upper and lower tie bar surfaces; and
    a half-etched portion formed in the lower tie bar surface and defining an etched tie bar surface which is disposed in opposed relation to the upper tie bar surface.
  8. 18. The semiconductor package of claim 17 wherein:
    the tie bar and each of the leads each further have an outer end; and
    the outer ends and portions of the upper lead and tie bar surfaces are exposed within the encapsulation material.
  9. 19. The semiconductor package of claim 17 wherein the lower tie bar surface is exposed within the encapsulation material and extends in generally co-planar relation to the lower lead surfaces of the leads.
  10. 20. The semiconductor package of claim 19 wherein the bottom surface of the chip paddle is exposed within the encapsulation material and extends in generally co-planar relation to the lower lead and tie bar surfaces.
  11. 21. The semiconductor package of claim 20 wherein the bottom surface of the chip paddle and the lower lead and tie bar surfaces are each plated with a corrosion-minimizing material.
  12. 22. The semiconductor package of claim 17 wherein the etched tie bar surface extends in generally co-planar relation to the etched lead surface of each of the leads and the half-etched section of the chip paddle.
  13. 23. The semiconductor package of claim 12 wherein the lead thickness of each of the leads exceeds the paddle thickness such that the top surface of the chip paddle extends in generally co-planar relation to the etched lead surface of each of the leads.
  14. 24. The semiconductor package of claim 12 wherein the upper lead surface of the at least one of the leads is plated with an electrical conductivity enhancing material.
  15. 25. The semiconductor package of claim 12 wherein the semiconductor chip is secured to the top surface of the chip paddle via an adhesive.
  16. 26. A leadframe comprising:
    a chip paddle defining opposed, generally planar top and bottom surfaces and a half-etched section which at least partially circumvents the bottom surface, the chip paddle having a paddle thickness between the top and bottom surfaces thereof; and
    a plurality of leads extending at least partially about the die paddle, each of the leads having:
    opposed, generally planar upper and lower lead surfaces and a lead thickness between the upper and lower lead surfaces thereof;
    an inner lead end; and
    a half-etched portion formed within the lower lead surface and extending to the inner lead end, the half-etched portion defining an etched lead surface which is disposed in opposed relation to the upper lead surface;
    the half-etched portion of at least some of the leads having an angled configuration;
    wherein the chip paddle thickness is in the range of from about 25% to about 75% of the lead thickness of each of the leads.
  17. 27. The leadframe of claim 26 wherein the bottom surface of the chip paddle extends in generally co-planar relation to the lower lead surfaces of the leads.
  18. 28. The leadframe of claim 26 further including at least one tie bar attached to and extending from the chip paddle, the tie bar having:
    opposed, generally planar upper and lower tie bar surfaces; and
    a half-etched portion formed in the lower tie bar surface and defining an etched tie bar surface which is disposed in opposed relation to the upper tie bar surface.
  19. 29. The leadframe of claim 28 wherein the lower tie bar surface extends in generally co-planar relation to the lower lead surfaces of the leads.
  20. 30. The leadframe of claim 26 wherein the lead thickness of each of the leads exceeds the paddle thickness such that the top surface of the chip paddle extends in generally co-planar relation to the etched lead surface of each of the leads.
  21. 31. A semiconductor package, comprising:
    a leadframe comprising:
    a chip paddle defining opposed, generally planar top and bottom surfaces and a half-etched section which at least partially circumvents the bottom surface, the chip paddle having a paddle thickness between the top and bottom surfaces thereof; and
    a plurality of leads extending at least partially about the chip paddle, each of the leads having:
    opposed, generally planar upper and lower lead surfaces and a lead thickness between the upper and lower lead surfaces thereof;
    an inner lead end; and
    a half-etched portion formed within the lower lead surface and extending to the inner lead end, the half-etched portion defining an etched lead surface which is disposed in opposed relation to the upper lead surface;
    the half-etched portion of at least some of the leads having an angled configuration;
    a semiconductor chip attached to the top surface of the chip paddle and electrically connected to at least one of the leads; and
    an encapsulation material at least partially encapsulating the leadframe and the semiconductor chip such that at least portions of the lower surfaces of the leads are exposed within the encapsulation material;
    wherein the lead thickness of each of the leads exceeds the paddle thickness such that the top surface of the chip paddle extends in generally co-planar relation to the etched lead surface of each of the leads.
US11947505 1999-10-15 2007-11-29 Semiconductor Package Having Reduced Thickness Abandoned US20080283979A1 (en)

Priority Applications (6)

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KR19990044651A KR20010037247A (en) 1999-10-15 1999-10-15 Semiconductor package
KR99-44651 1999-10-15
US09687585 US6696747B1 (en) 1999-10-15 2000-10-13 Semiconductor package having reduced thickness
US10763859 US7115445B2 (en) 1999-10-15 2004-01-23 Semiconductor package having reduced thickness
US11492481 US7321162B1 (en) 1999-10-15 2006-07-25 Semiconductor package having reduced thickness
US11947505 US20080283979A1 (en) 1999-10-15 2007-11-29 Semiconductor Package Having Reduced Thickness

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11947505 US20080283979A1 (en) 1999-10-15 2007-11-29 Semiconductor Package Having Reduced Thickness

Related Parent Applications (1)

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US11492481 Continuation US7321162B1 (en) 1999-10-15 2006-07-25 Semiconductor package having reduced thickness

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US20080283979A1 true true US20080283979A1 (en) 2008-11-20

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US10763859 Active US7115445B2 (en) 1999-10-15 2004-01-23 Semiconductor package having reduced thickness
US11492481 Active US7321162B1 (en) 1999-10-15 2006-07-25 Semiconductor package having reduced thickness
US11947505 Abandoned US20080283979A1 (en) 1999-10-15 2007-11-29 Semiconductor Package Having Reduced Thickness

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US11492481 Active US7321162B1 (en) 1999-10-15 2006-07-25 Semiconductor package having reduced thickness

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US7115445B2 (en) 2006-10-03 grant

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